src/gpu-compute/qstruct.hh

   1 /*
   2  * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * For use for simulation and test purposes only
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its contributors
  18  * may be used to endorse or promote products derived from this software
  19  * without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * Author: Brad Beckmann, Marc Orr
  34  */
  35
  36 #ifndef __Q_STRUCT_HH__
  37 #define __Q_STRUCT_HH__
  38
  39 #include <bitset>
  40 #include <cstdint>
  41
  42 // Maximum number of arguments
  43 static const int KER_NUM_ARGS = 32;
  44 // Kernel argument buffer size
  45 static const int KER_ARGS_LENGTH = 512;
  46
  47 class LdsChunk;
  48 struct NDRange;
  49
  50 // Be very careful of alignment in this structure. The structure
  51 // must compile to the same layout in both 32-bit and 64-bit mode.
  52 struct HsaQueueEntry
  53 {
  54     // Base pointer for array of instruction pointers
  55     uint64_t code_ptr;
  56     // Grid Size (3 dimensions)
  57     uint32_t gdSize[3];
  58     // Workgroup Size (3 dimensions)
  59     uint32_t wgSize[3];
  60     uint16_t sRegCount;
  61     uint16_t dRegCount;
  62     uint16_t cRegCount;
  63     uint64_t privMemStart;
  64     uint32_t privMemPerItem;
  65     uint32_t privMemTotal;
  66     uint64_t spillMemStart;
  67     uint32_t spillMemPerItem;
  68     uint32_t spillMemTotal;
  69     uint64_t roMemStart;
  70     uint32_t roMemTotal;
  71     // Size (in bytes) of LDS
  72     uint32_t ldsSize;
  73     // Virtual Memory Id (unused right now)
  74     uint32_t vmId;
  75
  76     // Pointer to dependency chain (unused now)
  77     uint64_t depends;
  78
  79     // pointer to bool
  80     uint64_t addrToNotify;
  81     // pointer to uint32_t
  82     uint64_t numDispLeft;
  83
  84     // variables to pass arguments when running in standalone mode,
  85     // will be removed when run.py and sh.cpp have been updated to
  86     // use args and offset arrays
  87     uint64_t arg1;
  88     uint64_t arg2;
  89     uint64_t arg3;
  90     uint64_t arg4;
  91
  92     // variables to pass arguments when running in cpu+gpu mode
  93     uint8_t args[KER_ARGS_LENGTH];
  94     uint16_t offsets[KER_NUM_ARGS];
  95     uint16_t num_args;
  96 };
  97
  98 // State that needs to be passed between the simulation and simulated app, a
  99 // pointer to this struct can be passed through the depends field in the
 100 // HsaQueueEntry struct
 101 struct HostState
 102 {
 103     // cl_event* has original HsaQueueEntry for init
 104     uint64_t event;
 105 };
 106
 107 // Total number of HSA queues
 108 static const int HSAQ_NQUEUES = 8;
 109
 110 // These values will eventually live in memory mapped registers
 111 // and be settable by the kernel mode driver.
 112
 113 // Number of entries in each HSA queue
 114 static const int HSAQ_SIZE = 64;
 115 // Address of first HSA queue index
 116 static const int HSAQ_INDX_BASE = 0x10000ll;
 117 // Address of first HSA queue
 118 static const int HSAQ_BASE = 0x11000ll;
 119 // Suggested start of HSA code
 120 static const int HSA_CODE_BASE = 0x18000ll;
 121
 122 // These are shortcuts for deriving the address of a specific
 123 // HSA queue or queue index
 124 #define HSAQ(n) (HSAQ_BASE + HSAQ_SIZE * sizeof(struct fsaQueue) * n)
 125 #define HSAQE(n,i) (HSAQ_BASE + (HSAQ_SIZE * n + i) * sizeof(struct fsaQueue))
 126 #define HSAQ_RI(n) (HSAQ_INDX_BASE + sizeof(int) * (n * 3 + 0))
 127 #define HSAQ_WI(n) (HSAQ_INDX_BASE + sizeof(int) * (n * 3 + 1))
 128 #define HSAQ_CI(n) (HSAQ_INDX_BASE + sizeof(int) * (n * 3 + 2))
 129
 130 /*
 131  * Example code for writing to a queue
 132  *
 133  * void
 134  * ToQueue(int n,struct fsaQueue *val)
 135  * {
 136  *     int wi = *(int*)HSAQ_WI(n);
 137  *     int ri = *(int*)HSAQ_RI(n);
 138  *     int ci = *(int*)HSAQ_CI(n);
 139  *
 140  *     if (ci - ri < HSAQ_SIZE) {
 141  *         (*(int*)HSAQ_CI(n))++;
 142  *         *(HsaQueueEntry*)(HSAQE(n, (wi % HSAQ_SIZE))) = *val;
 143  *         (*(int*)HSAQ_WI(n))++;
 144  *     }
 145  * }
 146  */
 147
 148 #endif // __Q_STRUCT_HH__