src/gpu-compute/scalar_memory_pipeline.hh

   1 /*
   2  * Copyright (c) 2016-2017 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * For use for simulation and test purposes only
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived from this
  19  * software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * Authors: John Kalamatianos
  34  */
  35
  36 #ifndef __GPU_COMPUTE_SCALAR_MEMORY_PIPELINE_HH__
  37 #define __GPU_COMPUTE_SCALAR_MEMORY_PIPELINE_HH__
  38
  39 #include <queue>
  40 #include <string>
  41
  42 #include "gpu-compute/misc.hh"
  43 #include "params/ComputeUnit.hh"
  44 #include "sim/stats.hh"
  45
  46 /*
  47  * @file scalar_memory_pipeline.hh
  48  *
  49  * The scalar memory pipeline issues global memory packets
  50  * from the scalar ALU to the DTLB and L1 Scalar Data Cache.
  51  * The exec() method of the memory packet issues
  52  * the packet to the DTLB if there is space available in the return fifo.
  53  * This exec() method also retires previously issued loads and stores that have
  54  * returned from the memory sub-system.
  55  */
  56
  57 class ComputeUnit;
  58
  59 class ScalarMemPipeline
  60 {
  61   public:
  62     ScalarMemPipeline(const ComputeUnitParams *params);
  63     void init(ComputeUnit *cu);
  64     void exec();
  65
  66     std::queue<GPUDynInstPtr> &getGMReqFIFO() { return issuedRequests; }
  67     std::queue<GPUDynInstPtr> &getGMStRespFIFO() { return returnedStores; }
  68     std::queue<GPUDynInstPtr> &getGMLdRespFIFO() { return returnedLoads; }
  69
  70     bool
  71     isGMLdRespFIFOWrRdy() const
  72     {
  73         return returnedLoads.size() < queueSize;
  74     }
  75
  76     bool
  77     isGMStRespFIFOWrRdy() const
  78     {
  79         return returnedStores.size() < queueSize;
  80     }
  81
  82     bool
  83     isGMReqFIFOWrRdy(uint32_t pendReqs=0) const
  84     {
  85         return (issuedRequests.size() + pendReqs) < queueSize;
  86     }
  87
  88     const std::string &name() const { return _name; }
  89     void regStats();
  90
  91   private:
  92     ComputeUnit *computeUnit;
  93     std::string _name;
  94     int queueSize;
  95
  96     // Counters to track and limit the inflight scalar loads and stores
  97     // generated by this memory pipeline.
  98     int inflightStores;
  99     int inflightLoads;
 100
 101     // Scalar Memory Request FIFO: all global memory scalar requests
 102     // are issued to this FIFO from the scalar memory pipelines
 103     std::queue<GPUDynInstPtr> issuedRequests;
 104
 105     // Scalar Store Response FIFO: all responses of global memory
 106     // scalar stores are sent to this FIFO from L1 Scalar Data Cache
 107     std::queue<GPUDynInstPtr> returnedStores;
 108
 109     // Scalar Load Response FIFO: all responses of global memory
 110     // scalar loads are sent to this FIFO from L1 Scalar Data Cache
 111     std::queue<GPUDynInstPtr> returnedLoads;
 112 };
 113
 114 #endif // __GPU_COMPUTE_SCALAR_MEMORY_PIPELINE_HH__