riscv: Fix bugs with RISC-V decoder and detailed CPUs
[gem5.git] / src / gpu-compute / schedule_stage.hh
1 /*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Author: Sooraj Puthoor
34 */
35
36 #ifndef __SCHEDULE_STAGE_HH__
37 #define __SCHEDULE_STAGE_HH__
38
39 #include <utility>
40 #include <vector>
41
42 #include "gpu-compute/exec_stage.hh"
43 #include "gpu-compute/scheduler.hh"
44 #include "gpu-compute/scoreboard_check_stage.hh"
45
46 // Schedule or execution arbitration stage.
47 // From the pool of ready waves in the ready list,
48 // one wave is selected for each execution resource.
49 // The selection is made based on a scheduling policy
50
51 class ComputeUnit;
52 class Wavefront;
53
54 struct ComputeUnitParams;
55
56 class ScheduleStage
57 {
58 public:
59 ScheduleStage(const ComputeUnitParams *params);
60 ~ScheduleStage();
61 void init(ComputeUnit *cu);
62 void exec();
63 void arbitrate();
64 // Stats related variables and methods
65 std::string name() { return _name; }
66 void regStats();
67
68 private:
69 ComputeUnit *computeUnit;
70 uint32_t numSIMDs;
71 uint32_t numMemUnits;
72
73 // Each execution resource will have its own
74 // scheduler and a dispatch list
75 std::vector<Scheduler> scheduler;
76
77 // Stores the status of waves. A READY implies the
78 // wave is ready to be scheduled this cycle and
79 // is already present in the readyList
80 std::vector<std::vector<std::pair<Wavefront*, WAVE_STATUS>>*>
81 waveStatusList;
82
83 // List of waves which will be dispatched to
84 // each execution resource. A FILLED implies
85 // dispatch list is non-empty and
86 // execution unit has something to execute
87 // this cycle. Currently, the dispatch list of
88 // an execution resource can hold only one wave because
89 // an execution resource can execute only one wave in a cycle.
90 std::vector<std::pair<Wavefront*, DISPATCH_STATUS>> *dispatchList;
91
92 std::string _name;
93 };
94
95 #endif // __SCHEDULE_STAGE_HH__