src/gpu-compute/vector_register_file.hh

   1 /*
   2  * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
   3  * All rights reserved.
   4  *
   5  * For use for simulation and test purposes only
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived from this
  19  * software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef __VECTOR_REGISTER_FILE_HH__
  35 #define __VECTOR_REGISTER_FILE_HH__
  36
  37 #include "arch/gpu_isa.hh"
  38 #include "config/the_gpu_isa.hh"
  39 #include "debug/GPUVRF.hh"
  40 #include "gpu-compute/register_file.hh"
  41 #include "gpu-compute/wavefront.hh"
  42
  43 struct VectorRegisterFileParams;
  44
  45 // Vector Register File
  46 class VectorRegisterFile : public RegisterFile
  47 {
  48   public:
  49     using VecRegContainer = TheGpuISA::VecRegContainerU32;
  50
  51     VectorRegisterFile(const VectorRegisterFileParams *p);
  52     ~VectorRegisterFile() { }
  53
  54     virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override;
  55     virtual void scheduleWriteOperands(Wavefront *w,
  56                                        GPUDynInstPtr ii) override;
  57     virtual void scheduleWriteOperandsFromLoad(Wavefront *w,
  58                                                GPUDynInstPtr ii) override;
  59     virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii) override;
  60
  61     void
  62     setParent(ComputeUnit *_computeUnit) override
  63     {
  64         RegisterFile::setParent(_computeUnit);
  65     }
  66
  67     // Read a register that is writeable (e.g., a DST operand)
  68     VecRegContainer&
  69     readWriteable(int regIdx)
  70     {
  71         return regFile[regIdx];
  72     }
  73
  74     // Read a register that is not writeable (e.g., src operand)
  75     const VecRegContainer&
  76     read(int regIdx) const
  77     {
  78         return regFile[regIdx];
  79     }
  80
  81     // Write a register
  82     void
  83     write(int regIdx, const VecRegContainer &value)
  84     {
  85         regFile[regIdx] = value;
  86     }
  87
  88     void
  89     printReg(Wavefront *wf, int regIdx) const
  90     {
  91 #ifndef NDEBUG
  92         const auto &vec_reg_cont = regFile[regIdx];
  93         auto vgpr = vec_reg_cont.as<TheGpuISA::VecElemU32>();
  94
  95         for (int lane = 0; lane < TheGpuISA::NumVecElemPerVecReg; ++lane) {
  96             if (wf->execMask(lane)) {
  97                 DPRINTF(GPUVRF, "WF[%d][%d]: WV[%d] v[%d][%d] = %#x\n",
  98                     wf->simdId, wf->wfSlotId, wf->wfDynId, regIdx, lane,
  99                     vgpr[lane]);
 100             }
 101         }
 102 #endif
 103     }
 104
 105   private:
 106     std::vector<VecRegContainer> regFile;
 107 };
 108
 109 #endif // __VECTOR_REGISTER_FILE_HH__