2 * Copyright (c) 2015 Advanced Micro Devices, Inc.
5 * For use for simulation and test purposes only
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8 * modification, are permitted provided that the following conditions are met:
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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33 * Author: John Kalamatianos
36 #ifndef __VECTOR_REGISTER_STATE_HH__
37 #define __VECTOR_REGISTER_STATE_HH__
44 #include "gpu-compute/misc.hh"
48 // Vector Register State per SIMD unit (contents of the vector
49 // registers in the VRF of the SIMD)
50 class VecRegisterState
54 void init(uint32_t _size, uint32_t wf_size);
56 const std::string& name() const { return _name; }
57 void setParent(ComputeUnit *_computeUnit);
63 read(int regIdx, int threadId=0) {
65 assert(sizeof(T) == 4 || sizeof(T) == 8);
67 p0 = (T*)(&s_reg[regIdx][threadId]);
69 p0 = (T*)(&d_reg[regIdx][threadId]);
77 write(unsigned int regIdx, T value, int threadId=0) {
79 assert(sizeof(T) == 4 || sizeof(T) == 8);
81 p0 = (T*)(&s_reg[regIdx][threadId]);
83 p0 = (T*)(&d_reg[regIdx][threadId]);
89 // (Single Precision) Vector Register File size.
90 int regSize() { return s_reg.size(); }
93 ComputeUnit *computeUnit;
95 // 32-bit Single Precision Vector Register State
96 std::vector<std::vector<uint32_t>> s_reg;
97 // 64-bit Double Precision Vector Register State
98 std::vector<std::vector<uint64_t>> d_reg;
101 #endif // __VECTOR_REGISTER_STATE_HH__