1 """IEEE Floating Point Adder Pipeline
3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=75
7 * scnorm - FPMulSpecialCasesDeNorm
8 * addalign - FPAddAlignSingleAdd
9 * normpack - FPNormToPack
11 scnorm - FPDIVSpecialCasesDeNorm ispec FPBaseData
14 StageChain: FPMULSpecialCasesMod,
18 addalign - FPAddAlignSingleAdd ispec FPSCData
19 -------- ospec FPPostCalcData
21 StageChain: FPAddAlignSingleMod
25 normpack - FPNormToPack ispec FPPostCalcData
26 -------- ospec FPPackData
28 StageChain: Norm1ModSingle,
33 This pipeline has a 3 clock latency, and, with the separation into
34 separate "modules", it is quite clear how to create longer-latency
35 pipelines (if needed) - just create a new, longer top-level (FPADDBasePipe
36 alternative) and construct shorter pipe stages using the building blocks,
37 RoundMod, FPAddStage0Mod etc.
41 from nmutil
.singlepipe
import ControlBase
42 from nmutil
.concurrentunit
import ReservationStations
, num_bits
44 from ieee754
.fpcommon
.normtopack
import FPNormToPack
45 from ieee754
.fpadd
.specialcases
import FPAddSpecialCasesDeNorm
46 from ieee754
.fpadd
.addstages
import FPAddAlignSingleAdd
47 from ieee754
.pipeline
import PipelineSpec
50 class FPADDBasePipe(ControlBase
):
51 def __init__(self
, pspec
):
52 ControlBase
.__init
__(self
)
53 self
.pipe1
= FPAddSpecialCasesDeNorm(pspec
)
54 self
.pipe2
= FPAddAlignSingleAdd(pspec
)
55 self
.pipe3
= FPNormToPack(pspec
)
57 self
._eqs
= self
.connect([self
.pipe1
, self
.pipe2
, self
.pipe3
])
59 def elaborate(self
, platform
):
60 m
= ControlBase
.elaborate(self
, platform
)
61 m
.submodules
.scnorm
= self
.pipe1
62 m
.submodules
.addalign
= self
.pipe2
63 m
.submodules
.normpack
= self
.pipe3
68 class FPADDMuxInOut(ReservationStations
):
69 """ Reservation-Station version of FPADD pipeline.
71 * fan-in on inputs (an array of FPBaseData: a,b,mid)
72 * 3-stage adder pipeline
73 * fan-out on outputs (an array of FPPackData: z,mid)
75 Fan-in and Fan-out are combinatorial.
78 def __init__(self
, width
, num_rows
, op_wid
=None):
79 self
.id_wid
= num_bits(num_rows
)
81 self
.pspec
= PipelineSpec(width
, self
.id_wid
, op_wid
)
82 self
.alu
= FPADDBasePipe(self
.pspec
)
83 ReservationStations
.__init
__(self
, num_rows
)