1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Elaboratable
6 from nmigen
.cli
import main
, verilog
8 from ieee754
.fpcommon
.fpbase
import MultiShiftRMerge
11 class FPEXPHigh(Elaboratable
):
13 def __init__(self
, m_width
, e_width
):
14 self
.m_width
= m_width
15 self
.e_width
= e_width
16 self
.ediff
= Signal((e_width
, True), reset_less
=True)
18 self
.m_in
= Signal(m_width
, reset_less
=True)
19 self
.e_in
= Signal((e_width
, True), reset_less
=True)
20 self
.m_out
= Signal(m_width
, reset_less
=True)
21 self
.e_out
= Signal((e_width
, True), reset_less
=True)
23 def elaborate(self
, platform
):
26 espec
= (self
.e_width
, True)
29 msr
= MultiShiftRMerge(mwid
, espec
)
30 m
.submodules
.multishift_r
= msr
33 # connect multi-shifter to inp/out mantissa (and ediff)
34 msr
.inp
.eq(self
.m_in
),
35 msr
.diff
.eq(self
.ediff
),
37 self
.e_out
.eq(self
.e_in
+ self
.ediff
),