1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Mux
, Array
, Const
, Elaboratable
6 from nmigen
.lib
.coding
import PriorityEncoder
7 from nmigen
.cli
import main
, verilog
10 from fpbase
import FPNumIn
, FPNumOut
, FPOpIn
, Overflow
, FPBase
, FPNumBase
11 from fpbase
import MultiShiftRMerge
, Trigger
12 from nmutil
.singlepipe
import (ControlBase
, StageChain
, SimpleHandshake
,
13 PassThroughStage
, PrevControl
)
14 from nmutil
.multipipe
import CombMuxOutPipe
15 from nmutil
.multipipe
import PriorityCombMuxInPipe
17 from fpbase
import FPState
18 from nmutil
import nmoperator
21 class FPGetOpMod(Elaboratable
):
22 def __init__(self
, width
):
23 self
.in_op
= FPOpIn(width
)
24 self
.in_op
.data_i
= Signal(width
)
25 self
.out_op
= Signal(width
)
26 self
.out_decode
= Signal(reset_less
=True)
28 def elaborate(self
, platform
):
30 m
.d
.comb
+= self
.out_decode
.eq((self
.in_op
.ready_o
) & \
31 (self
.in_op
.valid_i_test
))
32 m
.submodules
.get_op_in
= self
.in_op
33 #m.submodules.get_op_out = self.out_op
34 with m
.If(self
.out_decode
):
36 self
.out_op
.eq(self
.in_op
.v
),
41 class FPGetOp(FPState
):
45 def __init__(self
, in_state
, out_state
, in_op
, width
):
46 FPState
.__init
__(self
, in_state
)
47 self
.out_state
= out_state
48 self
.mod
= FPGetOpMod(width
)
50 self
.out_op
= Signal(width
)
51 self
.out_decode
= Signal(reset_less
=True)
53 def setup(self
, m
, in_op
):
54 """ links module to inputs and outputs
56 setattr(m
.submodules
, self
.state_from
, self
.mod
)
57 m
.d
.comb
+= nmoperator
.eq(self
.mod
.in_op
, in_op
)
58 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.out_decode
)
61 with m
.If(self
.out_decode
):
62 m
.next
= self
.out_state
64 self
.in_op
.ready_o
.eq(0),
65 self
.out_op
.eq(self
.mod
.out_op
)
68 m
.d
.sync
+= self
.in_op
.ready_o
.eq(1)
73 def __init__(self
, width
, id_wid
, m_extra
=True):
74 self
.a
= FPNumBase(width
, m_extra
)
75 self
.b
= FPNumBase(width
, m_extra
)
76 self
.mid
= Signal(id_wid
, reset_less
=True)
79 return [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
), self
.mid
.eq(i
.mid
)]
82 return [self
.a
, self
.b
, self
.mid
]
87 def __init__(self
, width
, id_wid
):
90 self
.a
= Signal(width
)
91 self
.b
= Signal(width
)
92 self
.mid
= Signal(id_wid
, reset_less
=True)
95 return [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
), self
.mid
.eq(i
.mid
)]
98 return [self
.a
, self
.b
, self
.mid
]
101 class FPGet2OpMod(PrevControl
):
102 def __init__(self
, width
, id_wid
):
103 PrevControl
.__init
__(self
)
106 self
.data_i
= self
.ispec()
108 self
.o
= self
.ospec()
111 return FPADDBaseData(self
.width
, self
.id_wid
)
114 return FPADDBaseData(self
.width
, self
.id_wid
)
116 def process(self
, i
):
119 def elaborate(self
, platform
):
120 m
= PrevControl
.elaborate(self
, platform
)
121 with m
.If(self
.trigger
):
123 self
.o
.eq(self
.data_i
),
128 class FPGet2Op(FPState
):
132 def __init__(self
, in_state
, out_state
, width
, id_wid
):
133 FPState
.__init
__(self
, in_state
)
134 self
.out_state
= out_state
135 self
.mod
= FPGet2OpMod(width
, id_wid
)
136 self
.o
= self
.ospec()
137 self
.in_stb
= Signal(reset_less
=True)
138 self
.out_ack
= Signal(reset_less
=True)
139 self
.out_decode
= Signal(reset_less
=True)
142 return self
.mod
.ispec()
145 return self
.mod
.ospec()
147 def trigger_setup(self
, m
, in_stb
, in_ack
):
150 m
.d
.comb
+= self
.mod
.valid_i
.eq(in_stb
)
151 m
.d
.comb
+= in_ack
.eq(self
.mod
.ready_o
)
153 def setup(self
, m
, i
):
154 """ links module to inputs and outputs
156 m
.submodules
.get_ops
= self
.mod
157 m
.d
.comb
+= self
.mod
.i
.eq(i
)
158 m
.d
.comb
+= self
.out_ack
.eq(self
.mod
.ready_o
)
159 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.trigger
)
161 def process(self
, i
):
165 with m
.If(self
.out_decode
):
166 m
.next
= self
.out_state
168 self
.mod
.ready_o
.eq(0),
169 self
.o
.eq(self
.mod
.o
),
172 m
.d
.sync
+= self
.mod
.ready_o
.eq(1)