1 """ key strategic example showing how to do multi-input fan-in into a
2 multi-stage pipeline, then multi-output fanout.
4 the multiplex ID from the fan-in is passed in to the pipeline, preserved,
5 and used as a routing ID on the fanout.
8 from random
import randint
9 from nmigen
.compat
.sim
import run_simulation
10 from nmigen
.cli
import verilog
, rtlil
14 def __init__(self
, dut
, width
, fpkls
, fpop
, vals
, single_op
, opcode
):
18 self
.single_op
= single_op
22 self
.tlen
= len(vals
) // dut
.num_rows
24 for muxid
in range(dut
.num_rows
):
27 for i
in range(self
.tlen
):
31 if isinstance(op1
, tuple):
34 res
= self
.fpop(self
.fpkls(op1
))
35 self
.di
[muxid
][i
] = (op1
, )
37 (op1
, op2
, ) = vals
.pop(0)
38 #print ("test", hex(op1), hex(op2))
39 res
= self
.fpop(self
.fpkls(op1
), self
.fpkls(op2
))
40 self
.di
[muxid
][i
] = (op1
, op2
)
41 self
.do
[muxid
].append(res
.bits
)
43 def send(self
, muxid
):
44 for i
in range(self
.tlen
):
46 op1
, = self
.di
[muxid
][i
]
48 op1
, op2
= self
.di
[muxid
][i
]
49 rs
= self
.dut
.p
[muxid
]
50 yield rs
.valid_i
.eq(1)
51 yield rs
.data_i
.a
.eq(op1
)
52 if self
.opcode
is not None:
53 yield rs
.data_i
.ctx
.op
.eq(self
.opcode
)
54 if not self
.single_op
:
55 yield rs
.data_i
.b
.eq(op2
)
56 yield rs
.data_i
.muxid
.eq(muxid
)
58 o_p_ready
= yield rs
.ready_o
61 o_p_ready
= yield rs
.ready_o
64 fop1
= self
.fpkls(op1
)
66 print ("send", muxid
, i
, hex(op1
), hex(res
.bits
),
69 fop1
= self
.fpkls(op1
)
70 fop2
= self
.fpkls(op2
)
71 res
= self
.fpop(fop1
, fop2
)
72 print ("send", muxid
, i
, hex(op1
), hex(op2
), hex(res
.bits
),
75 yield rs
.valid_i
.eq(0)
76 # wait random period of time before queueing another value
77 for i
in range(randint(0, 3)):
80 yield rs
.valid_i
.eq(0)
83 print ("send ended", muxid
)
85 ## wait random period of time before queueing another value
86 #for i in range(randint(0, 3)):
89 #send_range = randint(0, 3)
93 # send = randint(0, send_range) != 0
97 #stall_range = randint(0, 3)
98 #for j in range(randint(1,10)):
99 # stall = randint(0, stall_range) != 0
100 # yield self.dut.n[0].ready_i.eq(stall)
102 n
= self
.dut
.n
[muxid
]
103 yield n
.ready_i
.eq(1)
105 o_n_valid
= yield n
.valid_o
106 i_n_ready
= yield n
.ready_i
107 if not o_n_valid
or not i_n_ready
:
110 out_muxid
= yield n
.data_o
.muxid
111 out_z
= yield n
.data_o
.z
115 print ("recv", out_muxid
, hex(out_z
), "expected",
116 hex(self
.do
[muxid
][out_i
] ))
118 # see if this output has occurred already, delete it if it has
119 assert muxid
== out_muxid
, "out_muxid %d not correct %d" % \
121 assert self
.do
[muxid
][out_i
] == out_z
122 del self
.do
[muxid
][out_i
]
124 # check if there's any more outputs
125 if len(self
.do
[muxid
]) == 0:
127 print ("recv ended", muxid
)
130 def create_random(num_rows
, width
, single_op
=False, n_vals
=10):
132 for muxid
in range(num_rows
):
133 for i
in range(n_vals
):
135 op1
= randint(0, (1<<width
)-1)
151 #op1 = 0x9885020648d8c0e8
168 op1
= randint(0, (1<<width
)-1)
169 op2
= randint(0, (1<<width
)-1)
174 vals
.append((op1
, op2
,))
178 def repeat(num_rows
, vals
):
179 """ bit of a hack: repeats the last value to create a list
180 that will be accepted by the muxer, all mux lists to be
184 n_to_repeat
= len(vals
) % num_rows
185 #print ("repeat", vals)
186 return vals
+ [vals
[-1]] * n_to_repeat
189 def pipe_cornercases_repeat(dut
, name
, mod
, fmod
, width
, fn
, cc
, fpfn
, count
,
191 for i
, fixed_num
in enumerate(cc(mod
)):
192 vals
= fn(mod
, fixed_num
, count
, width
, single_op
)
193 vals
= repeat(dut
.num_rows
, vals
)
194 #print ("repeat", i, fn, single_op, list(vals))
195 fmt
= "test_pipe_fp%d_%s_cornercases_%d"
196 runfp(dut
, width
, fmt
% (width
, name
, i
),
197 fmod
, fpfn
, vals
=vals
, single_op
=single_op
)
200 def runfp(dut
, width
, name
, fpkls
, fpop
, single_op
=False, n_vals
=10,
201 vals
=None, opcode
=None):
202 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
203 with
open("%s.il" % name
, "w") as f
:
207 vals
= create_random(dut
.num_rows
, width
, single_op
, n_vals
)
209 test
= MuxInOut(dut
, width
, fpkls
, fpop
, vals
, single_op
, opcode
=opcode
)
211 for i
in range(dut
.num_rows
):
212 fns
.append(test
.rcv(i
))
213 fns
.append(test
.send(i
))
214 run_simulation(dut
, fns
, vcd_name
="%s.vcd" % name
)