167edde662eda12b7b774474ba09359b039c5ec3
1 """IEEE754 Floating Point Divider
3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
6 from nmigen
import Module
, Signal
, Cat
, Elaboratable
7 from nmigen
.cli
import main
, verilog
9 from ieee754
.fpcommon
.fpbase
import (FPNumBaseRecord
, Overflow
)
10 from ieee754
.fpcommon
.fpbase
import FPState
11 from ieee754
.fpcommon
.denorm
import FPSCData
14 class FPDivStage0Data
:
16 def __init__(self
, width
, id_wid
):
17 self
.z
= FPNumBaseRecord(width
, False)
18 self
.out_do_z
= Signal(reset_less
=True)
19 self
.oz
= Signal(width
, reset_less
=True)
22 # TODO: here is where Q and R would be put, and passed
23 # down to Stage1 processing.
25 mw
= (self
.z
.m_width
)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
26 self
.product
= Signal(mw
, reset_less
=True)
28 self
.mid
= Signal(id_wid
, reset_less
=True)
31 return [self
.z
.eq(i
.z
), self
.out_do_z
.eq(i
.out_do_z
), self
.oz
.eq(i
.oz
),
33 self
.product
.eq(i
.product
), self
.mid
.eq(i
.mid
)]
36 class FPDivStage0Mod(Elaboratable
):
38 def __init__(self
, width
, id_wid
):
45 return FPSCData(self
.width
, self
.id_wid
, False)
48 return FPDivStage0Data(self
.width
, self
.id_wid
)
53 def setup(self
, m
, i
):
54 """ links module to inputs and outputs
56 m
.submodules
.div0
= self
57 m
.d
.comb
+= self
.i
.eq(i
)
59 def elaborate(self
, platform
):
62 # XXX TODO, actual DIV code here. this class would be
63 # "step one" which takes the pre-normalised data (see ispec) and
64 # *begins* the processing phase (enters the massive DIV
65 # pipeline chain) - see ospec.
67 # store intermediate tests (and zero-extended mantissas)
68 am0
= Signal(len(self
.i
.a
.m
)+1, reset_less
=True)
69 bm0
= Signal(len(self
.i
.b
.m
)+1, reset_less
=True)
71 am0
.eq(Cat(self
.i
.a
.m
, 0)),
72 bm0
.eq(Cat(self
.i
.b
.m
, 0))
74 # same-sign (both negative or both positive) div mantissas
75 with m
.If(~self
.i
.out_do_z
):
76 m
.d
.comb
+= [self
.o
.z
.e
.eq(self
.i
.a
.e
+ self
.i
.b
.e
+ 1),
77 # TODO: no, not product, first stage Q and R etc. etc.
79 self
.o
.product
.eq(am0
* bm0
* 4),
80 self
.o
.z
.s
.eq(self
.i
.a
.s ^ self
.i
.b
.s
)
83 m
.d
.comb
+= self
.o
.oz
.eq(self
.i
.oz
)
84 m
.d
.comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
85 m
.d
.comb
+= self
.o
.mid
.eq(self
.i
.mid
)
89 class FPDivStage0(FPState
):
90 """ First stage of div.
93 def __init__(self
, width
, id_wid
):
94 FPState
.__init
__(self
, "divider_0")
95 self
.mod
= FPDivStage0Mod(width
)
96 self
.o
= self
.mod
.ospec()
98 def setup(self
, m
, i
):
99 """ links module to inputs and outputs
103 # NOTE: these could be done as combinatorial (merge div0+div1)
104 m
.d
.sync
+= self
.o
.eq(self
.mod
.o
)