src/ieee754/fpdiv/div1.py

   1 """IEEE754 Floating Point Divider
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4 """
   5
   6 from nmigen import Module, Signal, Cat, Elaboratable
   7 from nmigen.cli import main, verilog
   8
   9 from ieee754.fpcommon.fpbase import FPNumBaseRecord
  10 from ieee754.fpcommon.fpbase import FPState
  11 from ieee754.fpcommon.denorm import FPSCData
  12 from .div0 import FPDivStage0Data # TODO: replace with DivPipeCoreInterstageData
  13
  14
  15 class FPDivStage1Mod(Elaboratable):
  16
  17     def __init__(self, width, pspec):
  18         self.width = width
  19         self.pspec = pspec
  20         self.i = self.ispec()
  21         self.o = self.ospec()
  22
  23     def ispec(self):
  24         # TODO: DivPipeCoreInterstageData, here
  25         return FPDivStage0Data(self.width, self.pspec) # Q/Rem (etc) in...
  26
  27     def ospec(self):
  28         # TODO: DivPipeCoreInterstageData, here
  29         return FPDivStage0Data(self.width, self.pspec) # ... Q/Rem (etc) out
  30
  31     def process(self, i):
  32         return self.o
  33
  34     def setup(self, m, i):
  35         """ links module to inputs and outputs
  36         """
  37         m.submodules.div0 = self
  38         m.d.comb += self.i.eq(i)
  39
  40     def elaborate(self, platform):
  41         m = Module()
  42
  43         # XXX TODO, actual DIV code here.  this class would be
  44         # here is where Q and R are used, TODO: Q/REM (etc) need to be in
  45         # FPDivStage0Data.
  46
  47         # NOTE: this does ONE step of Q/REM processing.  it does NOT do
  48         # MULTIPLE stages of Q/REM processing.  it *MUST* be PURE
  49         # combinatorial and one step ONLY.
  50
  51         # store intermediate tests (and zero-extended mantissas)
  52         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  53         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  54         m.d.comb += [
  55                      am0.eq(Cat(self.i.a.m, 0)),
  56                      bm0.eq(Cat(self.i.b.m, 0))
  57                     ]
  58         # same-sign (both negative or both positive) div mantissas
  59         with m.If(~self.i.out_do_z):
  60             m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
  61                          # TODO: no, not product, first stage Q and R etc. etc.
  62                          # go here.
  63                          self.o.product.eq(am0 * bm0 * 4),
  64                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
  65                 ]
  66
  67         m.d.comb += self.o.oz.eq(self.i.oz)
  68         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  69         m.d.comb += self.o.ctx.eq(self.i.ctx)
  70         return m
  71