1 """IEEE754 Floating Point Multiplier Pipeline
3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
7 from nmigen
import Module
, Signal
, Mux
8 from nmigen
.cli
import main
, verilog
10 from nmutil
.pipemodbase
import PipeModBase
11 from ieee754
.fpcommon
.postcalc
import FPPostCalcData
12 from ieee754
.fpmul
.mul0
import FPMulStage0Data
15 class FPMulStage1Mod(PipeModBase
):
16 """ Second stage of mul: preparation for normalisation.
19 def __init__(self
, pspec
):
20 super().__init
__(pspec
, "mul1")
23 return FPMulStage0Data(self
.pspec
)
26 return FPPostCalcData(self
.pspec
)
28 def elaborate(self
, platform
):
33 comb
+= self
.o
.z
.s
.eq(self
.i
.z
.s
)
35 # results are in the range 0.25 to 0.999999999999
36 # sometimes the MSB will be zero, (0.5 * 0.5 = 0.25 which
37 # in binary is 0b010000) so to compensate for that we have
38 # to shift the mantissa up (and reduce the exponent by 1)
39 p
= Signal(len(self
.i
.product
), reset_less
=True)
40 msb
= Signal(reset_less
=True)
42 comb
+= msb
.eq(self
.i
.product
[-1])
43 comb
+= p
.eq(Mux(msb
, self
.i
.product
, self
.i
.product
<<1))
44 comb
+= e
.eq(Mux(msb
, self
.i
.z
.e
, self
.i
.z
.e
-1))
46 # top bits are mantissa, then guard and round, and the rest of
47 # the product is sticky
50 self
.o
.z
.m
.eq(p
[mw
+2:]), # mantissa
51 self
.o
.of
.m0
.eq(p
[mw
+2]), # copy of LSB
52 self
.o
.of
.guard
.eq(p
[mw
+1]), # guard
53 self
.o
.of
.round_bit
.eq(p
[mw
]), # round
54 self
.o
.of
.sticky
.eq(p
[0:mw
].bool()) # sticky
57 # pass through context
58 comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
59 comb
+= self
.o
.oz
.eq(self
.i
.oz
)
60 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)