dab89b27a6bf53759e3715a2c5a066987f8d21c9
1 # IEEE Floating Point Multiplier
3 from nmigen
import Module
, Signal
, Cat
, Const
, Elaboratable
4 from nmigen
.cli
import main
, verilog
7 from ieee754
.fpcommon
.fpbase
import FPNumDecode
, FPNumBaseRecord
8 from nmutil
.singlepipe
import SimpleHandshake
, StageChain
10 from ieee754
.fpcommon
.fpbase
import FPState
, FPID
11 from ieee754
.fpcommon
.getop
import FPADDBaseData
12 from ieee754
.fpcommon
.denorm
import (FPSCData
, FPAddDeNormMod
)
15 class FPMulSpecialCasesMod(Elaboratable
):
16 """ special cases: NaNs, infs, zeros, denormalised
17 see "Special Operations"
18 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
21 def __init__(self
, width
, pspec
):
28 return FPADDBaseData(self
.width
, self
.pspec
)
31 return FPSCData(self
.width
, self
.pspec
, False)
33 def setup(self
, m
, i
):
34 """ links module to inputs and outputs
36 m
.submodules
.specialcases
= self
37 m
.d
.comb
+= self
.i
.eq(i
)
42 def elaborate(self
, platform
):
45 #m.submodules.sc_out_z = self.o.z
47 # decode: XXX really should move to separate stage
48 a1
= FPNumBaseRecord(self
.width
, False)
49 b1
= FPNumBaseRecord(self
.width
, False)
50 m
.submodules
.sc_decode_a
= a1
= FPNumDecode(None, a1
)
51 m
.submodules
.sc_decode_b
= b1
= FPNumDecode(None, b1
)
52 m
.d
.comb
+= [a1
.v
.eq(self
.i
.a
),
58 obz
= Signal(reset_less
=True)
59 m
.d
.comb
+= obz
.eq(a1
.is_zero | b1
.is_zero
)
61 sabx
= Signal(reset_less
=True) # sign a xor b (sabx, get it?)
62 m
.d
.comb
+= sabx
.eq(a1
.s ^ b1
.s
)
64 abnan
= Signal(reset_less
=True)
65 m
.d
.comb
+= abnan
.eq(a1
.is_nan | b1
.is_nan
)
67 # if a is NaN or b is NaN return NaN
69 m
.d
.comb
+= self
.o
.out_do_z
.eq(1)
70 m
.d
.comb
+= self
.o
.z
.nan(0)
72 # if a is inf return inf (or NaN)
73 with m
.Elif(a1
.is_inf
):
74 m
.d
.comb
+= self
.o
.out_do_z
.eq(1)
75 m
.d
.comb
+= self
.o
.z
.inf(sabx
)
76 # b is zero return NaN
77 with m
.If(b1
.is_zero
):
78 m
.d
.comb
+= self
.o
.z
.nan(1)
80 # if b is inf return inf (or NaN)
81 with m
.Elif(b1
.is_inf
):
82 m
.d
.comb
+= self
.o
.out_do_z
.eq(1)
83 m
.d
.comb
+= self
.o
.z
.inf(sabx
)
84 # a is zero return NaN
85 with m
.If(a1
.is_zero
):
86 m
.d
.comb
+= self
.o
.z
.nan(1)
88 # if a is zero or b zero return signed-a/b
90 m
.d
.comb
+= self
.o
.out_do_z
.eq(1)
91 m
.d
.comb
+= self
.o
.z
.zero(sabx
)
93 # Denormalised Number checks next, so pass a/b data through
95 m
.d
.comb
+= self
.o
.out_do_z
.eq(0)
97 m
.d
.comb
+= self
.o
.oz
.eq(self
.o
.z
.v
)
98 m
.d
.comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)
103 class FPMulSpecialCases(FPState
):
104 """ special cases: NaNs, infs, zeros, denormalised
105 NOTE: some of these are unique to add. see "Special Operations"
106 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
109 def __init__(self
, width
, id_wid
):
110 FPState
.__init
__(self
, "special_cases")
111 self
.mod
= FPMulSpecialCasesMod(width
)
112 self
.out_z
= self
.mod
.ospec()
113 self
.out_do_z
= Signal(reset_less
=True)
115 def setup(self
, m
, i
):
116 """ links module to inputs and outputs
118 self
.mod
.setup(m
, i
, self
.out_do_z
)
119 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
) # only take the output
120 m
.d
.sync
+= self
.out_z
.ctx
.eq(self
.mod
.o
.ctx
) # (and context)
124 with m
.If(self
.out_do_z
):
127 m
.next
= "denormalise"
130 class FPMulSpecialCasesDeNorm(FPState
, SimpleHandshake
):
131 """ special cases: NaNs, infs, zeros, denormalised
134 def __init__(self
, width
, pspec
):
135 FPState
.__init
__(self
, "special_cases")
138 SimpleHandshake
.__init
__(self
, self
) # pipe is its own stage
139 self
.out
= self
.ospec()
142 return FPADDBaseData(self
.width
, self
.pspec
)
145 return FPSCData(self
.width
, self
.pspec
, False)
147 def setup(self
, m
, i
):
148 """ links module to inputs and outputs
150 smod
= FPMulSpecialCasesMod(self
.width
, self
.pspec
)
151 dmod
= FPAddDeNormMod(self
.width
, self
.pspec
, False)
153 chain
= StageChain([smod
, dmod
])
156 # only needed for break-out (early-out)
157 # self.out_do_z = smod.o.out_do_z
161 def process(self
, i
):
165 # for break-out (early-out)
166 #with m.If(self.out_do_z):
169 m
.d
.sync
+= self
.out
.eq(self
.process(None))