1 # SPDX-License-Identifier: LGPL-2.1-or-later
2 # See Notices.txt for copyright information
3 """Integer Multiplication."""
5 from nmigen
import Signal
, Module
, Value
, Elaboratable
, Cat
, C
, Mux
, Repl
6 from nmigen
.hdl
.ast
import Assign
7 from abc
import ABCMeta
, abstractmethod
8 from nmigen
.cli
import main
9 from functools
import reduce
10 from operator
import or_
13 class PartitionPoints(dict):
14 """Partition points and corresponding ``Value``s.
16 The points at where an ALU is partitioned along with ``Value``s that
17 specify if the corresponding partition points are enabled.
19 For example: ``{1: True, 5: True, 10: True}`` with
20 ``width == 16`` specifies that the ALU is split into 4 sections:
23 * bits 5 <= ``i`` < 10
24 * bits 10 <= ``i`` < 16
26 If the partition_points were instead ``{1: True, 5: a, 10: True}``
27 where ``a`` is a 1-bit ``Signal``:
28 * If ``a`` is asserted:
31 * bits 5 <= ``i`` < 10
32 * bits 10 <= ``i`` < 16
35 * bits 1 <= ``i`` < 10
36 * bits 10 <= ``i`` < 16
39 def __init__(self
, partition_points
=None):
40 """Create a new ``PartitionPoints``.
42 :param partition_points: the input partition points to values mapping.
45 if partition_points
is not None:
46 for point
, enabled
in partition_points
.items():
47 if not isinstance(point
, int):
48 raise TypeError("point must be a non-negative integer")
50 raise ValueError("point must be a non-negative integer")
51 self
[point
] = Value
.wrap(enabled
)
53 def like(self
, name
=None, src_loc_at
=0, mul
=1):
54 """Create a new ``PartitionPoints`` with ``Signal``s for all values.
56 :param name: the base name for the new ``Signal``s.
57 :param mul: a multiplication factor on the indices
60 name
= Signal(src_loc_at
=1+src_loc_at
).name
# get variable name
61 retval
= PartitionPoints()
62 for point
, enabled
in self
.items():
64 retval
[point
] = Signal(enabled
.shape(), name
=f
"{name}_{point}")
68 """Assign ``PartitionPoints`` using ``Signal.eq``."""
69 if set(self
.keys()) != set(rhs
.keys()):
70 raise ValueError("incompatible point set")
71 for point
, enabled
in self
.items():
72 yield enabled
.eq(rhs
[point
])
74 def as_mask(self
, width
, mul
=1):
75 """Create a bit-mask from `self`.
77 Each bit in the returned mask is clear only if the partition point at
78 the same bit-index is enabled.
80 :param width: the bit width of the resulting mask
81 :param mul: a "multiplier" which in-place expands the partition points
82 typically set to "2" when used for multipliers
85 for i
in range(width
):
87 if i
.is_integer() and int(i
) in self
:
93 def get_max_partition_count(self
, width
):
94 """Get the maximum number of partitions.
96 Gets the number of partitions when all partition points are enabled.
99 for point
in self
.keys():
104 def fits_in_width(self
, width
):
105 """Check if all partition points are smaller than `width`."""
106 for point
in self
.keys():
111 def part_byte(self
, index
, mfactor
=1): # mfactor used for "expanding"
112 if index
== -1 or index
== 7:
114 assert index
>= 0 and index
< 8
115 return self
[(index
* 8 + 8)*mfactor
]
118 class FullAdder(Elaboratable
):
121 :attribute in0: the first input
122 :attribute in1: the second input
123 :attribute in2: the third input
124 :attribute sum: the sum output
125 :attribute carry: the carry output
127 Rather than do individual full adders (and have an array of them,
128 which would be very slow to simulate), this module can specify the
129 bit width of the inputs and outputs: in effect it performs multiple
130 Full 3-2 Add operations "in parallel".
133 def __init__(self
, width
):
134 """Create a ``FullAdder``.
136 :param width: the bit width of the input and output
138 self
.in0
= Signal(width
, reset_less
=True)
139 self
.in1
= Signal(width
, reset_less
=True)
140 self
.in2
= Signal(width
, reset_less
=True)
141 self
.sum = Signal(width
, reset_less
=True)
142 self
.carry
= Signal(width
, reset_less
=True)
144 def elaborate(self
, platform
):
145 """Elaborate this module."""
147 m
.d
.comb
+= self
.sum.eq(self
.in0 ^ self
.in1 ^ self
.in2
)
148 m
.d
.comb
+= self
.carry
.eq((self
.in0
& self
.in1
)
149 |
(self
.in1
& self
.in2
)
150 |
(self
.in2
& self
.in0
))
154 class MaskedFullAdder(Elaboratable
):
155 """Masked Full Adder.
157 :attribute mask: the carry partition mask
158 :attribute in0: the first input
159 :attribute in1: the second input
160 :attribute in2: the third input
161 :attribute sum: the sum output
162 :attribute mcarry: the masked carry output
164 FullAdders are always used with a "mask" on the output. To keep
165 the graphviz "clean", this class performs the masking here rather
166 than inside a large for-loop.
168 See the following discussion as to why this is no longer derived
169 from FullAdder. Each carry is shifted here *before* being ANDed
170 with the mask, so that an AOI cell may be used (which is more
172 https://en.wikipedia.org/wiki/AND-OR-Invert
173 https://groups.google.com/d/msg/comp.arch/fcq-GLQqvas/vTxmcA0QAgAJ
176 def __init__(self
, width
):
177 """Create a ``MaskedFullAdder``.
179 :param width: the bit width of the input and output
182 self
.mask
= Signal(width
, reset_less
=True)
183 self
.mcarry
= Signal(width
, reset_less
=True)
184 self
.in0
= Signal(width
, reset_less
=True)
185 self
.in1
= Signal(width
, reset_less
=True)
186 self
.in2
= Signal(width
, reset_less
=True)
187 self
.sum = Signal(width
, reset_less
=True)
189 def elaborate(self
, platform
):
190 """Elaborate this module."""
192 s1
= Signal(self
.width
, reset_less
=True)
193 s2
= Signal(self
.width
, reset_less
=True)
194 s3
= Signal(self
.width
, reset_less
=True)
195 c1
= Signal(self
.width
, reset_less
=True)
196 c2
= Signal(self
.width
, reset_less
=True)
197 c3
= Signal(self
.width
, reset_less
=True)
198 m
.d
.comb
+= self
.sum.eq(self
.in0 ^ self
.in1 ^ self
.in2
)
199 m
.d
.comb
+= s1
.eq(Cat(0, self
.in0
))
200 m
.d
.comb
+= s2
.eq(Cat(0, self
.in1
))
201 m
.d
.comb
+= s3
.eq(Cat(0, self
.in2
))
202 m
.d
.comb
+= c1
.eq(s1
& s2
& self
.mask
)
203 m
.d
.comb
+= c2
.eq(s2
& s3
& self
.mask
)
204 m
.d
.comb
+= c3
.eq(s3
& s1
& self
.mask
)
205 m
.d
.comb
+= self
.mcarry
.eq(c1 | c2 | c3
)
209 class PartitionedAdder(Elaboratable
):
210 """Partitioned Adder.
212 Performs the final add. The partition points are included in the
213 actual add (in one of the operands only), which causes a carry over
214 to the next bit. Then the final output *removes* the extra bits from
217 partition: .... P... P... P... P... (32 bits)
218 a : .... .... .... .... .... (32 bits)
219 b : .... .... .... .... .... (32 bits)
220 exp-a : ....P....P....P....P.... (32+4 bits, P=1 if no partition)
221 exp-b : ....0....0....0....0.... (32 bits plus 4 zeros)
222 exp-o : ....xN...xN...xN...xN... (32+4 bits - x to be discarded)
223 o : .... N... N... N... N... (32 bits - x ignored, N is carry-over)
225 :attribute width: the bit width of the input and output. Read-only.
226 :attribute a: the first input to the adder
227 :attribute b: the second input to the adder
228 :attribute output: the sum output
229 :attribute partition_points: the input partition points. Modification not
230 supported, except for by ``Signal.eq``.
233 def __init__(self
, width
, partition_points
, partition_step
=1):
234 """Create a ``PartitionedAdder``.
236 :param width: the bit width of the input and output
237 :param partition_points: the input partition points
238 :param partition_step: a multiplier (typically double) step
239 which in-place "expands" the partition points
242 self
.pmul
= partition_step
243 self
.a
= Signal(width
, reset_less
=True)
244 self
.b
= Signal(width
, reset_less
=True)
245 self
.output
= Signal(width
, reset_less
=True)
246 self
.partition_points
= PartitionPoints(partition_points
)
247 if not self
.partition_points
.fits_in_width(width
):
248 raise ValueError("partition_points doesn't fit in width")
250 for i
in range(self
.width
):
251 if i
in self
.partition_points
:
254 self
._expanded
_width
= expanded_width
256 def elaborate(self
, platform
):
257 """Elaborate this module."""
259 expanded_a
= Signal(self
._expanded
_width
, reset_less
=True)
260 expanded_b
= Signal(self
._expanded
_width
, reset_less
=True)
261 expanded_o
= Signal(self
._expanded
_width
, reset_less
=True)
264 # store bits in a list, use Cat later. graphviz is much cleaner
265 al
, bl
, ol
, ea
, eb
, eo
= [],[],[],[],[],[]
267 # partition points are "breaks" (extra zeros or 1s) in what would
268 # otherwise be a massive long add. when the "break" points are 0,
269 # whatever is in it (in the output) is discarded. however when
270 # there is a "1", it causes a roll-over carry to the *next* bit.
271 # we still ignore the "break" bit in the [intermediate] output,
272 # however by that time we've got the effect that we wanted: the
273 # carry has been carried *over* the break point.
275 for i
in range(self
.width
):
276 pi
= i
/self
.pmul
# double the range of the partition point test
277 if pi
.is_integer() and pi
in self
.partition_points
:
278 # add extra bit set to 0 + 0 for enabled partition points
279 # and 1 + 0 for disabled partition points
280 ea
.append(expanded_a
[expanded_index
])
281 al
.append(~self
.partition_points
[pi
]) # add extra bit in a
282 eb
.append(expanded_b
[expanded_index
])
283 bl
.append(C(0)) # yes, add a zero
284 expanded_index
+= 1 # skip the extra point. NOT in the output
285 ea
.append(expanded_a
[expanded_index
])
286 eb
.append(expanded_b
[expanded_index
])
287 eo
.append(expanded_o
[expanded_index
])
290 ol
.append(self
.output
[i
])
293 # combine above using Cat
294 m
.d
.comb
+= Cat(*ea
).eq(Cat(*al
))
295 m
.d
.comb
+= Cat(*eb
).eq(Cat(*bl
))
296 m
.d
.comb
+= Cat(*ol
).eq(Cat(*eo
))
298 # use only one addition to take advantage of look-ahead carry and
299 # special hardware on FPGAs
300 m
.d
.comb
+= expanded_o
.eq(expanded_a
+ expanded_b
)
304 FULL_ADDER_INPUT_COUNT
= 3
308 def __init__(self
, part_pts
, n_inputs
, output_width
, n_parts
):
309 self
.part_ops
= [Signal(2, name
=f
"part_ops_{i}", reset_less
=True)
310 for i
in range(n_parts
)]
311 self
.terms
= [Signal(output_width
, name
=f
"inputs_{i}",
313 for i
in range(n_inputs
)]
314 self
.part_pts
= part_pts
.like()
316 def eq_from(self
, part_pts
, inputs
, part_ops
):
317 return [self
.part_pts
.eq(part_pts
)] + \
318 [self
.terms
[i
].eq(inputs
[i
])
319 for i
in range(len(self
.terms
))] + \
320 [self
.part_ops
[i
].eq(part_ops
[i
])
321 for i
in range(len(self
.part_ops
))]
324 return self
.eq_from(rhs
.part_pts
, rhs
.terms
, rhs
.part_ops
)
327 class FinalReduceData
:
329 def __init__(self
, part_pts
, output_width
, n_parts
):
330 self
.part_ops
= [Signal(2, name
=f
"part_ops_{i}", reset_less
=True)
331 for i
in range(n_parts
)]
332 self
.output
= Signal(output_width
, reset_less
=True)
333 self
.part_pts
= part_pts
.like()
335 def eq_from(self
, part_pts
, output
, part_ops
):
336 return [self
.part_pts
.eq(part_pts
)] + \
337 [self
.output
.eq(output
)] + \
338 [self
.part_ops
[i
].eq(part_ops
[i
])
339 for i
in range(len(self
.part_ops
))]
342 return self
.eq_from(rhs
.part_pts
, rhs
.output
, rhs
.part_ops
)
345 class FinalAdd(Elaboratable
):
346 """ Final stage of add reduce
349 def __init__(self
, n_inputs
, output_width
, n_parts
, partition_points
):
350 self
.i
= AddReduceData(partition_points
, n_inputs
,
351 output_width
, n_parts
)
352 self
.o
= FinalReduceData(partition_points
, output_width
, n_parts
)
353 self
.output_width
= output_width
354 self
.n_inputs
= n_inputs
355 self
.n_parts
= n_parts
356 self
.partition_points
= PartitionPoints(partition_points
)
357 if not self
.partition_points
.fits_in_width(output_width
):
358 raise ValueError("partition_points doesn't fit in output_width")
360 def elaborate(self
, platform
):
361 """Elaborate this module."""
364 output_width
= self
.output_width
365 output
= Signal(output_width
, reset_less
=True)
366 if self
.n_inputs
== 0:
367 # use 0 as the default output value
368 m
.d
.comb
+= output
.eq(0)
369 elif self
.n_inputs
== 1:
370 # handle single input
371 m
.d
.comb
+= output
.eq(self
.i
.terms
[0])
373 # base case for adding 2 inputs
374 assert self
.n_inputs
== 2
375 adder
= PartitionedAdder(output_width
,
377 m
.submodules
.final_adder
= adder
378 m
.d
.comb
+= adder
.a
.eq(self
.i
.terms
[0])
379 m
.d
.comb
+= adder
.b
.eq(self
.i
.terms
[1])
380 m
.d
.comb
+= output
.eq(adder
.output
)
383 m
.d
.comb
+= self
.o
.eq_from(self
.i
.part_pts
, output
,
389 class AddReduceSingle(Elaboratable
):
390 """Add list of numbers together.
392 :attribute inputs: input ``Signal``s to be summed. Modification not
393 supported, except for by ``Signal.eq``.
394 :attribute register_levels: List of nesting levels that should have
396 :attribute output: output sum.
397 :attribute partition_points: the input partition points. Modification not
398 supported, except for by ``Signal.eq``.
401 def __init__(self
, n_inputs
, output_width
, n_parts
, partition_points
):
402 """Create an ``AddReduce``.
404 :param inputs: input ``Signal``s to be summed.
405 :param output_width: bit-width of ``output``.
406 :param partition_points: the input partition points.
408 self
.n_inputs
= n_inputs
409 self
.n_parts
= n_parts
410 self
.output_width
= output_width
411 self
.i
= AddReduceData(partition_points
, n_inputs
,
412 output_width
, n_parts
)
413 self
.partition_points
= PartitionPoints(partition_points
)
414 if not self
.partition_points
.fits_in_width(output_width
):
415 raise ValueError("partition_points doesn't fit in output_width")
417 self
.groups
= AddReduceSingle
.full_adder_groups(n_inputs
)
418 n_terms
= AddReduceSingle
.calc_n_inputs(n_inputs
, self
.groups
)
419 self
.o
= AddReduceData(partition_points
, n_terms
, output_width
, n_parts
)
422 def calc_n_inputs(n_inputs
, groups
):
423 retval
= len(groups
)*2
424 if n_inputs
% FULL_ADDER_INPUT_COUNT
== 1:
426 elif n_inputs
% FULL_ADDER_INPUT_COUNT
== 2:
429 assert n_inputs
% FULL_ADDER_INPUT_COUNT
== 0
433 def get_max_level(input_count
):
434 """Get the maximum level.
436 All ``register_levels`` must be less than or equal to the maximum
441 groups
= AddReduceSingle
.full_adder_groups(input_count
)
444 input_count
%= FULL_ADDER_INPUT_COUNT
445 input_count
+= 2 * len(groups
)
449 def full_adder_groups(input_count
):
450 """Get ``inputs`` indices for which a full adder should be built."""
452 input_count
- FULL_ADDER_INPUT_COUNT
+ 1,
453 FULL_ADDER_INPUT_COUNT
)
455 def create_next_terms(self
):
456 """ create next intermediate terms, for linking up in elaborate, below
461 # create full adders for this recursive level.
462 # this shrinks N terms to 2 * (N // 3) plus the remainder
463 for i
in self
.groups
:
464 adder_i
= MaskedFullAdder(self
.output_width
)
465 adders
.append((i
, adder_i
))
466 # add both the sum and the masked-carry to the next level.
467 # 3 inputs have now been reduced to 2...
468 terms
.append(adder_i
.sum)
469 terms
.append(adder_i
.mcarry
)
470 # handle the remaining inputs.
471 if self
.n_inputs
% FULL_ADDER_INPUT_COUNT
== 1:
472 terms
.append(self
.i
.terms
[-1])
473 elif self
.n_inputs
% FULL_ADDER_INPUT_COUNT
== 2:
474 # Just pass the terms to the next layer, since we wouldn't gain
475 # anything by using a half adder since there would still be 2 terms
476 # and just passing the terms to the next layer saves gates.
477 terms
.append(self
.i
.terms
[-2])
478 terms
.append(self
.i
.terms
[-1])
480 assert self
.n_inputs
% FULL_ADDER_INPUT_COUNT
== 0
484 def elaborate(self
, platform
):
485 """Elaborate this module."""
488 terms
, adders
= self
.create_next_terms()
490 # copy the intermediate terms to the output
491 for i
, value
in enumerate(terms
):
492 m
.d
.comb
+= self
.o
.terms
[i
].eq(value
)
494 # copy reg part points and part ops to output
495 m
.d
.comb
+= self
.o
.part_pts
.eq(self
.i
.part_pts
)
496 m
.d
.comb
+= [self
.o
.part_ops
[i
].eq(self
.i
.part_ops
[i
])
497 for i
in range(len(self
.i
.part_ops
))]
499 # set up the partition mask (for the adders)
500 part_mask
= Signal(self
.output_width
, reset_less
=True)
502 # get partition points as a mask
503 mask
= self
.i
.part_pts
.as_mask(self
.output_width
, mul
=2)
504 m
.d
.comb
+= part_mask
.eq(mask
)
506 # add and link the intermediate term modules
507 for i
, (iidx
, adder_i
) in enumerate(adders
):
508 setattr(m
.submodules
, f
"adder_{i}", adder_i
)
510 m
.d
.comb
+= adder_i
.in0
.eq(self
.i
.terms
[iidx
])
511 m
.d
.comb
+= adder_i
.in1
.eq(self
.i
.terms
[iidx
+ 1])
512 m
.d
.comb
+= adder_i
.in2
.eq(self
.i
.terms
[iidx
+ 2])
513 m
.d
.comb
+= adder_i
.mask
.eq(part_mask
)
518 class AddReduce(Elaboratable
):
519 """Recursively Add list of numbers together.
521 :attribute inputs: input ``Signal``s to be summed. Modification not
522 supported, except for by ``Signal.eq``.
523 :attribute register_levels: List of nesting levels that should have
525 :attribute output: output sum.
526 :attribute partition_points: the input partition points. Modification not
527 supported, except for by ``Signal.eq``.
530 def __init__(self
, inputs
, output_width
, register_levels
, partition_points
,
532 """Create an ``AddReduce``.
534 :param inputs: input ``Signal``s to be summed.
535 :param output_width: bit-width of ``output``.
536 :param register_levels: List of nesting levels that should have
538 :param partition_points: the input partition points.
541 self
.part_ops
= part_ops
542 n_parts
= len(part_ops
)
543 self
.o
= FinalReduceData(partition_points
, output_width
, n_parts
)
544 self
.output_width
= output_width
545 self
.register_levels
= register_levels
546 self
.partition_points
= partition_points
551 def get_max_level(input_count
):
552 return AddReduceSingle
.get_max_level(input_count
)
555 def next_register_levels(register_levels
):
556 """``Iterable`` of ``register_levels`` for next recursive level."""
557 for level
in register_levels
:
561 def create_levels(self
):
562 """creates reduction levels"""
565 partition_points
= self
.partition_points
566 part_ops
= self
.part_ops
567 n_parts
= len(part_ops
)
571 groups
= AddReduceSingle
.full_adder_groups(len(inputs
))
574 next_level
= AddReduceSingle(ilen
, self
.output_width
, n_parts
,
576 mods
.append(next_level
)
577 partition_points
= next_level
.i
.part_pts
578 inputs
= next_level
.o
.terms
580 part_ops
= next_level
.i
.part_ops
582 next_level
= FinalAdd(ilen
, self
.output_width
, n_parts
,
584 mods
.append(next_level
)
588 def elaborate(self
, platform
):
589 """Elaborate this module."""
592 for i
, next_level
in enumerate(self
.levels
):
593 setattr(m
.submodules
, "next_level%d" % i
, next_level
)
595 partition_points
= self
.partition_points
597 part_ops
= self
.part_ops
598 n_parts
= len(part_ops
)
599 n_inputs
= len(inputs
)
600 output_width
= self
.output_width
601 i
= AddReduceData(partition_points
, n_inputs
, output_width
, n_parts
)
602 m
.d
.comb
+= i
.eq_from(partition_points
, inputs
, part_ops
)
603 for idx
in range(len(self
.levels
)):
604 mcur
= self
.levels
[idx
]
605 if idx
in self
.register_levels
:
606 m
.d
.sync
+= mcur
.i
.eq(i
)
608 m
.d
.comb
+= mcur
.i
.eq(i
)
609 i
= mcur
.o
# for next loop
611 # output comes from last module
612 m
.d
.comb
+= self
.o
.eq(i
)
618 OP_MUL_SIGNED_HIGH
= 1
619 OP_MUL_SIGNED_UNSIGNED_HIGH
= 2 # a is signed, b is unsigned
620 OP_MUL_UNSIGNED_HIGH
= 3
623 def get_term(value
, shift
=0, enabled
=None):
624 if enabled
is not None:
625 value
= Mux(enabled
, value
, 0)
627 value
= Cat(Repl(C(0, 1), shift
), value
)
633 class ProductTerm(Elaboratable
):
634 """ this class creates a single product term (a[..]*b[..]).
635 it has a design flaw in that is the *output* that is selected,
636 where the multiplication(s) are combinatorially generated
640 def __init__(self
, width
, twidth
, pbwid
, a_index
, b_index
):
641 self
.a_index
= a_index
642 self
.b_index
= b_index
643 shift
= 8 * (self
.a_index
+ self
.b_index
)
649 self
.ti
= Signal(self
.width
, reset_less
=True)
650 self
.term
= Signal(twidth
, reset_less
=True)
651 self
.a
= Signal(twidth
//2, reset_less
=True)
652 self
.b
= Signal(twidth
//2, reset_less
=True)
653 self
.pb_en
= Signal(pbwid
, reset_less
=True)
656 min_index
= min(self
.a_index
, self
.b_index
)
657 max_index
= max(self
.a_index
, self
.b_index
)
658 for i
in range(min_index
, max_index
):
659 tl
.append(self
.pb_en
[i
])
660 name
= "te_%d_%d" % (self
.a_index
, self
.b_index
)
662 term_enabled
= Signal(name
=name
, reset_less
=True)
665 self
.enabled
= term_enabled
666 self
.term
.name
= "term_%d_%d" % (a_index
, b_index
) # rename
668 def elaborate(self
, platform
):
671 if self
.enabled
is not None:
672 m
.d
.comb
+= self
.enabled
.eq(~
(Cat(*self
.tl
).bool()))
674 bsa
= Signal(self
.width
, reset_less
=True)
675 bsb
= Signal(self
.width
, reset_less
=True)
676 a_index
, b_index
= self
.a_index
, self
.b_index
678 m
.d
.comb
+= bsa
.eq(self
.a
.part(a_index
* pwidth
, pwidth
))
679 m
.d
.comb
+= bsb
.eq(self
.b
.part(b_index
* pwidth
, pwidth
))
680 m
.d
.comb
+= self
.ti
.eq(bsa
* bsb
)
681 m
.d
.comb
+= self
.term
.eq(get_term(self
.ti
, self
.shift
, self
.enabled
))
683 #TODO: sort out width issues, get inputs a/b switched on/off.
684 #data going into Muxes is 1/2 the required width
688 bsa = Signal(self.twidth//2, reset_less=True)
689 bsb = Signal(self.twidth//2, reset_less=True)
690 asel = Signal(width, reset_less=True)
691 bsel = Signal(width, reset_less=True)
692 a_index, b_index = self.a_index, self.b_index
693 m.d.comb += asel.eq(self.a.part(a_index * pwidth, pwidth))
694 m.d.comb += bsel.eq(self.b.part(b_index * pwidth, pwidth))
695 m.d.comb += bsa.eq(get_term(asel, self.shift, self.enabled))
696 m.d.comb += bsb.eq(get_term(bsel, self.shift, self.enabled))
697 m.d.comb += self.ti.eq(bsa * bsb)
698 m.d.comb += self.term.eq(self.ti)
704 class ProductTerms(Elaboratable
):
705 """ creates a bank of product terms. also performs the actual bit-selection
706 this class is to be wrapped with a for-loop on the "a" operand.
707 it creates a second-level for-loop on the "b" operand.
709 def __init__(self
, width
, twidth
, pbwid
, a_index
, blen
):
710 self
.a_index
= a_index
715 self
.a
= Signal(twidth
//2, reset_less
=True)
716 self
.b
= Signal(twidth
//2, reset_less
=True)
717 self
.pb_en
= Signal(pbwid
, reset_less
=True)
718 self
.terms
= [Signal(twidth
, name
="term%d"%i, reset_less
=True) \
719 for i
in range(blen
)]
721 def elaborate(self
, platform
):
725 for b_index
in range(self
.blen
):
726 t
= ProductTerm(self
.pwidth
, self
.twidth
, self
.pbwid
,
727 self
.a_index
, b_index
)
728 setattr(m
.submodules
, "term_%d" % b_index
, t
)
730 m
.d
.comb
+= t
.a
.eq(self
.a
)
731 m
.d
.comb
+= t
.b
.eq(self
.b
)
732 m
.d
.comb
+= t
.pb_en
.eq(self
.pb_en
)
734 m
.d
.comb
+= self
.terms
[b_index
].eq(t
.term
)
739 class LSBNegTerm(Elaboratable
):
741 def __init__(self
, bit_width
):
742 self
.bit_width
= bit_width
743 self
.part
= Signal(reset_less
=True)
744 self
.signed
= Signal(reset_less
=True)
745 self
.op
= Signal(bit_width
, reset_less
=True)
746 self
.msb
= Signal(reset_less
=True)
747 self
.nt
= Signal(bit_width
*2, reset_less
=True)
748 self
.nl
= Signal(bit_width
*2, reset_less
=True)
750 def elaborate(self
, platform
):
753 bit_wid
= self
.bit_width
754 ext
= Repl(0, bit_wid
) # extend output to HI part
756 # determine sign of each incoming number *in this partition*
757 enabled
= Signal(reset_less
=True)
758 m
.d
.comb
+= enabled
.eq(self
.part
& self
.msb
& self
.signed
)
760 # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
761 # negation operation is split into a bitwise not and a +1.
762 # likewise for 16, 32, and 64-bit values.
764 # width-extended 1s complement if a is signed, otherwise zero
765 comb
+= self
.nt
.eq(Mux(enabled
, Cat(ext
, ~self
.op
), 0))
767 # add 1 if signed, otherwise add zero
768 comb
+= self
.nl
.eq(Cat(ext
, enabled
, Repl(0, bit_wid
-1)))
773 class Parts(Elaboratable
):
775 def __init__(self
, pbwid
, part_pts
, n_parts
):
778 self
.part_pts
= PartitionPoints
.like(part_pts
)
780 self
.parts
= [Signal(name
=f
"part_{i}", reset_less
=True)
781 for i
in range(n_parts
)]
783 def elaborate(self
, platform
):
786 part_pts
, parts
= self
.part_pts
, self
.parts
787 # collect part-bytes (double factor because the input is extended)
788 pbs
= Signal(self
.pbwid
, reset_less
=True)
790 for i
in range(self
.pbwid
):
791 pb
= Signal(name
="pb%d" % i
, reset_less
=True)
792 m
.d
.comb
+= pb
.eq(part_pts
.part_byte(i
))
794 m
.d
.comb
+= pbs
.eq(Cat(*tl
))
796 # negated-temporary copy of partition bits
797 npbs
= Signal
.like(pbs
, reset_less
=True)
798 m
.d
.comb
+= npbs
.eq(~pbs
)
799 byte_count
= 8 // len(parts
)
800 for i
in range(len(parts
)):
802 pbl
.append(npbs
[i
* byte_count
- 1])
803 for j
in range(i
* byte_count
, (i
+ 1) * byte_count
- 1):
805 pbl
.append(npbs
[(i
+ 1) * byte_count
- 1])
806 value
= Signal(len(pbl
), name
="value_%d" % i
, reset_less
=True)
807 m
.d
.comb
+= value
.eq(Cat(*pbl
))
808 m
.d
.comb
+= parts
[i
].eq(~
(value
).bool())
813 class Part(Elaboratable
):
814 """ a key class which, depending on the partitioning, will determine
815 what action to take when parts of the output are signed or unsigned.
817 this requires 2 pieces of data *per operand, per partition*:
818 whether the MSB is HI/LO (per partition!), and whether a signed
819 or unsigned operation has been *requested*.
821 once that is determined, signed is basically carried out
822 by splitting 2's complement into 1's complement plus one.
823 1's complement is just a bit-inversion.
825 the extra terms - as separate terms - are then thrown at the
826 AddReduce alongside the multiplication part-results.
828 def __init__(self
, part_pts
, width
, n_parts
, n_levels
, pbwid
):
831 self
.part_pts
= part_pts
834 self
.a
= Signal(64, reset_less
=True)
835 self
.b
= Signal(64, reset_less
=True)
836 self
.a_signed
= [Signal(name
=f
"a_signed_{i}", reset_less
=True)
838 self
.b_signed
= [Signal(name
=f
"_b_signed_{i}", reset_less
=True)
840 self
.pbs
= Signal(pbwid
, reset_less
=True)
843 self
.parts
= [Signal(name
=f
"part_{i}", reset_less
=True)
844 for i
in range(n_parts
)]
846 self
.not_a_term
= Signal(width
, reset_less
=True)
847 self
.neg_lsb_a_term
= Signal(width
, reset_less
=True)
848 self
.not_b_term
= Signal(width
, reset_less
=True)
849 self
.neg_lsb_b_term
= Signal(width
, reset_less
=True)
851 def elaborate(self
, platform
):
854 pbs
, parts
= self
.pbs
, self
.parts
855 part_pts
= self
.part_pts
856 m
.submodules
.p
= p
= Parts(self
.pbwid
, part_pts
, len(parts
))
857 m
.d
.comb
+= p
.part_pts
.eq(part_pts
)
860 byte_count
= 8 // len(parts
)
862 not_a_term
, neg_lsb_a_term
, not_b_term
, neg_lsb_b_term
= (
863 self
.not_a_term
, self
.neg_lsb_a_term
,
864 self
.not_b_term
, self
.neg_lsb_b_term
)
866 byte_width
= 8 // len(parts
) # byte width
867 bit_wid
= 8 * byte_width
# bit width
868 nat
, nbt
, nla
, nlb
= [], [], [], []
869 for i
in range(len(parts
)):
870 # work out bit-inverted and +1 term for a.
871 pa
= LSBNegTerm(bit_wid
)
872 setattr(m
.submodules
, "lnt_%d_a_%d" % (bit_wid
, i
), pa
)
873 m
.d
.comb
+= pa
.part
.eq(parts
[i
])
874 m
.d
.comb
+= pa
.op
.eq(self
.a
.part(bit_wid
* i
, bit_wid
))
875 m
.d
.comb
+= pa
.signed
.eq(self
.b_signed
[i
* byte_width
]) # yes b
876 m
.d
.comb
+= pa
.msb
.eq(self
.b
[(i
+ 1) * bit_wid
- 1]) # really, b
880 # work out bit-inverted and +1 term for b
881 pb
= LSBNegTerm(bit_wid
)
882 setattr(m
.submodules
, "lnt_%d_b_%d" % (bit_wid
, i
), pb
)
883 m
.d
.comb
+= pb
.part
.eq(parts
[i
])
884 m
.d
.comb
+= pb
.op
.eq(self
.b
.part(bit_wid
* i
, bit_wid
))
885 m
.d
.comb
+= pb
.signed
.eq(self
.a_signed
[i
* byte_width
]) # yes a
886 m
.d
.comb
+= pb
.msb
.eq(self
.a
[(i
+ 1) * bit_wid
- 1]) # really, a
890 # concatenate together and return all 4 results.
891 m
.d
.comb
+= [not_a_term
.eq(Cat(*nat
)),
892 not_b_term
.eq(Cat(*nbt
)),
893 neg_lsb_a_term
.eq(Cat(*nla
)),
894 neg_lsb_b_term
.eq(Cat(*nlb
)),
900 class IntermediateOut(Elaboratable
):
901 """ selects the HI/LO part of the multiplication, for a given bit-width
902 the output is also reconstructed in its SIMD (partition) lanes.
904 def __init__(self
, width
, out_wid
, n_parts
):
906 self
.n_parts
= n_parts
907 self
.part_ops
= [Signal(2, name
="dpop%d" % i
, reset_less
=True)
909 self
.intermed
= Signal(out_wid
, reset_less
=True)
910 self
.output
= Signal(out_wid
//2, reset_less
=True)
912 def elaborate(self
, platform
):
918 for i
in range(self
.n_parts
):
919 op
= Signal(w
, reset_less
=True, name
="op%d_%d" % (w
, i
))
921 Mux(self
.part_ops
[sel
* i
] == OP_MUL_LOW
,
922 self
.intermed
.part(i
* w
*2, w
),
923 self
.intermed
.part(i
* w
*2 + w
, w
)))
925 m
.d
.comb
+= self
.output
.eq(Cat(*ol
))
930 class FinalOut(Elaboratable
):
931 """ selects the final output based on the partitioning.
933 each byte is selectable independently, i.e. it is possible
934 that some partitions requested 8-bit computation whilst others
935 requested 16 or 32 bit.
937 def __init__(self
, output_width
, n_parts
, part_pts
):
938 self
.part_pts
= part_pts
939 self
.i
= IntermediateData(part_pts
, output_width
, n_parts
)
940 self
.out_wid
= output_width
//2
942 self
.out
= Signal(self
.out_wid
, reset_less
=True)
943 self
.intermediate_output
= Signal(output_width
, reset_less
=True)
945 def elaborate(self
, platform
):
948 part_pts
= self
.part_pts
949 m
.submodules
.p_8
= p_8
= Parts(8, part_pts
, 8)
950 m
.submodules
.p_16
= p_16
= Parts(8, part_pts
, 4)
951 m
.submodules
.p_32
= p_32
= Parts(8, part_pts
, 2)
952 m
.submodules
.p_64
= p_64
= Parts(8, part_pts
, 1)
954 out_part_pts
= self
.i
.part_pts
957 d8
= [Signal(name
=f
"d8_{i}", reset_less
=True) for i
in range(8)]
958 d16
= [Signal(name
=f
"d16_{i}", reset_less
=True) for i
in range(4)]
959 d32
= [Signal(name
=f
"d32_{i}", reset_less
=True) for i
in range(2)]
961 i8
= Signal(self
.out_wid
, reset_less
=True)
962 i16
= Signal(self
.out_wid
, reset_less
=True)
963 i32
= Signal(self
.out_wid
, reset_less
=True)
964 i64
= Signal(self
.out_wid
, reset_less
=True)
966 m
.d
.comb
+= p_8
.part_pts
.eq(out_part_pts
)
967 m
.d
.comb
+= p_16
.part_pts
.eq(out_part_pts
)
968 m
.d
.comb
+= p_32
.part_pts
.eq(out_part_pts
)
969 m
.d
.comb
+= p_64
.part_pts
.eq(out_part_pts
)
971 for i
in range(len(p_8
.parts
)):
972 m
.d
.comb
+= d8
[i
].eq(p_8
.parts
[i
])
973 for i
in range(len(p_16
.parts
)):
974 m
.d
.comb
+= d16
[i
].eq(p_16
.parts
[i
])
975 for i
in range(len(p_32
.parts
)):
976 m
.d
.comb
+= d32
[i
].eq(p_32
.parts
[i
])
977 m
.d
.comb
+= i8
.eq(self
.i
.outputs
[0])
978 m
.d
.comb
+= i16
.eq(self
.i
.outputs
[1])
979 m
.d
.comb
+= i32
.eq(self
.i
.outputs
[2])
980 m
.d
.comb
+= i64
.eq(self
.i
.outputs
[3])
984 # select one of the outputs: d8 selects i8, d16 selects i16
985 # d32 selects i32, and the default is i64.
986 # d8 and d16 are ORed together in the first Mux
987 # then the 2nd selects either i8 or i16.
988 # if neither d8 nor d16 are set, d32 selects either i32 or i64.
989 op
= Signal(8, reset_less
=True, name
="op_%d" % i
)
991 Mux(d8
[i
] | d16
[i
// 2],
992 Mux(d8
[i
], i8
.part(i
* 8, 8), i16
.part(i
* 8, 8)),
993 Mux(d32
[i
// 4], i32
.part(i
* 8, 8), i64
.part(i
* 8, 8))))
995 m
.d
.comb
+= self
.out
.eq(Cat(*ol
))
996 m
.d
.comb
+= self
.intermediate_output
.eq(self
.i
.intermediate_output
)
1000 class OrMod(Elaboratable
):
1001 """ ORs four values together in a hierarchical tree
1003 def __init__(self
, wid
):
1005 self
.orin
= [Signal(wid
, name
="orin%d" % i
, reset_less
=True)
1007 self
.orout
= Signal(wid
, reset_less
=True)
1009 def elaborate(self
, platform
):
1011 or1
= Signal(self
.wid
, reset_less
=True)
1012 or2
= Signal(self
.wid
, reset_less
=True)
1013 m
.d
.comb
+= or1
.eq(self
.orin
[0] | self
.orin
[1])
1014 m
.d
.comb
+= or2
.eq(self
.orin
[2] | self
.orin
[3])
1015 m
.d
.comb
+= self
.orout
.eq(or1 | or2
)
1020 class Signs(Elaboratable
):
1021 """ determines whether a or b are signed numbers
1022 based on the required operation type (OP_MUL_*)
1026 self
.part_ops
= Signal(2, reset_less
=True)
1027 self
.a_signed
= Signal(reset_less
=True)
1028 self
.b_signed
= Signal(reset_less
=True)
1030 def elaborate(self
, platform
):
1034 asig
= self
.part_ops
!= OP_MUL_UNSIGNED_HIGH
1035 bsig
= (self
.part_ops
== OP_MUL_LOW
) \
1036 |
(self
.part_ops
== OP_MUL_SIGNED_HIGH
)
1037 m
.d
.comb
+= self
.a_signed
.eq(asig
)
1038 m
.d
.comb
+= self
.b_signed
.eq(bsig
)
1043 class IntermediateData
:
1045 def __init__(self
, part_pts
, output_width
, n_parts
):
1046 self
.part_ops
= [Signal(2, name
=f
"part_ops_{i}", reset_less
=True)
1047 for i
in range(n_parts
)]
1048 self
.part_pts
= part_pts
.like()
1049 self
.outputs
= [Signal(output_width
, name
="io%d" % i
, reset_less
=True)
1051 # intermediates (needed for unit tests)
1052 self
.intermediate_output
= Signal(output_width
)
1054 def eq_from(self
, part_pts
, outputs
, intermediate_output
,
1056 return [self
.part_pts
.eq(part_pts
)] + \
1057 [self
.intermediate_output
.eq(intermediate_output
)] + \
1058 [self
.outputs
[i
].eq(outputs
[i
])
1059 for i
in range(4)] + \
1060 [self
.part_ops
[i
].eq(part_ops
[i
])
1061 for i
in range(len(self
.part_ops
))]
1064 return self
.eq_from(rhs
.part_pts
, rhs
.outputs
,
1065 rhs
.intermediate_output
, rhs
.part_ops
)
1070 def __init__(self
, partition_points
):
1073 self
.part_pts
= partition_points
.like()
1074 self
.part_ops
= [Signal(2, name
=f
"part_ops_{i}") for i
in range(8)]
1076 def eq_from(self
, part_pts
, inputs
, part_ops
):
1077 return [self
.part_pts
.eq(part_pts
)] + \
1078 [self
.a
.eq(a
), self
.b
.eq(b
)] + \
1079 [self
.part_ops
[i
].eq(part_ops
[i
])
1080 for i
in range(len(self
.part_ops
))]
1083 return self
.eq_from(rhs
.part_pts
, rhs
.a
, rhs
.b
, rhs
.part_ops
)
1086 class AllTerms(Elaboratable
):
1087 """Set of terms to be added together
1090 def __init__(self
, n_inputs
, output_width
, n_parts
, register_levels
,
1092 """Create an ``AddReduce``.
1094 :param inputs: input ``Signal``s to be summed.
1095 :param output_width: bit-width of ``output``.
1096 :param register_levels: List of nesting levels that should have
1098 :param partition_points: the input partition points.
1100 self
.i
= AllTermsData(partition_points
)
1101 self
.register_levels
= register_levels
1102 self
.n_inputs
= n_inputs
1103 self
.n_parts
= n_parts
1104 self
.output_width
= output_width
1105 self
.o
= AddReduceData(self
.i
.part_pts
, n_inputs
,
1106 output_width
, n_parts
)
1108 def elaborate(self
, platform
):
1111 eps
= self
.i
.part_pts
1113 # collect part-bytes
1114 pbs
= Signal(8, reset_less
=True)
1117 pb
= Signal(name
="pb%d" % i
, reset_less
=True)
1118 m
.d
.comb
+= pb
.eq(eps
.part_byte(i
))
1120 m
.d
.comb
+= pbs
.eq(Cat(*tl
))
1127 setattr(m
.submodules
, "signs%d" % i
, s
)
1128 m
.d
.comb
+= s
.part_ops
.eq(self
.i
.part_ops
[i
])
1130 n_levels
= len(self
.register_levels
)+1
1131 m
.submodules
.part_8
= part_8
= Part(eps
, 128, 8, n_levels
, 8)
1132 m
.submodules
.part_16
= part_16
= Part(eps
, 128, 4, n_levels
, 8)
1133 m
.submodules
.part_32
= part_32
= Part(eps
, 128, 2, n_levels
, 8)
1134 m
.submodules
.part_64
= part_64
= Part(eps
, 128, 1, n_levels
, 8)
1135 nat_l
, nbt_l
, nla_l
, nlb_l
= [], [], [], []
1136 for mod
in [part_8
, part_16
, part_32
, part_64
]:
1137 m
.d
.comb
+= mod
.a
.eq(self
.i
.a
)
1138 m
.d
.comb
+= mod
.b
.eq(self
.i
.b
)
1139 for i
in range(len(signs
)):
1140 m
.d
.comb
+= mod
.a_signed
[i
].eq(signs
[i
].a_signed
)
1141 m
.d
.comb
+= mod
.b_signed
[i
].eq(signs
[i
].b_signed
)
1142 m
.d
.comb
+= mod
.pbs
.eq(pbs
)
1143 nat_l
.append(mod
.not_a_term
)
1144 nbt_l
.append(mod
.not_b_term
)
1145 nla_l
.append(mod
.neg_lsb_a_term
)
1146 nlb_l
.append(mod
.neg_lsb_b_term
)
1150 for a_index
in range(8):
1151 t
= ProductTerms(8, 128, 8, a_index
, 8)
1152 setattr(m
.submodules
, "terms_%d" % a_index
, t
)
1154 m
.d
.comb
+= t
.a
.eq(self
.i
.a
)
1155 m
.d
.comb
+= t
.b
.eq(self
.i
.b
)
1156 m
.d
.comb
+= t
.pb_en
.eq(pbs
)
1158 for term
in t
.terms
:
1161 # it's fine to bitwise-or data together since they are never enabled
1163 m
.submodules
.nat_or
= nat_or
= OrMod(128)
1164 m
.submodules
.nbt_or
= nbt_or
= OrMod(128)
1165 m
.submodules
.nla_or
= nla_or
= OrMod(128)
1166 m
.submodules
.nlb_or
= nlb_or
= OrMod(128)
1167 for l
, mod
in [(nat_l
, nat_or
),
1171 for i
in range(len(l
)):
1172 m
.d
.comb
+= mod
.orin
[i
].eq(l
[i
])
1173 terms
.append(mod
.orout
)
1175 # copy the intermediate terms to the output
1176 for i
, value
in enumerate(terms
):
1177 m
.d
.comb
+= self
.o
.terms
[i
].eq(value
)
1179 # copy reg part points and part ops to output
1180 m
.d
.comb
+= self
.o
.part_pts
.eq(eps
)
1181 m
.d
.comb
+= [self
.o
.part_ops
[i
].eq(self
.i
.part_ops
[i
])
1182 for i
in range(len(self
.i
.part_ops
))]
1187 class Intermediates(Elaboratable
):
1188 """ Intermediate output modules
1191 def __init__(self
, output_width
, n_parts
, partition_points
):
1192 self
.i
= FinalReduceData(partition_points
, output_width
, n_parts
)
1193 self
.o
= IntermediateData(partition_points
, output_width
, n_parts
)
1195 def elaborate(self
, platform
):
1198 out_part_ops
= self
.i
.part_ops
1199 out_part_pts
= self
.i
.part_pts
1202 m
.submodules
.io64
= io64
= IntermediateOut(64, 128, 1)
1203 m
.d
.comb
+= io64
.intermed
.eq(self
.i
.output
)
1205 m
.d
.comb
+= io64
.part_ops
[i
].eq(out_part_ops
[i
])
1206 m
.d
.comb
+= self
.o
.outputs
[3].eq(io64
.output
)
1209 m
.submodules
.io32
= io32
= IntermediateOut(32, 128, 2)
1210 m
.d
.comb
+= io32
.intermed
.eq(self
.i
.output
)
1212 m
.d
.comb
+= io32
.part_ops
[i
].eq(out_part_ops
[i
])
1213 m
.d
.comb
+= self
.o
.outputs
[2].eq(io32
.output
)
1216 m
.submodules
.io16
= io16
= IntermediateOut(16, 128, 4)
1217 m
.d
.comb
+= io16
.intermed
.eq(self
.i
.output
)
1219 m
.d
.comb
+= io16
.part_ops
[i
].eq(out_part_ops
[i
])
1220 m
.d
.comb
+= self
.o
.outputs
[1].eq(io16
.output
)
1223 m
.submodules
.io8
= io8
= IntermediateOut(8, 128, 8)
1224 m
.d
.comb
+= io8
.intermed
.eq(self
.i
.output
)
1226 m
.d
.comb
+= io8
.part_ops
[i
].eq(out_part_ops
[i
])
1227 m
.d
.comb
+= self
.o
.outputs
[0].eq(io8
.output
)
1230 m
.d
.comb
+= self
.o
.part_ops
[i
].eq(out_part_ops
[i
])
1231 m
.d
.comb
+= self
.o
.part_pts
.eq(out_part_pts
)
1232 m
.d
.comb
+= self
.o
.intermediate_output
.eq(self
.i
.output
)
1237 class Mul8_16_32_64(Elaboratable
):
1238 """Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
1240 Supports partitioning into any combination of 8, 16, 32, and 64-bit
1241 partitions on naturally-aligned boundaries. Supports the operation being
1242 set for each partition independently.
1244 :attribute part_pts: the input partition points. Has a partition point at
1245 multiples of 8 in 0 < i < 64. Each partition point's associated
1246 ``Value`` is a ``Signal``. Modification not supported, except for by
1248 :attribute part_ops: the operation for each byte. The operation for a
1249 particular partition is selected by assigning the selected operation
1250 code to each byte in the partition. The allowed operation codes are:
1252 :attribute OP_MUL_LOW: the LSB half of the product. Equivalent to
1253 RISC-V's `mul` instruction.
1254 :attribute OP_MUL_SIGNED_HIGH: the MSB half of the product where both
1255 ``a`` and ``b`` are signed. Equivalent to RISC-V's `mulh`
1257 :attribute OP_MUL_SIGNED_UNSIGNED_HIGH: the MSB half of the product
1258 where ``a`` is signed and ``b`` is unsigned. Equivalent to RISC-V's
1259 `mulhsu` instruction.
1260 :attribute OP_MUL_UNSIGNED_HIGH: the MSB half of the product where both
1261 ``a`` and ``b`` are unsigned. Equivalent to RISC-V's `mulhu`
1265 def __init__(self
, register_levels
=()):
1266 """ register_levels: specifies the points in the cascade at which
1267 flip-flops are to be inserted.
1271 self
.register_levels
= list(register_levels
)
1274 self
.part_pts
= PartitionPoints()
1275 for i
in range(8, 64, 8):
1276 self
.part_pts
[i
] = Signal(name
=f
"part_pts_{i}")
1277 self
.part_ops
= [Signal(2, name
=f
"part_ops_{i}") for i
in range(8)]
1281 # intermediates (needed for unit tests)
1282 self
.intermediate_output
= Signal(128)
1285 self
.output
= Signal(64)
1287 def elaborate(self
, platform
):
1290 part_pts
= self
.part_pts
1293 n_parts
= 8 #len(self.part_pts)
1294 t
= AllTerms(n_inputs
, 128, n_parts
, self
.register_levels
, part_pts
)
1295 m
.submodules
.allterms
= t
1296 m
.d
.comb
+= t
.i
.a
.eq(self
.a
)
1297 m
.d
.comb
+= t
.i
.b
.eq(self
.b
)
1298 m
.d
.comb
+= t
.i
.part_pts
.eq(part_pts
)
1300 m
.d
.comb
+= t
.i
.part_ops
[i
].eq(self
.part_ops
[i
])
1304 add_reduce
= AddReduce(terms
,
1306 self
.register_levels
,
1310 out_part_ops
= add_reduce
.o
.part_ops
1311 out_part_pts
= add_reduce
.o
.part_pts
1313 m
.submodules
.add_reduce
= add_reduce
1315 interm
= Intermediates(128, 8, part_pts
)
1316 m
.submodules
.intermediates
= interm
1317 m
.d
.comb
+= interm
.i
.eq(add_reduce
.o
)
1320 m
.submodules
.finalout
= finalout
= FinalOut(128, 8, part_pts
)
1321 m
.d
.comb
+= finalout
.i
.eq(interm
.o
)
1322 m
.d
.comb
+= self
.output
.eq(finalout
.out
)
1323 m
.d
.comb
+= self
.intermediate_output
.eq(finalout
.intermediate_output
)
1328 if __name__
== "__main__":
1332 m
.intermediate_output
,
1335 *m
.part_pts
.values()])