intel/blorp_blit: Add split_blorp_blit_debug switch
[mesa.git] / src / intel / blorp / blorp.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <errno.h>
25
26 #include "program/prog_instruction.h"
27
28 #include "blorp_priv.h"
29 #include "brw_compiler.h"
30 #include "brw_nir.h"
31
32 void
33 blorp_init(struct blorp_context *blorp, void *driver_ctx,
34 struct isl_device *isl_dev)
35 {
36 blorp->driver_ctx = driver_ctx;
37 blorp->isl_dev = isl_dev;
38 }
39
40 void
41 blorp_finish(struct blorp_context *blorp)
42 {
43 blorp->driver_ctx = NULL;
44 }
45
46 void
47 blorp_batch_init(struct blorp_context *blorp,
48 struct blorp_batch *batch, void *driver_batch,
49 enum blorp_batch_flags flags)
50 {
51 batch->blorp = blorp;
52 batch->driver_batch = driver_batch;
53 batch->flags = flags;
54 }
55
56 void
57 blorp_batch_finish(struct blorp_batch *batch)
58 {
59 batch->blorp = NULL;
60 }
61
62 void
63 brw_blorp_surface_info_init(struct blorp_context *blorp,
64 struct brw_blorp_surface_info *info,
65 const struct blorp_surf *surf,
66 unsigned int level, unsigned int layer,
67 enum isl_format format, bool is_render_target)
68 {
69 info->enabled = true;
70
71 if (format == ISL_FORMAT_UNSUPPORTED)
72 format = surf->surf->format;
73
74 if (format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
75 /* Unfortunately, ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as
76 * a render target, which would prevent us from blitting to 24-bit
77 * depth. The miptree consists of 32 bits per pixel, arranged as 24-bit
78 * depth values interleaved with 8 "don't care" bits. Since depth
79 * values don't require any blending, it doesn't matter how we interpret
80 * the bit pattern as long as we copy the right amount of data, so just
81 * map it as 8-bit BGRA.
82 */
83 format = ISL_FORMAT_B8G8R8A8_UNORM;
84 } else if (surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) {
85 assert(surf->surf->format == ISL_FORMAT_R8_UINT);
86 /* Prior to Broadwell, we can't render to R8_UINT */
87 if (blorp->isl_dev->info->gen < 8)
88 format = ISL_FORMAT_R8_UNORM;
89 }
90
91 info->surf = *surf->surf;
92 info->addr = surf->addr;
93
94 info->aux_usage = surf->aux_usage;
95 if (info->aux_usage != ISL_AUX_USAGE_NONE) {
96 info->aux_surf = *surf->aux_surf;
97 info->aux_addr = surf->aux_addr;
98 }
99
100 info->clear_color = surf->clear_color;
101
102 info->view = (struct isl_view) {
103 .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
104 ISL_SURF_USAGE_TEXTURE_BIT,
105 .format = format,
106 .base_level = level,
107 .levels = 1,
108 .swizzle = ISL_SWIZZLE_IDENTITY,
109 };
110
111 info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
112 info->surf.logical_level0_px.array_len);
113
114 if (!is_render_target &&
115 (info->surf.dim == ISL_SURF_DIM_3D ||
116 info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
117 /* 3-D textures don't support base_array layer and neither do 2-D
118 * multisampled textures on IVB so we need to pass it through the
119 * sampler in those cases. These are also two cases where we are
120 * guaranteed that we won't be doing any funny surface hacks.
121 */
122 info->view.base_array_layer = 0;
123 info->z_offset = layer;
124 } else {
125 info->view.base_array_layer = layer;
126
127 assert(info->view.array_len >= info->view.base_array_layer);
128 info->view.array_len -= info->view.base_array_layer;
129 info->z_offset = 0;
130 }
131
132 /* Sandy Bridge has a limit of a maximum of 512 layers for layered
133 * rendering.
134 */
135 if (is_render_target && blorp->isl_dev->info->gen == 6)
136 info->view.array_len = MIN2(info->view.array_len, 512);
137 }
138
139
140 void
141 blorp_params_init(struct blorp_params *params)
142 {
143 memset(params, 0, sizeof(*params));
144 params->num_samples = 1;
145 params->num_draw_buffers = 1;
146 params->num_layers = 1;
147 }
148
149 void
150 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key)
151 {
152 memset(wm_key, 0, sizeof(*wm_key));
153 wm_key->nr_color_regions = 1;
154 for (int i = 0; i < MAX_SAMPLERS; i++)
155 wm_key->tex.swizzles[i] = SWIZZLE_XYZW;
156 }
157
158 const unsigned *
159 blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx,
160 struct nir_shader *nir,
161 const struct brw_wm_prog_key *wm_key,
162 bool use_repclear,
163 struct brw_wm_prog_data *wm_prog_data,
164 unsigned *program_size)
165 {
166 const struct brw_compiler *compiler = blorp->compiler;
167
168 nir->options =
169 compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
170
171 memset(wm_prog_data, 0, sizeof(*wm_prog_data));
172
173 assert(exec_list_is_empty(&nir->uniforms));
174 wm_prog_data->base.nr_params = 0;
175 wm_prog_data->base.param = NULL;
176
177 /* BLORP always just uses the first two binding table entries */
178 wm_prog_data->binding_table.render_target_start = BLORP_RENDERBUFFER_BT_INDEX;
179 wm_prog_data->base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
180
181 nir = brw_preprocess_nir(compiler, nir);
182 nir_remove_dead_variables(nir, nir_var_shader_in);
183 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
184
185 const unsigned *program =
186 brw_compile_fs(compiler, blorp->driver_ctx, mem_ctx, wm_key,
187 wm_prog_data, nir, NULL, -1, -1, false, use_repclear,
188 NULL, program_size, NULL);
189
190 return program;
191 }
192
193 const unsigned *
194 blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
195 struct nir_shader *nir,
196 struct brw_vs_prog_data *vs_prog_data,
197 unsigned *program_size)
198 {
199 const struct brw_compiler *compiler = blorp->compiler;
200
201 nir->options =
202 compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions;
203
204 nir = brw_preprocess_nir(compiler, nir);
205 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
206
207 vs_prog_data->inputs_read = nir->info->inputs_read;
208
209 brw_compute_vue_map(compiler->devinfo,
210 &vs_prog_data->base.vue_map,
211 nir->info->outputs_written,
212 nir->info->separate_shader);
213
214 struct brw_vs_prog_key vs_key = { 0, };
215
216 const unsigned *program =
217 brw_compile_vs(compiler, blorp->driver_ctx, mem_ctx,
218 &vs_key, vs_prog_data, nir,
219 NULL, false, -1, program_size, NULL);
220
221 return program;
222 }
223
224 void
225 blorp_gen6_hiz_op(struct blorp_batch *batch,
226 struct blorp_surf *surf, unsigned level, unsigned layer,
227 enum blorp_hiz_op op)
228 {
229 struct blorp_params params;
230 blorp_params_init(&params);
231
232 params.hiz_op = op;
233
234 brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level, layer,
235 surf->surf->format, true);
236
237 /* Align the rectangle primitive to 8x4 pixels.
238 *
239 * During fast depth clears, the emitted rectangle primitive must be
240 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
241 * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
242 * PRM):
243 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
244 * aligned to an 8x4 pixel block relative to the upper left corner
245 * of the depth buffer [...]
246 *
247 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
248 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
249 * Ivybridge simulator require the alignment.
250 *
251 * To be safe, let's just align the rect for all hiz operations and all
252 * hardware generations.
253 *
254 * However, for some miptree slices of a Z24 texture, emitting an 8x4
255 * aligned rectangle that covers the slice may clobber adjacent slices if
256 * we strictly adhered to the texture alignments specified in the PRM. The
257 * Ivybridge PRM, Section "Alignment Unit Size", states that
258 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
259 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
260 * prevents the clobbering.
261 */
262 params.x1 = minify(params.depth.surf.logical_level0_px.width,
263 params.depth.view.base_level);
264 params.y1 = minify(params.depth.surf.logical_level0_px.height,
265 params.depth.view.base_level);
266 params.x1 = ALIGN(params.x1, 8);
267 params.y1 = ALIGN(params.y1, 4);
268
269 if (params.depth.view.base_level == 0) {
270 /* TODO: What about MSAA? */
271 params.depth.surf.logical_level0_px.width = params.x1;
272 params.depth.surf.logical_level0_px.height = params.y1;
273 }
274
275 params.dst.surf.samples = params.depth.surf.samples;
276 params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
277 params.depth_format = isl_format_get_depth_format(surf->surf->format, false);
278 params.num_samples = params.depth.surf.samples;
279
280 batch->blorp->exec(batch, &params);
281 }