2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "program/prog_instruction.h"
28 #include "blorp_priv.h"
29 #include "compiler/brw_compiler.h"
30 #include "compiler/brw_nir.h"
33 blorp_init(struct blorp_context
*blorp
, void *driver_ctx
,
34 struct isl_device
*isl_dev
)
36 blorp
->driver_ctx
= driver_ctx
;
37 blorp
->isl_dev
= isl_dev
;
41 blorp_finish(struct blorp_context
*blorp
)
43 blorp
->driver_ctx
= NULL
;
47 blorp_batch_init(struct blorp_context
*blorp
,
48 struct blorp_batch
*batch
, void *driver_batch
,
49 enum blorp_batch_flags flags
)
52 batch
->driver_batch
= driver_batch
;
57 blorp_batch_finish(struct blorp_batch
*batch
)
63 brw_blorp_surface_info_init(struct blorp_context
*blorp
,
64 struct brw_blorp_surface_info
*info
,
65 const struct blorp_surf
*surf
,
66 unsigned int level
, unsigned int layer
,
67 enum isl_format format
, bool is_render_target
)
69 assert(level
< surf
->surf
->levels
);
70 assert(layer
< MAX2(surf
->surf
->logical_level0_px
.depth
>> level
,
71 surf
->surf
->logical_level0_px
.array_len
));
75 if (format
== ISL_FORMAT_UNSUPPORTED
)
76 format
= surf
->surf
->format
;
78 if (format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
79 /* Unfortunately, ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as
80 * a render target, which would prevent us from blitting to 24-bit
81 * depth. The miptree consists of 32 bits per pixel, arranged as 24-bit
82 * depth values interleaved with 8 "don't care" bits. Since depth
83 * values don't require any blending, it doesn't matter how we interpret
84 * the bit pattern as long as we copy the right amount of data, so just
85 * map it as 8-bit BGRA.
87 format
= ISL_FORMAT_B8G8R8A8_UNORM
;
90 info
->surf
= *surf
->surf
;
91 info
->addr
= surf
->addr
;
93 info
->aux_usage
= surf
->aux_usage
;
94 if (info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
95 info
->aux_surf
= *surf
->aux_surf
;
96 info
->aux_addr
= surf
->aux_addr
;
97 assert(level
< info
->aux_surf
.levels
);
98 assert(layer
< MAX2(info
->aux_surf
.logical_level0_px
.depth
>> level
,
99 info
->aux_surf
.logical_level0_px
.array_len
));
102 info
->clear_color
= surf
->clear_color
;
104 info
->view
= (struct isl_view
) {
105 .usage
= is_render_target
? ISL_SURF_USAGE_RENDER_TARGET_BIT
:
106 ISL_SURF_USAGE_TEXTURE_BIT
,
110 .swizzle
= ISL_SWIZZLE_IDENTITY
,
113 info
->view
.array_len
= MAX2(info
->surf
.logical_level0_px
.depth
,
114 info
->surf
.logical_level0_px
.array_len
);
116 if (!is_render_target
&&
117 (info
->surf
.dim
== ISL_SURF_DIM_3D
||
118 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)) {
119 /* 3-D textures don't support base_array layer and neither do 2-D
120 * multisampled textures on IVB so we need to pass it through the
121 * sampler in those cases. These are also two cases where we are
122 * guaranteed that we won't be doing any funny surface hacks.
124 info
->view
.base_array_layer
= 0;
125 info
->z_offset
= layer
;
127 info
->view
.base_array_layer
= layer
;
129 assert(info
->view
.array_len
>= info
->view
.base_array_layer
);
130 info
->view
.array_len
-= info
->view
.base_array_layer
;
134 /* Sandy Bridge and earlier have a limit of a maximum of 512 layers for
137 if (is_render_target
&& blorp
->isl_dev
->info
->gen
<= 6)
138 info
->view
.array_len
= MIN2(info
->view
.array_len
, 512);
143 blorp_params_init(struct blorp_params
*params
)
145 memset(params
, 0, sizeof(*params
));
146 params
->num_samples
= 1;
147 params
->num_draw_buffers
= 1;
148 params
->num_layers
= 1;
152 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key
*wm_key
)
154 memset(wm_key
, 0, sizeof(*wm_key
));
155 wm_key
->nr_color_regions
= 1;
156 for (int i
= 0; i
< MAX_SAMPLERS
; i
++)
157 wm_key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;
161 blorp_compile_fs(struct blorp_context
*blorp
, void *mem_ctx
,
162 struct nir_shader
*nir
,
163 struct brw_wm_prog_key
*wm_key
,
165 struct brw_wm_prog_data
*wm_prog_data
,
166 unsigned *program_size
)
168 const struct brw_compiler
*compiler
= blorp
->compiler
;
171 compiler
->glsl_compiler_options
[MESA_SHADER_FRAGMENT
].NirOptions
;
173 memset(wm_prog_data
, 0, sizeof(*wm_prog_data
));
175 assert(exec_list_is_empty(&nir
->uniforms
));
176 wm_prog_data
->base
.nr_params
= 0;
177 wm_prog_data
->base
.param
= NULL
;
179 /* BLORP always just uses the first two binding table entries */
180 wm_prog_data
->binding_table
.render_target_start
= BLORP_RENDERBUFFER_BT_INDEX
;
181 wm_prog_data
->base
.binding_table
.texture_start
= BLORP_TEXTURE_BT_INDEX
;
183 nir
= brw_preprocess_nir(compiler
, nir
);
184 nir_remove_dead_variables(nir
, nir_var_shader_in
);
185 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
187 if (blorp
->compiler
->devinfo
->gen
< 6) {
188 if (nir
->info
.fs
.uses_discard
)
189 wm_key
->iz_lookup
|= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
;
191 wm_key
->input_slots_valid
= nir
->info
.inputs_read
| VARYING_BIT_POS
;
194 const unsigned *program
=
195 brw_compile_fs(compiler
, blorp
->driver_ctx
, mem_ctx
, wm_key
,
196 wm_prog_data
, nir
, NULL
, -1, -1, false, use_repclear
,
197 NULL
, program_size
, NULL
);
203 blorp_compile_vs(struct blorp_context
*blorp
, void *mem_ctx
,
204 struct nir_shader
*nir
,
205 struct brw_vs_prog_data
*vs_prog_data
,
206 unsigned *program_size
)
208 const struct brw_compiler
*compiler
= blorp
->compiler
;
211 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].NirOptions
;
213 nir
= brw_preprocess_nir(compiler
, nir
);
214 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
216 vs_prog_data
->inputs_read
= nir
->info
.inputs_read
;
218 brw_compute_vue_map(compiler
->devinfo
,
219 &vs_prog_data
->base
.vue_map
,
220 nir
->info
.outputs_written
,
221 nir
->info
.separate_shader
);
223 struct brw_vs_prog_key vs_key
= { 0, };
225 const unsigned *program
=
226 brw_compile_vs(compiler
, blorp
->driver_ctx
, mem_ctx
,
227 &vs_key
, vs_prog_data
, nir
,
228 NULL
, false, -1, program_size
, NULL
);
233 struct blorp_sf_key
{
234 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_GEN4_SF */
236 struct brw_sf_prog_key key
;
240 blorp_ensure_sf_program(struct blorp_context
*blorp
,
241 struct blorp_params
*params
)
243 const struct brw_wm_prog_data
*wm_prog_data
= params
->wm_prog_data
;
244 assert(params
->wm_prog_data
);
246 /* Gen6+ doesn't need a strips and fans program */
247 if (blorp
->compiler
->devinfo
->gen
>= 6)
250 struct blorp_sf_key key
= {
251 .shader_type
= BLORP_SHADER_TYPE_GEN4_SF
,
254 /* Everything gets compacted in vertex setup, so we just need a
255 * pass-through for the correct number of input varyings.
257 const uint64_t slots_valid
= VARYING_BIT_POS
|
258 ((1ull << wm_prog_data
->num_varying_inputs
) - 1) << VARYING_SLOT_VAR0
;
260 key
.key
.attrs
= slots_valid
;
261 key
.key
.primitive
= BRW_SF_PRIM_TRIANGLES
;
262 key
.key
.contains_flat_varying
= wm_prog_data
->contains_flat_varying
;
264 STATIC_ASSERT(sizeof(key
.key
.interp_mode
) ==
265 sizeof(wm_prog_data
->interp_mode
));
266 memcpy(key
.key
.interp_mode
, wm_prog_data
->interp_mode
,
267 sizeof(key
.key
.interp_mode
));
269 if (blorp
->lookup_shader(blorp
, &key
, sizeof(key
),
270 ¶ms
->sf_prog_kernel
, ¶ms
->sf_prog_data
))
273 void *mem_ctx
= ralloc_context(NULL
);
275 const unsigned *program
;
276 unsigned program_size
;
278 struct brw_vue_map vue_map
;
279 brw_compute_vue_map(blorp
->compiler
->devinfo
, &vue_map
, slots_valid
, false);
281 struct brw_sf_prog_data prog_data_tmp
;
282 program
= brw_compile_sf(blorp
->compiler
, mem_ctx
, &key
.key
,
283 &prog_data_tmp
, &vue_map
, &program_size
);
286 blorp
->upload_shader(blorp
, &key
, sizeof(key
), program
, program_size
,
287 (void *)&prog_data_tmp
, sizeof(prog_data_tmp
),
288 ¶ms
->sf_prog_kernel
, ¶ms
->sf_prog_data
);
290 ralloc_free(mem_ctx
);
296 blorp_hiz_op(struct blorp_batch
*batch
, struct blorp_surf
*surf
,
297 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
298 enum blorp_hiz_op op
)
300 struct blorp_params params
;
301 blorp_params_init(¶ms
);
304 params
.full_surface_hiz_op
= true;
306 for (uint32_t a
= 0; a
< num_layers
; a
++) {
307 const uint32_t layer
= start_layer
+ a
;
309 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, surf
, level
,
310 layer
, surf
->surf
->format
, true);
312 /* Align the rectangle primitive to 8x4 pixels.
314 * During fast depth clears, the emitted rectangle primitive must be
315 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
316 * 11.5.3.1 Depth Buffer Clear (and the matching section in the
319 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
320 * aligned to an 8x4 pixel block relative to the upper left corner
321 * of the depth buffer [...]
323 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
324 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
325 * Ivybridge simulator require the alignment.
327 * To be safe, let's just align the rect for all hiz operations and all
328 * hardware generations.
330 * However, for some miptree slices of a Z24 texture, emitting an 8x4
331 * aligned rectangle that covers the slice may clobber adjacent slices
332 * if we strictly adhered to the texture alignments specified in the
333 * PRM. The Ivybridge PRM, Section "Alignment Unit Size", states that
334 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24
335 * surfaces, not 8. But commit 1f112cc increased the alignment from 4 to
336 * 8, which prevents the clobbering.
338 params
.x1
= minify(params
.depth
.surf
.logical_level0_px
.width
,
339 params
.depth
.view
.base_level
);
340 params
.y1
= minify(params
.depth
.surf
.logical_level0_px
.height
,
341 params
.depth
.view
.base_level
);
342 params
.x1
= ALIGN(params
.x1
, 8);
343 params
.y1
= ALIGN(params
.y1
, 4);
345 if (params
.depth
.view
.base_level
== 0) {
346 /* TODO: What about MSAA? */
347 params
.depth
.surf
.logical_level0_px
.width
= params
.x1
;
348 params
.depth
.surf
.logical_level0_px
.height
= params
.y1
;
351 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
352 params
.dst
.surf
.logical_level0_px
= params
.depth
.surf
.logical_level0_px
;
353 params
.depth_format
=
354 isl_format_get_depth_format(surf
->surf
->format
, false);
355 params
.num_samples
= params
.depth
.surf
.samples
;
357 batch
->blorp
->exec(batch
, ¶ms
);