src/intel/blorp/blorp.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <errno.h>
  25
  26 #include "program/prog_instruction.h"
  27
  28 #include "blorp_priv.h"
  29 #include "compiler/brw_compiler.h"
  30 #include "compiler/brw_nir.h"
  31
  32 void
  33 blorp_init(struct blorp_context *blorp, void *driver_ctx,
  34            struct isl_device *isl_dev)
  35 {
  36    blorp->driver_ctx = driver_ctx;
  37    blorp->isl_dev = isl_dev;
  38 }
  39
  40 void
  41 blorp_finish(struct blorp_context *blorp)
  42 {
  43    blorp->driver_ctx = NULL;
  44 }
  45
  46 void
  47 blorp_batch_init(struct blorp_context *blorp,
  48                  struct blorp_batch *batch, void *driver_batch,
  49                  enum blorp_batch_flags flags)
  50 {
  51    batch->blorp = blorp;
  52    batch->driver_batch = driver_batch;
  53    batch->flags = flags;
  54 }
  55
  56 void
  57 blorp_batch_finish(struct blorp_batch *batch)
  58 {
  59    batch->blorp = NULL;
  60 }
  61
  62 void
  63 brw_blorp_surface_info_init(struct blorp_context *blorp,
  64                             struct brw_blorp_surface_info *info,
  65                             const struct blorp_surf *surf,
  66                             unsigned int level, unsigned int layer,
  67                             enum isl_format format, bool is_render_target)
  68 {
  69    info->enabled = true;
  70
  71    if (format == ISL_FORMAT_UNSUPPORTED)
  72       format = surf->surf->format;
  73
  74    if (format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
  75       /* Unfortunately, ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as
  76        * a render target, which would prevent us from blitting to 24-bit
  77        * depth.  The miptree consists of 32 bits per pixel, arranged as 24-bit
  78        * depth values interleaved with 8 "don't care" bits.  Since depth
  79        * values don't require any blending, it doesn't matter how we interpret
  80        * the bit pattern as long as we copy the right amount of data, so just
  81        * map it as 8-bit BGRA.
  82        */
  83       format = ISL_FORMAT_B8G8R8A8_UNORM;
  84    }
  85
  86    info->surf = *surf->surf;
  87    info->addr = surf->addr;
  88
  89    info->aux_usage = surf->aux_usage;
  90    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
  91       info->aux_surf = *surf->aux_surf;
  92       info->aux_addr = surf->aux_addr;
  93    }
  94
  95    info->clear_color = surf->clear_color;
  96
  97    info->view = (struct isl_view) {
  98       .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
  99                                   ISL_SURF_USAGE_TEXTURE_BIT,
 100       .format = format,
 101       .base_level = level,
 102       .levels = 1,
 103       .swizzle = ISL_SWIZZLE_IDENTITY,
 104    };
 105
 106    info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
 107                                info->surf.logical_level0_px.array_len);
 108
 109    if (!is_render_target &&
 110        (info->surf.dim == ISL_SURF_DIM_3D ||
 111         info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
 112       /* 3-D textures don't support base_array layer and neither do 2-D
 113        * multisampled textures on IVB so we need to pass it through the
 114        * sampler in those cases.  These are also two cases where we are
 115        * guaranteed that we won't be doing any funny surface hacks.
 116        */
 117       info->view.base_array_layer = 0;
 118       info->z_offset = layer;
 119    } else {
 120       info->view.base_array_layer = layer;
 121
 122       assert(info->view.array_len >= info->view.base_array_layer);
 123       info->view.array_len -= info->view.base_array_layer;
 124       info->z_offset = 0;
 125    }
 126
 127    /* Sandy Bridge and earlier have a limit of a maximum of 512 layers for
 128     * layered rendering.
 129     */
 130    if (is_render_target && blorp->isl_dev->info->gen <= 6)
 131       info->view.array_len = MIN2(info->view.array_len, 512);
 132 }
 133
 134
 135 void
 136 blorp_params_init(struct blorp_params *params)
 137 {
 138    memset(params, 0, sizeof(*params));
 139    params->num_samples = 1;
 140    params->num_draw_buffers = 1;
 141    params->num_layers = 1;
 142 }
 143
 144 void
 145 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key)
 146 {
 147    memset(wm_key, 0, sizeof(*wm_key));
 148    wm_key->nr_color_regions = 1;
 149    for (int i = 0; i < MAX_SAMPLERS; i++)
 150       wm_key->tex.swizzles[i] = SWIZZLE_XYZW;
 151 }
 152
 153 const unsigned *
 154 blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx,
 155                  struct nir_shader *nir,
 156                  struct brw_wm_prog_key *wm_key,
 157                  bool use_repclear,
 158                  struct brw_wm_prog_data *wm_prog_data,
 159                  unsigned *program_size)
 160 {
 161    const struct brw_compiler *compiler = blorp->compiler;
 162
 163    nir->options =
 164       compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
 165
 166    memset(wm_prog_data, 0, sizeof(*wm_prog_data));
 167
 168    assert(exec_list_is_empty(&nir->uniforms));
 169    wm_prog_data->base.nr_params = 0;
 170    wm_prog_data->base.param = NULL;
 171
 172    /* BLORP always just uses the first two binding table entries */
 173    wm_prog_data->binding_table.render_target_start = BLORP_RENDERBUFFER_BT_INDEX;
 174    wm_prog_data->base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
 175
 176    nir = brw_preprocess_nir(compiler, nir);
 177    nir_remove_dead_variables(nir, nir_var_shader_in);
 178    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 179
 180    if (blorp->compiler->devinfo->gen < 6) {
 181       if (nir->info.fs.uses_discard)
 182          wm_key->iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
 183
 184       wm_key->input_slots_valid = nir->info.inputs_read | VARYING_BIT_POS;
 185    }
 186
 187    const unsigned *program =
 188       brw_compile_fs(compiler, blorp->driver_ctx, mem_ctx, wm_key,
 189                      wm_prog_data, nir, NULL, -1, -1, false, use_repclear,
 190                      NULL, program_size, NULL);
 191
 192    return program;
 193 }
 194
 195 const unsigned *
 196 blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
 197                  struct nir_shader *nir,
 198                  struct brw_vs_prog_data *vs_prog_data,
 199                  unsigned *program_size)
 200 {
 201    const struct brw_compiler *compiler = blorp->compiler;
 202
 203    nir->options =
 204       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions;
 205
 206    nir = brw_preprocess_nir(compiler, nir);
 207    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 208
 209    vs_prog_data->inputs_read = nir->info.inputs_read;
 210
 211    brw_compute_vue_map(compiler->devinfo,
 212                        &vs_prog_data->base.vue_map,
 213                        nir->info.outputs_written,
 214                        nir->info.separate_shader);
 215
 216    struct brw_vs_prog_key vs_key = { 0, };
 217
 218    const unsigned *program =
 219       brw_compile_vs(compiler, blorp->driver_ctx, mem_ctx,
 220                      &vs_key, vs_prog_data, nir,
 221                      NULL, false, -1, program_size, NULL);
 222
 223    return program;
 224 }
 225
 226 struct blorp_sf_key {
 227    enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_GEN4_SF */
 228
 229    struct brw_sf_prog_key key;
 230 };
 231
 232 bool
 233 blorp_ensure_sf_program(struct blorp_context *blorp,
 234                         struct blorp_params *params)
 235 {
 236    const struct brw_wm_prog_data *wm_prog_data = params->wm_prog_data;
 237    assert(params->wm_prog_data);
 238
 239    /* Gen6+ doesn't need a strips and fans program */
 240    if (blorp->compiler->devinfo->gen >= 6)
 241       return true;
 242
 243    struct blorp_sf_key key = {
 244       .shader_type = BLORP_SHADER_TYPE_GEN4_SF,
 245    };
 246
 247    /* Everything gets compacted in vertex setup, so we just need a
 248     * pass-through for the correct number of input varyings.
 249     */
 250    const uint64_t slots_valid = VARYING_BIT_POS |
 251       ((1ull << wm_prog_data->num_varying_inputs) - 1) << VARYING_SLOT_VAR0;
 252
 253    key.key.attrs = slots_valid;
 254    key.key.primitive = BRW_SF_PRIM_TRIANGLES;
 255    key.key.contains_flat_varying = wm_prog_data->contains_flat_varying;
 256
 257    STATIC_ASSERT(sizeof(key.key.interp_mode) ==
 258                  sizeof(wm_prog_data->interp_mode));
 259    memcpy(key.key.interp_mode, wm_prog_data->interp_mode,
 260           sizeof(key.key.interp_mode));
 261
 262    if (blorp->lookup_shader(blorp, &key, sizeof(key),
 263                             &params->sf_prog_kernel, &params->sf_prog_data))
 264       return true;
 265
 266    void *mem_ctx = ralloc_context(NULL);
 267
 268    const unsigned *program;
 269    unsigned program_size;
 270
 271    struct brw_vue_map vue_map;
 272    brw_compute_vue_map(blorp->compiler->devinfo, &vue_map, slots_valid, false);
 273
 274    struct brw_sf_prog_data prog_data_tmp;
 275    program = brw_compile_sf(blorp->compiler, mem_ctx, &key.key,
 276                             &prog_data_tmp, &vue_map, &program_size);
 277
 278    bool result =
 279       blorp->upload_shader(blorp, &key, sizeof(key), program, program_size,
 280                            (void *)&prog_data_tmp, sizeof(prog_data_tmp),
 281                            &params->sf_prog_kernel, &params->sf_prog_data);
 282
 283    ralloc_free(mem_ctx);
 284
 285    return result;
 286 }
 287
 288 void
 289 blorp_gen6_hiz_op(struct blorp_batch *batch,
 290                   struct blorp_surf *surf, unsigned level, unsigned layer,
 291                   enum blorp_hiz_op op)
 292 {
 293    struct blorp_params params;
 294    blorp_params_init(&params);
 295
 296    params.hiz_op = op;
 297
 298    brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level, layer,
 299                                surf->surf->format, true);
 300
 301    /* Align the rectangle primitive to 8x4 pixels.
 302     *
 303     * During fast depth clears, the emitted rectangle primitive  must be
 304     * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
 305     * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
 306     * PRM):
 307     *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
 308     *     aligned to an 8x4 pixel block relative to the upper left corner
 309     *     of the depth buffer [...]
 310     *
 311     * For hiz resolves, the rectangle must also be 8x4 aligned. Item
 312     * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
 313     * Ivybridge simulator require the alignment.
 314     *
 315     * To be safe, let's just align the rect for all hiz operations and all
 316     * hardware generations.
 317     *
 318     * However, for some miptree slices of a Z24 texture, emitting an 8x4
 319     * aligned rectangle that covers the slice may clobber adjacent slices if
 320     * we strictly adhered to the texture alignments specified in the PRM.  The
 321     * Ivybridge PRM, Section "Alignment Unit Size", states that
 322     * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
 323     * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
 324     * prevents the clobbering.
 325     */
 326    params.x1 = minify(params.depth.surf.logical_level0_px.width,
 327                       params.depth.view.base_level);
 328    params.y1 = minify(params.depth.surf.logical_level0_px.height,
 329                       params.depth.view.base_level);
 330    params.x1 = ALIGN(params.x1, 8);
 331    params.y1 = ALIGN(params.y1, 4);
 332
 333    if (params.depth.view.base_level == 0) {
 334       /* TODO: What about MSAA? */
 335       params.depth.surf.logical_level0_px.width = params.x1;
 336       params.depth.surf.logical_level0_px.height = params.y1;
 337    }
 338
 339    params.dst.surf.samples = params.depth.surf.samples;
 340    params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
 341    params.depth_format = isl_format_get_depth_format(surf->surf->format, false);
 342    params.num_samples = params.depth.surf.samples;
 343
 344    batch->blorp->exec(batch, &params);
 345 }