src/intel/blorp/blorp.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <errno.h>
  25
  26 #include "program/prog_instruction.h"
  27
  28 #include "blorp_priv.h"
  29 #include "compiler/brw_compiler.h"
  30 #include "compiler/brw_nir.h"
  31
  32 void
  33 blorp_init(struct blorp_context *blorp, void *driver_ctx,
  34            struct isl_device *isl_dev)
  35 {
  36    blorp->driver_ctx = driver_ctx;
  37    blorp->isl_dev = isl_dev;
  38 }
  39
  40 void
  41 blorp_finish(struct blorp_context *blorp)
  42 {
  43    blorp->driver_ctx = NULL;
  44 }
  45
  46 void
  47 blorp_batch_init(struct blorp_context *blorp,
  48                  struct blorp_batch *batch, void *driver_batch,
  49                  enum blorp_batch_flags flags)
  50 {
  51    batch->blorp = blorp;
  52    batch->driver_batch = driver_batch;
  53    batch->flags = flags;
  54 }
  55
  56 void
  57 blorp_batch_finish(struct blorp_batch *batch)
  58 {
  59    batch->blorp = NULL;
  60 }
  61
  62 void
  63 brw_blorp_surface_info_init(struct blorp_context *blorp,
  64                             struct brw_blorp_surface_info *info,
  65                             const struct blorp_surf *surf,
  66                             unsigned int level, unsigned int layer,
  67                             enum isl_format format, bool is_render_target)
  68 {
  69    assert(level < surf->surf->levels);
  70    assert(layer < MAX2(surf->surf->logical_level0_px.depth >> level,
  71                        surf->surf->logical_level0_px.array_len));
  72
  73    info->enabled = true;
  74
  75    if (format == ISL_FORMAT_UNSUPPORTED)
  76       format = surf->surf->format;
  77
  78    if (format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
  79       /* Unfortunately, ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as
  80        * a render target, which would prevent us from blitting to 24-bit
  81        * depth.  The miptree consists of 32 bits per pixel, arranged as 24-bit
  82        * depth values interleaved with 8 "don't care" bits.  Since depth
  83        * values don't require any blending, it doesn't matter how we interpret
  84        * the bit pattern as long as we copy the right amount of data, so just
  85        * map it as 8-bit BGRA.
  86        */
  87       format = ISL_FORMAT_B8G8R8A8_UNORM;
  88    }
  89
  90    info->surf = *surf->surf;
  91    info->addr = surf->addr;
  92
  93    info->aux_usage = surf->aux_usage;
  94    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
  95       info->aux_surf = *surf->aux_surf;
  96       info->aux_addr = surf->aux_addr;
  97       assert(level < info->aux_surf.levels);
  98       assert(layer < MAX2(info->aux_surf.logical_level0_px.depth >> level,
  99                           info->aux_surf.logical_level0_px.array_len));
 100    }
 101
 102    info->clear_color = surf->clear_color;
 103    info->clear_color_addr = surf->clear_color_addr;
 104
 105    info->view = (struct isl_view) {
 106       .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
 107                                   ISL_SURF_USAGE_TEXTURE_BIT,
 108       .format = format,
 109       .base_level = level,
 110       .levels = 1,
 111       .swizzle = ISL_SWIZZLE_IDENTITY,
 112    };
 113
 114    info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
 115                                info->surf.logical_level0_px.array_len);
 116
 117    if (!is_render_target &&
 118        (info->surf.dim == ISL_SURF_DIM_3D ||
 119         info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
 120       /* 3-D textures don't support base_array layer and neither do 2-D
 121        * multisampled textures on IVB so we need to pass it through the
 122        * sampler in those cases.  These are also two cases where we are
 123        * guaranteed that we won't be doing any funny surface hacks.
 124        */
 125       info->view.base_array_layer = 0;
 126       info->z_offset = layer;
 127    } else {
 128       info->view.base_array_layer = layer;
 129
 130       assert(info->view.array_len >= info->view.base_array_layer);
 131       info->view.array_len -= info->view.base_array_layer;
 132       info->z_offset = 0;
 133    }
 134
 135    /* Sandy Bridge and earlier have a limit of a maximum of 512 layers for
 136     * layered rendering.
 137     */
 138    if (is_render_target && blorp->isl_dev->info->gen <= 6)
 139       info->view.array_len = MIN2(info->view.array_len, 512);
 140 }
 141
 142
 143 void
 144 blorp_params_init(struct blorp_params *params)
 145 {
 146    memset(params, 0, sizeof(*params));
 147    params->num_samples = 1;
 148    params->num_draw_buffers = 1;
 149    params->num_layers = 1;
 150 }
 151
 152 void
 153 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key)
 154 {
 155    memset(wm_key, 0, sizeof(*wm_key));
 156    wm_key->nr_color_regions = 1;
 157    for (int i = 0; i < MAX_SAMPLERS; i++)
 158       wm_key->tex.swizzles[i] = SWIZZLE_XYZW;
 159 }
 160
 161 const unsigned *
 162 blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx,
 163                  struct nir_shader *nir,
 164                  struct brw_wm_prog_key *wm_key,
 165                  bool use_repclear,
 166                  struct brw_wm_prog_data *wm_prog_data)
 167 {
 168    const struct brw_compiler *compiler = blorp->compiler;
 169
 170    nir->options =
 171       compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
 172
 173    memset(wm_prog_data, 0, sizeof(*wm_prog_data));
 174
 175    assert(exec_list_is_empty(&nir->uniforms));
 176    wm_prog_data->base.nr_params = 0;
 177    wm_prog_data->base.param = NULL;
 178
 179    /* BLORP always just uses the first two binding table entries */
 180    wm_prog_data->binding_table.render_target_start = BLORP_RENDERBUFFER_BT_INDEX;
 181    wm_prog_data->base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
 182
 183    nir = brw_preprocess_nir(compiler, nir);
 184    nir_remove_dead_variables(nir, nir_var_shader_in);
 185    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 186
 187    if (blorp->compiler->devinfo->gen < 6) {
 188       if (nir->info.fs.uses_discard)
 189          wm_key->iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
 190
 191       wm_key->input_slots_valid = nir->info.inputs_read | VARYING_BIT_POS;
 192    }
 193
 194    const unsigned *program =
 195       brw_compile_fs(compiler, blorp->driver_ctx, mem_ctx, wm_key,
 196                      wm_prog_data, nir, NULL, -1, -1, false, use_repclear,
 197                      NULL, NULL);
 198
 199    return program;
 200 }
 201
 202 const unsigned *
 203 blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
 204                  struct nir_shader *nir,
 205                  struct brw_vs_prog_data *vs_prog_data)
 206 {
 207    const struct brw_compiler *compiler = blorp->compiler;
 208
 209    nir->options =
 210       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions;
 211
 212    nir = brw_preprocess_nir(compiler, nir);
 213    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 214
 215    vs_prog_data->inputs_read = nir->info.inputs_read;
 216
 217    brw_compute_vue_map(compiler->devinfo,
 218                        &vs_prog_data->base.vue_map,
 219                        nir->info.outputs_written,
 220                        nir->info.separate_shader);
 221
 222    struct brw_vs_prog_key vs_key = { 0, };
 223
 224    const unsigned *program =
 225       brw_compile_vs(compiler, blorp->driver_ctx, mem_ctx,
 226                      &vs_key, vs_prog_data, nir, -1, NULL);
 227
 228    return program;
 229 }
 230
 231 struct blorp_sf_key {
 232    enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_GEN4_SF */
 233
 234    struct brw_sf_prog_key key;
 235 };
 236
 237 bool
 238 blorp_ensure_sf_program(struct blorp_context *blorp,
 239                         struct blorp_params *params)
 240 {
 241    const struct brw_wm_prog_data *wm_prog_data = params->wm_prog_data;
 242    assert(params->wm_prog_data);
 243
 244    /* Gen6+ doesn't need a strips and fans program */
 245    if (blorp->compiler->devinfo->gen >= 6)
 246       return true;
 247
 248    struct blorp_sf_key key = {
 249       .shader_type = BLORP_SHADER_TYPE_GEN4_SF,
 250    };
 251
 252    /* Everything gets compacted in vertex setup, so we just need a
 253     * pass-through for the correct number of input varyings.
 254     */
 255    const uint64_t slots_valid = VARYING_BIT_POS |
 256       ((1ull << wm_prog_data->num_varying_inputs) - 1) << VARYING_SLOT_VAR0;
 257
 258    key.key.attrs = slots_valid;
 259    key.key.primitive = BRW_SF_PRIM_TRIANGLES;
 260    key.key.contains_flat_varying = wm_prog_data->contains_flat_varying;
 261
 262    STATIC_ASSERT(sizeof(key.key.interp_mode) ==
 263                  sizeof(wm_prog_data->interp_mode));
 264    memcpy(key.key.interp_mode, wm_prog_data->interp_mode,
 265           sizeof(key.key.interp_mode));
 266
 267    if (blorp->lookup_shader(blorp, &key, sizeof(key),
 268                             &params->sf_prog_kernel, &params->sf_prog_data))
 269       return true;
 270
 271    void *mem_ctx = ralloc_context(NULL);
 272
 273    const unsigned *program;
 274    unsigned program_size;
 275
 276    struct brw_vue_map vue_map;
 277    brw_compute_vue_map(blorp->compiler->devinfo, &vue_map, slots_valid, false);
 278
 279    struct brw_sf_prog_data prog_data_tmp;
 280    program = brw_compile_sf(blorp->compiler, mem_ctx, &key.key,
 281                             &prog_data_tmp, &vue_map, &program_size);
 282
 283    bool result =
 284       blorp->upload_shader(blorp, &key, sizeof(key), program, program_size,
 285                            (void *)&prog_data_tmp, sizeof(prog_data_tmp),
 286                            &params->sf_prog_kernel, &params->sf_prog_data);
 287
 288    ralloc_free(mem_ctx);
 289
 290    return result;
 291 }
 292
 293 void
 294 blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
 295              uint32_t level, uint32_t start_layer, uint32_t num_layers,
 296              enum blorp_hiz_op op)
 297 {
 298    struct blorp_params params;
 299    blorp_params_init(&params);
 300
 301    params.hiz_op = op;
 302    params.full_surface_hiz_op = true;
 303
 304    for (uint32_t a = 0; a < num_layers; a++) {
 305       const uint32_t layer = start_layer + a;
 306
 307       brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level,
 308                                   layer, surf->surf->format, true);
 309
 310       /* Align the rectangle primitive to 8x4 pixels.
 311        *
 312        * During fast depth clears, the emitted rectangle primitive  must be
 313        * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
 314        * 11.5.3.1 Depth Buffer Clear (and the matching section in the
 315        * Sandybridge PRM):
 316        *
 317        *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
 318        *     aligned to an 8x4 pixel block relative to the upper left corner
 319        *     of the depth buffer [...]
 320        *
 321        * For hiz resolves, the rectangle must also be 8x4 aligned. Item
 322        * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
 323        * Ivybridge simulator require the alignment.
 324        *
 325        * To be safe, let's just align the rect for all hiz operations and all
 326        * hardware generations.
 327        *
 328        * However, for some miptree slices of a Z24 texture, emitting an 8x4
 329        * aligned rectangle that covers the slice may clobber adjacent slices
 330        * if we strictly adhered to the texture alignments specified in the
 331        * PRM.  The Ivybridge PRM, Section "Alignment Unit Size", states that
 332        * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24
 333        * surfaces, not 8. But commit 1f112cc increased the alignment from 4 to
 334        * 8, which prevents the clobbering.
 335        */
 336       params.x1 = minify(params.depth.surf.logical_level0_px.width,
 337                          params.depth.view.base_level);
 338       params.y1 = minify(params.depth.surf.logical_level0_px.height,
 339                          params.depth.view.base_level);
 340       params.x1 = ALIGN(params.x1, 8);
 341       params.y1 = ALIGN(params.y1, 4);
 342
 343       if (params.depth.view.base_level == 0) {
 344          /* TODO: What about MSAA? */
 345          params.depth.surf.logical_level0_px.width = params.x1;
 346          params.depth.surf.logical_level0_px.height = params.y1;
 347       }
 348
 349       params.dst.surf.samples = params.depth.surf.samples;
 350       params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
 351       params.depth_format =
 352          isl_format_get_depth_format(surf->surf->format, false);
 353       params.num_samples = params.depth.surf.samples;
 354
 355       batch->blorp->exec(batch, &params);
 356    }
 357 }