src/intel/blorp/blorp.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <errno.h>
  25
  26 #include "program/prog_instruction.h"
  27
  28 #include "blorp_priv.h"
  29 #include "compiler/brw_compiler.h"
  30 #include "compiler/brw_nir.h"
  31
  32 void
  33 blorp_init(struct blorp_context *blorp, void *driver_ctx,
  34            struct isl_device *isl_dev)
  35 {
  36    blorp->driver_ctx = driver_ctx;
  37    blorp->isl_dev = isl_dev;
  38 }
  39
  40 void
  41 blorp_finish(struct blorp_context *blorp)
  42 {
  43    blorp->driver_ctx = NULL;
  44 }
  45
  46 void
  47 blorp_batch_init(struct blorp_context *blorp,
  48                  struct blorp_batch *batch, void *driver_batch,
  49                  enum blorp_batch_flags flags)
  50 {
  51    batch->blorp = blorp;
  52    batch->driver_batch = driver_batch;
  53    batch->flags = flags;
  54 }
  55
  56 void
  57 blorp_batch_finish(struct blorp_batch *batch)
  58 {
  59    batch->blorp = NULL;
  60 }
  61
  62 void
  63 brw_blorp_surface_info_init(struct blorp_context *blorp,
  64                             struct brw_blorp_surface_info *info,
  65                             const struct blorp_surf *surf,
  66                             unsigned int level, unsigned int layer,
  67                             enum isl_format format, bool is_render_target)
  68 {
  69    memset(info, 0, sizeof(*info));
  70    assert(level < surf->surf->levels);
  71    assert(layer < MAX2(surf->surf->logical_level0_px.depth >> level,
  72                        surf->surf->logical_level0_px.array_len));
  73
  74    info->enabled = true;
  75
  76    if (format == ISL_FORMAT_UNSUPPORTED)
  77       format = surf->surf->format;
  78
  79    info->surf = *surf->surf;
  80    info->addr = surf->addr;
  81
  82    info->aux_usage = surf->aux_usage;
  83    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
  84       info->aux_surf = *surf->aux_surf;
  85       info->aux_addr = surf->aux_addr;
  86       assert(level < info->aux_surf.levels);
  87       assert(layer < MAX2(info->aux_surf.logical_level0_px.depth >> level,
  88                           info->aux_surf.logical_level0_px.array_len));
  89    }
  90
  91    info->clear_color = surf->clear_color;
  92    info->clear_color_addr = surf->clear_color_addr;
  93
  94    info->view = (struct isl_view) {
  95       .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
  96                                   ISL_SURF_USAGE_TEXTURE_BIT,
  97       .format = format,
  98       .base_level = level,
  99       .levels = 1,
 100       .swizzle = ISL_SWIZZLE_IDENTITY,
 101    };
 102
 103    info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
 104                                info->surf.logical_level0_px.array_len);
 105
 106    if (!is_render_target &&
 107        (info->surf.dim == ISL_SURF_DIM_3D ||
 108         info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
 109       /* 3-D textures don't support base_array layer and neither do 2-D
 110        * multisampled textures on IVB so we need to pass it through the
 111        * sampler in those cases.  These are also two cases where we are
 112        * guaranteed that we won't be doing any funny surface hacks.
 113        */
 114       info->view.base_array_layer = 0;
 115       info->z_offset = layer;
 116    } else {
 117       info->view.base_array_layer = layer;
 118
 119       assert(info->view.array_len >= info->view.base_array_layer);
 120       info->view.array_len -= info->view.base_array_layer;
 121       info->z_offset = 0;
 122    }
 123
 124    /* Sandy Bridge and earlier have a limit of a maximum of 512 layers for
 125     * layered rendering.
 126     */
 127    if (is_render_target && blorp->isl_dev->info->gen <= 6)
 128       info->view.array_len = MIN2(info->view.array_len, 512);
 129
 130    if (surf->tile_x_sa || surf->tile_y_sa) {
 131       /* This is only allowed on simple 2D surfaces without MSAA */
 132       assert(info->surf.dim == ISL_SURF_DIM_2D);
 133       assert(info->surf.samples == 1);
 134       assert(info->surf.levels == 1);
 135       assert(info->surf.logical_level0_px.array_len == 1);
 136       assert(info->aux_usage == ISL_AUX_USAGE_NONE);
 137
 138       info->tile_x_sa = surf->tile_x_sa;
 139       info->tile_y_sa = surf->tile_y_sa;
 140
 141       /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we
 142        * place the image at the tile boundary and offset our sampling or
 143        * rendering.  For this reason, we need to grow the image by the offset
 144        * to ensure that the hardware doesn't think we've gone past the edge.
 145        */
 146       info->surf.logical_level0_px.w += surf->tile_x_sa;
 147       info->surf.logical_level0_px.h += surf->tile_y_sa;
 148       info->surf.phys_level0_sa.w += surf->tile_x_sa;
 149       info->surf.phys_level0_sa.h += surf->tile_y_sa;
 150    }
 151 }
 152
 153
 154 void
 155 blorp_params_init(struct blorp_params *params)
 156 {
 157    memset(params, 0, sizeof(*params));
 158    params->num_samples = 1;
 159    params->num_draw_buffers = 1;
 160    params->num_layers = 1;
 161 }
 162
 163 void
 164 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key)
 165 {
 166    memset(wm_key, 0, sizeof(*wm_key));
 167    wm_key->nr_color_regions = 1;
 168    for (int i = 0; i < MAX_SAMPLERS; i++)
 169       wm_key->base.tex.swizzles[i] = SWIZZLE_XYZW;
 170 }
 171
 172 const unsigned *
 173 blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx,
 174                  struct nir_shader *nir,
 175                  struct brw_wm_prog_key *wm_key,
 176                  bool use_repclear,
 177                  struct brw_wm_prog_data *wm_prog_data)
 178 {
 179    const struct brw_compiler *compiler = blorp->compiler;
 180
 181    nir->options =
 182       compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
 183
 184    memset(wm_prog_data, 0, sizeof(*wm_prog_data));
 185
 186    assert(exec_list_is_empty(&nir->uniforms));
 187    wm_prog_data->base.nr_params = 0;
 188    wm_prog_data->base.param = NULL;
 189
 190    /* BLORP always uses the first two binding table entries:
 191     * - Surface 0 is the render target (which always start from 0)
 192     * - Surface 1 is the source texture
 193     */
 194    wm_prog_data->base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
 195
 196    brw_preprocess_nir(compiler, nir, NULL);
 197    nir_remove_dead_variables(nir, nir_var_shader_in);
 198    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 199
 200    if (blorp->compiler->devinfo->gen < 6) {
 201       if (nir->info.fs.uses_discard)
 202          wm_key->iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
 203
 204       wm_key->input_slots_valid = nir->info.inputs_read | VARYING_BIT_POS;
 205    }
 206
 207    const unsigned *program =
 208       brw_compile_fs(compiler, blorp->driver_ctx, mem_ctx, wm_key,
 209                      wm_prog_data, nir, -1, -1, -1, false, use_repclear,
 210                      NULL, NULL, NULL);
 211
 212    return program;
 213 }
 214
 215 const unsigned *
 216 blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
 217                  struct nir_shader *nir,
 218                  struct brw_vs_prog_data *vs_prog_data)
 219 {
 220    const struct brw_compiler *compiler = blorp->compiler;
 221
 222    nir->options =
 223       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions;
 224
 225    brw_preprocess_nir(compiler, nir, NULL);
 226    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 227
 228    vs_prog_data->inputs_read = nir->info.inputs_read;
 229
 230    brw_compute_vue_map(compiler->devinfo,
 231                        &vs_prog_data->base.vue_map,
 232                        nir->info.outputs_written,
 233                        nir->info.separate_shader);
 234
 235    struct brw_vs_prog_key vs_key = { 0, };
 236
 237    const unsigned *program =
 238       brw_compile_vs(compiler, blorp->driver_ctx, mem_ctx,
 239                      &vs_key, vs_prog_data, nir, -1, NULL, NULL);
 240
 241    return program;
 242 }
 243
 244 struct blorp_sf_key {
 245    enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_GEN4_SF */
 246
 247    struct brw_sf_prog_key key;
 248 };
 249
 250 bool
 251 blorp_ensure_sf_program(struct blorp_batch *batch,
 252                         struct blorp_params *params)
 253 {
 254    struct blorp_context *blorp = batch->blorp;
 255    const struct brw_wm_prog_data *wm_prog_data = params->wm_prog_data;
 256    assert(params->wm_prog_data);
 257
 258    /* Gen6+ doesn't need a strips and fans program */
 259    if (blorp->compiler->devinfo->gen >= 6)
 260       return true;
 261
 262    struct blorp_sf_key key = {
 263       .shader_type = BLORP_SHADER_TYPE_GEN4_SF,
 264    };
 265
 266    /* Everything gets compacted in vertex setup, so we just need a
 267     * pass-through for the correct number of input varyings.
 268     */
 269    const uint64_t slots_valid = VARYING_BIT_POS |
 270       ((1ull << wm_prog_data->num_varying_inputs) - 1) << VARYING_SLOT_VAR0;
 271
 272    key.key.attrs = slots_valid;
 273    key.key.primitive = BRW_SF_PRIM_TRIANGLES;
 274    key.key.contains_flat_varying = wm_prog_data->contains_flat_varying;
 275
 276    STATIC_ASSERT(sizeof(key.key.interp_mode) ==
 277                  sizeof(wm_prog_data->interp_mode));
 278    memcpy(key.key.interp_mode, wm_prog_data->interp_mode,
 279           sizeof(key.key.interp_mode));
 280
 281    if (blorp->lookup_shader(batch, &key, sizeof(key),
 282                             &params->sf_prog_kernel, &params->sf_prog_data))
 283       return true;
 284
 285    void *mem_ctx = ralloc_context(NULL);
 286
 287    const unsigned *program;
 288    unsigned program_size;
 289
 290    struct brw_vue_map vue_map;
 291    brw_compute_vue_map(blorp->compiler->devinfo, &vue_map, slots_valid, false);
 292
 293    struct brw_sf_prog_data prog_data_tmp;
 294    program = brw_compile_sf(blorp->compiler, mem_ctx, &key.key,
 295                             &prog_data_tmp, &vue_map, &program_size);
 296
 297    bool result =
 298       blorp->upload_shader(batch, &key, sizeof(key), program, program_size,
 299                            (void *)&prog_data_tmp, sizeof(prog_data_tmp),
 300                            &params->sf_prog_kernel, &params->sf_prog_data);
 301
 302    ralloc_free(mem_ctx);
 303
 304    return result;
 305 }
 306
 307 void
 308 blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
 309              uint32_t level, uint32_t start_layer, uint32_t num_layers,
 310              enum isl_aux_op op)
 311 {
 312    struct blorp_params params;
 313    blorp_params_init(&params);
 314
 315    params.hiz_op = op;
 316    params.full_surface_hiz_op = true;
 317
 318    for (uint32_t a = 0; a < num_layers; a++) {
 319       const uint32_t layer = start_layer + a;
 320
 321       brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level,
 322                                   layer, surf->surf->format, true);
 323
 324       /* Align the rectangle primitive to 8x4 pixels.
 325        *
 326        * During fast depth clears, the emitted rectangle primitive  must be
 327        * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
 328        * 11.5.3.1 Depth Buffer Clear (and the matching section in the
 329        * Sandybridge PRM):
 330        *
 331        *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
 332        *     aligned to an 8x4 pixel block relative to the upper left corner
 333        *     of the depth buffer [...]
 334        *
 335        * For hiz resolves, the rectangle must also be 8x4 aligned. Item
 336        * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
 337        * Ivybridge simulator require the alignment.
 338        *
 339        * To be safe, let's just align the rect for all hiz operations and all
 340        * hardware generations.
 341        *
 342        * However, for some miptree slices of a Z24 texture, emitting an 8x4
 343        * aligned rectangle that covers the slice may clobber adjacent slices
 344        * if we strictly adhered to the texture alignments specified in the
 345        * PRM.  The Ivybridge PRM, Section "Alignment Unit Size", states that
 346        * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24
 347        * surfaces, not 8. But commit 1f112cc increased the alignment from 4 to
 348        * 8, which prevents the clobbering.
 349        */
 350       params.x1 = minify(params.depth.surf.logical_level0_px.width,
 351                          params.depth.view.base_level);
 352       params.y1 = minify(params.depth.surf.logical_level0_px.height,
 353                          params.depth.view.base_level);
 354       params.x1 = ALIGN(params.x1, 8);
 355       params.y1 = ALIGN(params.y1, 4);
 356
 357       if (params.depth.view.base_level == 0) {
 358          /* TODO: What about MSAA? */
 359          params.depth.surf.logical_level0_px.width = params.x1;
 360          params.depth.surf.logical_level0_px.height = params.y1;
 361       }
 362
 363       params.dst.surf.samples = params.depth.surf.samples;
 364       params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
 365       params.depth_format =
 366          isl_format_get_depth_format(surf->surf->format, false);
 367       params.num_samples = params.depth.surf.samples;
 368
 369       batch->blorp->exec(batch, &params);
 370    }
 371 }