2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "blorp_nir_builder.h"
25 #include "compiler/nir/nir_format_convert.h"
27 #include "blorp_priv.h"
29 #include "util/format_rgb9e5.h"
30 /* header-only include needed for _mesa_unorm_to_float and friends. */
31 #include "mesa/main/format_utils.h"
33 #define FILE_DEBUG_FLAG DEBUG_BLORP
35 static const bool split_blorp_blit_debug
= false;
38 * Enum to specify the order of arguments in a sampler message
40 enum sampler_message_arg
42 SAMPLER_MESSAGE_ARG_U_FLOAT
,
43 SAMPLER_MESSAGE_ARG_V_FLOAT
,
44 SAMPLER_MESSAGE_ARG_U_INT
,
45 SAMPLER_MESSAGE_ARG_V_INT
,
46 SAMPLER_MESSAGE_ARG_R_INT
,
47 SAMPLER_MESSAGE_ARG_SI_INT
,
48 SAMPLER_MESSAGE_ARG_MCS_INT
,
49 SAMPLER_MESSAGE_ARG_ZERO_INT
,
52 struct brw_blorp_blit_vars
{
53 /* Input values from brw_blorp_wm_inputs */
54 nir_variable
*v_discard_rect
;
55 nir_variable
*v_rect_grid
;
56 nir_variable
*v_coord_transform
;
57 nir_variable
*v_src_z
;
58 nir_variable
*v_src_offset
;
59 nir_variable
*v_dst_offset
;
60 nir_variable
*v_src_inv_size
;
63 nir_variable
*frag_coord
;
66 nir_variable
*color_out
;
70 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
71 const struct brw_blorp_blit_prog_key
*key
)
73 /* Blended and scaled blits never use pixel discard. */
74 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
76 #define LOAD_INPUT(name, type)\
77 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
79 LOAD_INPUT(discard_rect
, glsl_vec4_type())
80 LOAD_INPUT(rect_grid
, glsl_vec4_type())
81 LOAD_INPUT(coord_transform
, glsl_vec4_type())
82 LOAD_INPUT(src_z
, glsl_uint_type())
83 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
84 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
85 LOAD_INPUT(src_inv_size
, glsl_vector_type(GLSL_TYPE_FLOAT
, 2))
89 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
90 glsl_vec4_type(), "gl_FragCoord");
91 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
92 v
->frag_coord
->data
.origin_upper_left
= true;
94 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
95 glsl_vec4_type(), "gl_FragColor");
96 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
100 blorp_blit_get_frag_coords(nir_builder
*b
,
101 const struct brw_blorp_blit_prog_key
*key
,
102 struct brw_blorp_blit_vars
*v
)
104 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_var(b
, v
->frag_coord
));
106 /* Account for destination surface intratile offset
108 * Transformation parameters giving translation from destination to source
109 * coordinates don't take into account possible intra-tile destination
110 * offset. Therefore it has to be first subtracted from the incoming
111 * coordinates. Vertices are set up based on coordinates containing the
114 if (key
->need_dst_offset
)
115 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
117 if (key
->persample_msaa_dispatch
) {
118 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
119 nir_load_sample_id(b
));
121 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
126 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
130 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
131 struct brw_blorp_blit_vars
*v
)
133 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
135 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
136 nir_channel(b
, coord_transform
, 3));
137 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
138 nir_channel(b
, coord_transform
, 2));
140 return nir_fadd(b
, nir_fmul(b
, src_pos
, mul
), offset
);
144 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
145 struct brw_blorp_blit_vars
*v
)
147 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
148 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
149 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
150 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
151 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
152 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
154 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
155 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
156 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
157 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
159 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
161 nir_intrinsic_instr
*discard
=
162 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
163 discard
->src
[0] = nir_src_for_ssa(oob
);
164 nir_builder_instr_insert(b
, &discard
->instr
);
167 static nir_tex_instr
*
168 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
169 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
170 nir_alu_type dst_type
)
172 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
176 tex
->dest_type
= dst_type
;
177 tex
->is_array
= false;
178 tex
->is_shadow
= false;
180 /* Blorp only has one texture and it's bound at unit 0 */
183 tex
->texture_index
= 0;
184 tex
->sampler_index
= 0;
186 /* To properly handle 3-D and 2-D array textures, we pull the Z component
187 * from an input. TODO: This is a bit magic; we should probably make this
188 * more explicit in the future.
190 assert(pos
->num_components
>= 2);
191 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
192 nir_load_var(b
, v
->v_src_z
));
194 tex
->src
[0].src_type
= nir_tex_src_coord
;
195 tex
->src
[0].src
= nir_src_for_ssa(pos
);
196 tex
->coord_components
= 3;
198 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
204 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
205 const struct brw_blorp_blit_prog_key
*key
, nir_ssa_def
*pos
)
207 if (key
->need_src_offset
)
208 pos
= nir_fadd(b
, pos
, nir_i2f32(b
, nir_load_var(b
, v
->v_src_offset
)));
210 /* If the sampler requires normalized coordinates, we need to compensate. */
211 if (key
->src_coords_normalized
)
212 pos
= nir_fmul(b
, pos
, nir_load_var(b
, v
->v_src_inv_size
));
215 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2,
216 key
->texture_data_type
);
218 assert(pos
->num_components
== 2);
219 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
220 tex
->src
[1].src_type
= nir_tex_src_lod
;
221 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
223 nir_builder_instr_insert(b
, &tex
->instr
);
225 return &tex
->dest
.ssa
;
229 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
230 nir_ssa_def
*pos
, nir_alu_type dst_type
)
233 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
235 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
236 tex
->src
[1].src_type
= nir_tex_src_lod
;
237 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
239 nir_builder_instr_insert(b
, &tex
->instr
);
241 return &tex
->dest
.ssa
;
245 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
246 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
249 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
250 mcs
!= NULL
? 3 : 2, dst_type
);
252 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
254 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
255 if (pos
->num_components
== 2) {
256 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
258 assert(pos
->num_components
== 3);
259 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
263 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
264 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
267 nir_builder_instr_insert(b
, &tex
->instr
);
269 return &tex
->dest
.ssa
;
273 blorp_blit_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
277 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
278 pos
, 1, nir_type_int
);
280 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
282 nir_builder_instr_insert(b
, &tex
->instr
);
284 return &tex
->dest
.ssa
;
288 * Emit code to compensate for the difference between Y and W tiling.
290 * This code modifies the X and Y coordinates according to the formula:
292 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
294 * (See brw_blorp_build_nir_shader).
296 static inline nir_ssa_def
*
297 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
299 assert(pos
->num_components
== 2);
300 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
301 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
303 /* Given X and Y coordinates that describe an address using Y tiling,
304 * translate to the X and Y coordinates that describe the same address
307 * If we break down the low order bits of X and Y, using a
308 * single letter to represent each low-order bit:
310 * X = A << 7 | 0bBCDEFGH
311 * Y = J << 5 | 0bKLMNP (1)
313 * Then we can apply the Y tiling formula to see the memory offset being
316 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
318 * If we apply the W detiling formula to this memory location, that the
319 * corresponding X' and Y' coordinates are:
321 * X' = A << 6 | 0bBCDPFH (3)
322 * Y' = J << 6 | 0bKLMNEG
324 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
325 * we need to make the following computation:
327 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
328 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
330 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
331 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
332 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
333 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
335 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
336 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
337 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
338 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
340 return nir_vec2(b
, x_W
, y_W
);
344 * Emit code to compensate for the difference between Y and W tiling.
346 * This code modifies the X and Y coordinates according to the formula:
348 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
350 * (See brw_blorp_build_nir_shader).
352 static inline nir_ssa_def
*
353 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
355 assert(pos
->num_components
== 2);
356 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
357 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
359 /* Applying the same logic as above, but in reverse, we obtain the
362 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
363 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
365 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
366 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
367 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
368 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
369 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
371 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
372 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
373 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
375 return nir_vec2(b
, x_Y
, y_Y
);
379 * Emit code to compensate for the difference between MSAA and non-MSAA
382 * This code modifies the X and Y coordinates according to the formula:
384 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
386 * (See brw_blorp_blit_program).
388 static inline nir_ssa_def
*
389 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
390 unsigned num_samples
, enum isl_msaa_layout layout
)
392 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
395 case ISL_MSAA_LAYOUT_NONE
:
396 assert(pos
->num_components
== 2);
398 case ISL_MSAA_LAYOUT_ARRAY
:
399 /* No translation needed */
401 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
402 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
403 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
404 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
405 nir_channel(b
, pos
, 2);
407 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
408 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
409 switch (num_samples
) {
412 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
413 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
416 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
417 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
418 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
420 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
421 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
422 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
423 if (num_samples
== 2) {
426 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
427 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
428 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
433 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
434 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
436 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
438 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
439 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
440 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
441 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
442 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
443 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
444 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
448 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
449 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
451 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
454 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
455 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
456 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
457 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
458 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
459 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
460 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
461 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
465 unreachable("Invalid number of samples for IMS layout");
468 return nir_vec2(b
, x_out
, y_out
);
472 unreachable("Invalid MSAA layout");
477 * Emit code to compensate for the difference between MSAA and non-MSAA
480 * This code modifies the X and Y coordinates according to the formula:
482 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
484 * (See brw_blorp_blit_program).
486 static inline nir_ssa_def
*
487 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
488 unsigned num_samples
, enum isl_msaa_layout layout
)
490 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
493 case ISL_MSAA_LAYOUT_NONE
:
494 /* No translation necessary, and S should already be zero. */
495 assert(pos
->num_components
== 2);
497 case ISL_MSAA_LAYOUT_ARRAY
:
498 /* No translation necessary. */
500 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
501 assert(pos
->num_components
== 2);
503 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
504 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
506 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
507 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
508 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
509 switch (num_samples
) {
512 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
513 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
514 * S = (X & 0b10) >> 1
516 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
517 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
518 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
519 * S = (Y & 0b10) | (X & 0b10) >> 1
521 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
522 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
523 if (num_samples
== 2) {
525 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
527 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
528 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
529 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
530 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
535 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
536 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
537 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
538 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
540 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
541 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
542 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
543 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
544 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
545 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
546 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
550 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
551 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
552 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
553 * S = (Y & 0b100) << 1 | (X & 0b100) |
554 * (Y & 0b10) | (X & 0b10) >> 1
556 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
557 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
558 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
559 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
560 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
561 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
562 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
563 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
567 unreachable("Invalid number of samples for IMS layout");
570 return nir_vec3(b
, x_out
, y_out
, s_out
);
574 unreachable("Invalid MSAA layout");
579 * Count the number of trailing 1 bits in the given value. For example:
581 * count_trailing_one_bits(0) == 0
582 * count_trailing_one_bits(7) == 3
583 * count_trailing_one_bits(11) == 2
585 static inline int count_trailing_one_bits(unsigned value
)
587 #ifdef HAVE___BUILTIN_CTZ
588 return __builtin_ctz(~value
);
590 return _mesa_bitcount(value
& ~(value
+ 1));
595 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
596 nir_ssa_def
*pos
, unsigned tex_samples
,
597 enum isl_aux_usage tex_aux_usage
,
598 nir_alu_type dst_type
)
600 /* If non-null, this is the outer-most if statement */
601 nir_if
*outer_if
= NULL
;
603 nir_variable
*color
=
604 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
606 nir_ssa_def
*mcs
= NULL
;
607 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
608 mcs
= blorp_blit_txf_ms_mcs(b
, v
, pos
);
610 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
612 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
614 * This ensures that when all samples have the same value, no numerical
615 * precision is lost, since each addition operation always adds two equal
616 * values, and summing two equal floating point values does not lose
619 * We perform this computation by treating the texture_data array as a
620 * stack and performing the following operations:
622 * - push sample 0 onto stack
623 * - push sample 1 onto stack
624 * - add top two stack entries
625 * - push sample 2 onto stack
626 * - push sample 3 onto stack
627 * - add top two stack entries
628 * - add top two stack entries
629 * - divide top stack entry by 4
631 * Note that after pushing sample i onto the stack, the number of add
632 * operations we do is equal to the number of trailing 1 bits in i. This
633 * works provided the total number of samples is a power of two, which it
634 * always is for i965.
636 * For integer formats, we replace the add operations with average
637 * operations and skip the final division.
639 nir_ssa_def
*texture_data
[5];
640 unsigned stack_depth
= 0;
641 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
642 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
644 /* Push sample i onto the stack */
645 assert(stack_depth
< ARRAY_SIZE(texture_data
));
647 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
648 nir_channel(b
, pos
, 1),
650 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
652 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
653 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
654 * suggests an optimization:
656 * "A simple optimization with probable large return in
657 * performance is to compare the MCS value to zero (indicating
658 * all samples are on sample slice 0), and sample only from
659 * sample slice 0 using ld2dss if MCS is zero."
661 * Note that in the case where the MCS value is zero, sampling from
662 * sample slice 0 using ld2dss and sampling from sample 0 using
663 * ld2dms are equivalent (since all samples are on sample slice 0).
664 * Since we have already sampled from sample 0, all we need to do is
665 * skip the remaining fetches and averaging if MCS is zero.
667 * It's also trivial to detect when the MCS has the magic clear color
668 * value. In this case, the txf we did on sample 0 will return the
669 * clear color and we can skip the remaining fetches just like we do
672 nir_ssa_def
*mcs_zero
=
673 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
674 if (tex_samples
== 16) {
675 mcs_zero
= nir_iand(b
, mcs_zero
,
676 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
678 nir_ssa_def
*mcs_clear
=
679 blorp_nir_mcs_is_clear_color(b
, mcs
, tex_samples
);
681 nir_if
*if_stmt
= nir_if_create(b
->shader
);
682 if_stmt
->condition
= nir_src_for_ssa(nir_ior(b
, mcs_zero
, mcs_clear
));
683 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
685 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
686 nir_store_var(b
, color
, texture_data
[0], 0xf);
688 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
692 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
693 assert(stack_depth
>= 2);
696 assert(dst_type
== nir_type_float
);
697 texture_data
[stack_depth
- 1] =
698 nir_fadd(b
, texture_data
[stack_depth
- 1],
699 texture_data
[stack_depth
]);
703 /* We should have just 1 sample on the stack now. */
704 assert(stack_depth
== 1);
706 texture_data
[0] = nir_fmul(b
, texture_data
[0],
707 nir_imm_float(b
, 1.0 / tex_samples
));
709 nir_store_var(b
, color
, texture_data
[0], 0xf);
712 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
714 return nir_load_var(b
, color
);
717 static inline nir_ssa_def
*
718 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
722 memset(&v
, 0, sizeof(v
));
726 return nir_build_imm(build
, 4, 32, v
);
730 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
731 unsigned tex_samples
,
732 const struct brw_blorp_blit_prog_key
*key
,
733 struct brw_blorp_blit_vars
*v
)
735 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
736 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
737 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
739 /* Translate coordinates to lay out the samples in a rectangular grid
740 * roughly corresponding to sample locations.
742 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
743 /* Adjust coordinates so that integers represent pixel centers rather
746 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
747 /* Clamp the X, Y texture coordinates to properly handle the sampling of
748 * texels on texture edges.
750 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
751 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
752 nir_channel(b
, rect_grid
, 1)));
754 /* Store the fractional parts to be used as bilinear interpolation
757 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
758 /* Round the float coordinates down to nearest integer */
759 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
761 nir_ssa_def
*tex_data
[4];
762 for (unsigned i
= 0; i
< 4; ++i
) {
763 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
764 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
765 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
767 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
768 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
770 /* The MCS value we fetch has to match up with the pixel that we're
771 * sampling from. Since we sample from different pixels in each
772 * iteration of this "for" loop, the call to mcs_fetch() should be
773 * here inside the loop after computing the pixel coordinates.
775 nir_ssa_def
*mcs
= NULL
;
776 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
777 mcs
= blorp_blit_txf_ms_mcs(b
, v
, sample_coords_int
);
779 /* Compute sample index and map the sample index to a sample number.
780 * Sample index layout shows the numbering of slots in a rectangular
781 * grid of samples with in a pixel. Sample number layout shows the
782 * rectangular grid of samples roughly corresponding to the real sample
783 * locations with in a pixel.
784 * In case of 4x MSAA, layout of sample indices matches the layout of
792 * In case of 8x MSAA the two layouts don't match.
793 * sample index layout : --------- sample number layout : ---------
794 * | 0 | 1 | | 3 | 7 |
795 * --------- ---------
796 * | 2 | 3 | | 5 | 0 |
797 * --------- ---------
798 * | 4 | 5 | | 1 | 2 |
799 * --------- ---------
800 * | 6 | 7 | | 4 | 6 |
801 * --------- ---------
803 * Fortunately, this can be done fairly easily as:
804 * S' = (0x17306425 >> (S * 4)) & 0xf
806 * In the case of 16x MSAA the two layouts don't match.
807 * Sample index layout: Sample number layout:
808 * --------------------- ---------------------
809 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
810 * --------------------- ---------------------
811 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
812 * --------------------- ---------------------
813 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
814 * --------------------- ---------------------
815 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
816 * --------------------- ---------------------
818 * This is equivalent to
819 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
821 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
822 nir_ssa_def
*sample
=
823 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
824 key
->x_scale
* key
->y_scale
));
825 sample
= nir_f2i32(b
, sample
);
827 if (tex_samples
== 8) {
828 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
829 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
830 nir_imm_int(b
, 0xf));
831 } else if (tex_samples
== 16) {
832 nir_ssa_def
*sample_low
=
833 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
834 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
835 nir_imm_int(b
, 0xf));
836 nir_ssa_def
*sample_high
=
837 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
838 nir_ishl(b
, nir_iadd(b
, sample
,
841 nir_imm_int(b
, 0xf));
843 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
844 sample_low
, sample_high
);
846 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
847 nir_channel(b
, sample_coords_int
, 1),
849 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
852 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
853 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
854 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
855 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
859 /** Perform a color bit-cast operation
861 * For copy operations involving CCS, we may need to use different formats for
862 * the source and destination surfaces. The two formats must both be UINT
863 * formats and must have the same size but may have different bit layouts.
864 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
865 * to R16G16_UINT. This function generates code to shuffle bits around to get
866 * us from one to the other.
869 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
870 const struct brw_blorp_blit_prog_key
*key
)
872 assert(key
->texture_data_type
== nir_type_uint
);
874 if (key
->dst_bpc
> key
->src_bpc
) {
875 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
876 nir_ssa_def
*dst_chan
[2] = { u
, u
};
878 unsigned dst_idx
= 0;
879 for (unsigned i
= 0; i
< 4; i
++) {
880 nir_ssa_def
*shifted
= nir_ishl(b
, nir_channel(b
, color
, i
),
881 nir_imm_int(b
, shift
));
883 dst_chan
[dst_idx
] = shifted
;
885 dst_chan
[dst_idx
] = nir_ior(b
, dst_chan
[dst_idx
], shifted
);
888 shift
+= key
->src_bpc
;
889 if (shift
>= key
->dst_bpc
) {
895 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], u
, u
);
897 assert(key
->dst_bpc
< key
->src_bpc
);
899 nir_ssa_def
*mask
= nir_imm_int(b
, ~0u >> (32 - key
->dst_bpc
));
901 nir_ssa_def
*dst_chan
[4];
902 unsigned src_idx
= 0;
904 for (unsigned i
= 0; i
< 4; i
++) {
905 dst_chan
[i
] = nir_iand(b
, nir_ushr(b
, nir_channel(b
, color
, src_idx
),
906 nir_imm_int(b
, shift
)),
908 shift
+= key
->dst_bpc
;
909 if (shift
>= key
->src_bpc
) {
915 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], dst_chan
[2], dst_chan
[3]);
920 select_color_channel(struct nir_builder
*b
, nir_ssa_def
*color
,
921 nir_alu_type data_type
,
922 enum isl_channel_select chan
)
924 if (chan
== ISL_CHANNEL_SELECT_ZERO
) {
925 return nir_imm_int(b
, 0);
926 } else if (chan
== ISL_CHANNEL_SELECT_ONE
) {
930 return nir_imm_int(b
, 1);
932 return nir_imm_float(b
, 1);
934 unreachable("Invalid data type");
937 assert((unsigned)(chan
- ISL_CHANNEL_SELECT_RED
) < 4);
938 return nir_channel(b
, color
, chan
- ISL_CHANNEL_SELECT_RED
);
943 swizzle_color(struct nir_builder
*b
, nir_ssa_def
*color
,
944 struct isl_swizzle swizzle
, nir_alu_type data_type
)
947 select_color_channel(b
, color
, data_type
, swizzle
.r
),
948 select_color_channel(b
, color
, data_type
, swizzle
.g
),
949 select_color_channel(b
, color
, data_type
, swizzle
.b
),
950 select_color_channel(b
, color
, data_type
, swizzle
.a
));
954 convert_color(struct nir_builder
*b
, nir_ssa_def
*color
,
955 const struct brw_blorp_blit_prog_key
*key
)
957 /* All of our color conversions end up generating a single-channel color
958 * value that we need to write out.
962 if (key
->dst_format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
963 /* The destination image is bound as R32_UNORM but the data needs to be
964 * in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and the
965 * top 8 need to be zero. We can accomplish this by simply multiplying
966 * by a factor to scale things down.
968 float factor
= (float)((1 << 24) - 1) / (float)UINT32_MAX
;
969 value
= nir_fmul(b
, nir_fsat(b
, nir_channel(b
, color
, 0)),
970 nir_imm_float(b
, factor
));
971 } else if (key
->dst_format
== ISL_FORMAT_L8_UNORM_SRGB
) {
972 value
= nir_format_linear_to_srgb(b
, color
);
973 } else if (key
->dst_format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
974 value
= nir_format_pack_r9g9b9e5(b
, color
);
976 unreachable("Unsupported format conversion");
979 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
980 return nir_vec4(b
, value
, u
, u
, u
);
984 * Generator for WM programs used in BLORP blits.
986 * The bulk of the work done by the WM program is to wrap and unwrap the
987 * coordinate transformations used by the hardware to store surfaces in
988 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
989 * sample index for a multisampled surface) to a memory offset by the
990 * following formulas:
992 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
993 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
995 * For a single-sampled surface, or for a multisampled surface using
996 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
999 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1000 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1001 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1002 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1004 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1005 * embeds the sample number into bit 1 of the X and Y coordinates:
1007 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1008 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1009 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
1010 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1011 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1012 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1013 * S = (Y & 0b10) | (X & 0b10) >> 1
1015 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1016 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
1019 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1020 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
1021 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1022 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1023 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1024 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1025 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1027 * For X tiling, tile() combines together the low-order bits of the X and Y
1028 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
1029 * bytes wide and 8 rows high:
1031 * tile(x_tiled, X, Y, S) = A
1032 * where A = tile_num << 12 | offset
1033 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
1034 * offset = (Y' & 0b111) << 9
1035 * | (X & 0b111111111)
1037 * Y' = Y + S * qpitch
1038 * detile(x_tiled, A) = (X, Y, S)
1039 * where X = X' / cpp
1042 * Y' = (tile_num / tile_pitch) << 3
1043 * | (A & 0b111000000000) >> 9
1044 * X' = (tile_num % tile_pitch) << 9
1045 * | (A & 0b111111111)
1047 * (In all tiling formulas, cpp is the number of bytes occupied by a single
1048 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
1049 * to fill the width of the surface, and qpitch is the spacing (in rows)
1050 * between array slices).
1052 * For Y tiling, tile() combines together the low-order bits of the X and Y
1053 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
1054 * bytes wide and 32 rows high:
1056 * tile(y_tiled, X, Y, S) = A
1057 * where A = tile_num << 12 | offset
1058 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
1059 * offset = (X' & 0b1110000) << 5
1060 * | (Y' & 0b11111) << 4
1063 * Y' = Y + S * qpitch
1064 * detile(y_tiled, A) = (X, Y, S)
1065 * where X = X' / cpp
1068 * Y' = (tile_num / tile_pitch) << 5
1069 * | (A & 0b111110000) >> 4
1070 * X' = (tile_num % tile_pitch) << 7
1071 * | (A & 0b111000000000) >> 5
1074 * For W tiling, tile() combines together the low-order bits of the X and Y
1075 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1076 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1077 * buffers, which always have cpp = 1 and S=0):
1079 * tile(w_tiled, X, Y, S) = A
1080 * where A = tile_num << 12 | offset
1081 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1082 * offset = (X' & 0b111000) << 6
1083 * | (Y' & 0b111100) << 3
1084 * | (X' & 0b100) << 2
1085 * | (Y' & 0b10) << 2
1086 * | (X' & 0b10) << 1
1090 * Y' = Y + S * qpitch
1091 * detile(w_tiled, A) = (X, Y, S)
1092 * where X = X' / cpp = X'
1093 * Y = Y' % qpitch = Y'
1094 * S = Y / qpitch = 0
1095 * Y' = (tile_num / tile_pitch) << 6
1096 * | (A & 0b111100000) >> 3
1097 * | (A & 0b1000) >> 2
1099 * X' = (tile_num % tile_pitch) << 6
1100 * | (A & 0b111000000000) >> 6
1101 * | (A & 0b10000) >> 2
1102 * | (A & 0b100) >> 1
1105 * Finally, for a non-tiled surface, tile() simply combines together the X and
1106 * Y coordinates in the natural way:
1108 * tile(untiled, X, Y, S) = A
1109 * where A = Y * pitch + X'
1111 * Y' = Y + S * qpitch
1112 * detile(untiled, A) = (X, Y, S)
1113 * where X = X' / cpp
1119 * (In these formulas, pitch is the number of bytes occupied by a single row
1123 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1124 const struct brw_blorp_blit_prog_key
*key
)
1126 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1127 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1130 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1131 /* If the destination image is W tiled and multisampled, then the thread
1132 * must be dispatched once per sample, not once per pixel. This is
1133 * necessary because after conversion between W and Y tiling, there's no
1134 * guarantee that all samples corresponding to a single pixel will still
1137 assert(key
->persample_msaa_dispatch
);
1141 /* We are blending, which means we won't have an opportunity to
1142 * translate the tiling and sample count for the texture surface. So
1143 * the surface state for the texture must be configured with the correct
1144 * tiling and sample count.
1146 assert(!key
->src_tiled_w
);
1147 assert(key
->tex_samples
== key
->src_samples
);
1148 assert(key
->tex_layout
== key
->src_layout
);
1149 assert(key
->tex_samples
> 0);
1152 if (key
->persample_msaa_dispatch
) {
1153 /* It only makes sense to do persample dispatch if the render target is
1154 * configured as multisampled.
1156 assert(key
->rt_samples
> 0);
1159 /* Make sure layout is consistent with sample count */
1160 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1161 (key
->tex_samples
<= 1));
1162 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1163 (key
->rt_samples
<= 1));
1164 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1165 (key
->src_samples
<= 1));
1166 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1167 (key
->dst_samples
<= 1));
1170 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1172 struct brw_blorp_blit_vars v
;
1173 brw_blorp_blit_vars_init(&b
, &v
, key
);
1175 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1177 /* Render target and texture hardware don't support W tiling until Gen8. */
1178 const bool rt_tiled_w
= false;
1179 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1181 /* The address that data will be written to is determined by the
1182 * coordinates supplied to the WM thread and the tiling and sample count of
1183 * the render target, according to the formula:
1185 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1187 * If the actual tiling and sample count of the destination surface are not
1188 * the same as the configuration of the render target, then these
1189 * coordinates are wrong and we have to adjust them to compensate for the
1192 if (rt_tiled_w
!= key
->dst_tiled_w
||
1193 key
->rt_samples
!= key
->dst_samples
||
1194 key
->rt_layout
!= key
->dst_layout
) {
1195 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1197 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1198 if (rt_tiled_w
!= key
->dst_tiled_w
)
1199 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1200 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1201 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1205 nir_ssa_def
*comp
= NULL
;
1207 /* The destination image is bound as a red texture three times as wide
1208 * as the actual image. Our shader is effectively running one color
1209 * component at a time. We need to save off the component and adjust
1210 * the destination position.
1212 assert(dst_pos
->num_components
== 2);
1213 nir_ssa_def
*dst_x
= nir_channel(&b
, dst_pos
, 0);
1214 comp
= nir_umod(&b
, dst_x
, nir_imm_int(&b
, 3));
1215 dst_pos
= nir_vec2(&b
, nir_idiv(&b
, dst_x
, nir_imm_int(&b
, 3)),
1216 nir_channel(&b
, dst_pos
, 1));
1219 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1221 * That is: X, Y and S now contain the true coordinates and sample index of
1222 * the data that the WM thread should output.
1224 * If we need to kill pixels that are outside the destination rectangle,
1225 * now is the time to do it.
1227 if (key
->use_kill
) {
1228 assert(!(key
->blend
&& key
->blit_scaled
));
1229 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1232 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1233 if (dst_pos
->num_components
== 3) {
1234 /* The sample coordinate is an integer that we want left alone but
1235 * blorp_blit_apply_transform() blindly applies the transform to all
1236 * three coordinates. Grab the original sample index.
1238 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1239 nir_channel(&b
, src_pos
, 1),
1240 nir_channel(&b
, dst_pos
, 2));
1243 /* If the source image is not multisampled, then we want to fetch sample
1244 * number 0, because that's the only sample there is.
1246 if (key
->src_samples
== 1)
1247 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1249 /* X, Y, and S are now the coordinates of the pixel in the source image
1250 * that we want to texture from. Exception: if we are blending, then S is
1251 * irrelevant, because we are going to fetch all samples.
1253 if (key
->blend
&& !key
->blit_scaled
) {
1254 /* Resolves (effecively) use texelFetch, so we need integers and we
1255 * don't care about the sample index if we got one.
1257 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1259 if (devinfo
->gen
== 6) {
1260 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1261 * blending we need with a single linear-interpolated texture lookup
1262 * at the center of the sample. The texture coordinates to be odd
1263 * integers so that they correspond to the center of a 2x2 block
1264 * representing the four samples that maxe up a pixel. So we need
1265 * to multiply our X and Y coordinates each by 2 and then add 1.
1267 assert(key
->src_coords_normalized
);
1268 src_pos
= nir_fadd(&b
,
1269 nir_i2f32(&b
, src_pos
),
1270 nir_imm_float(&b
, 0.5f
));
1271 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1273 /* Gen7+ hardware doesn't automaticaly blend. */
1274 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1276 key
->texture_data_type
);
1278 } else if (key
->blend
&& key
->blit_scaled
) {
1279 assert(!key
->use_kill
);
1280 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1282 if (key
->bilinear_filter
) {
1283 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1285 /* We're going to use texelFetch, so we need integers */
1286 if (src_pos
->num_components
== 2) {
1287 src_pos
= nir_f2i32(&b
, src_pos
);
1289 assert(src_pos
->num_components
== 3);
1290 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1291 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1292 nir_channel(&b
, src_pos
, 2));
1295 /* We aren't blending, which means we just want to fetch a single
1296 * sample from the source surface. The address that we want to fetch
1297 * from is related to the X, Y and S values according to the formula:
1299 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1301 * If the actual tiling and sample count of the source surface are
1302 * not the same as the configuration of the texture, then we need to
1303 * adjust the coordinates to compensate for the difference.
1305 if (tex_tiled_w
!= key
->src_tiled_w
||
1306 key
->tex_samples
!= key
->src_samples
||
1307 key
->tex_layout
!= key
->src_layout
) {
1308 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1310 /* Now (X, Y, S) = detile(src_tiling, offset) */
1311 if (tex_tiled_w
!= key
->src_tiled_w
)
1312 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1313 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1314 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1318 if (key
->need_src_offset
)
1319 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1321 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1323 * In other words: X, Y, and S now contain values which, when passed to
1324 * the texturing unit, will cause data to be read from the correct
1325 * memory location. So we can fetch the texel now.
1327 if (key
->src_samples
== 1) {
1328 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1330 nir_ssa_def
*mcs
= NULL
;
1331 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1332 mcs
= blorp_blit_txf_ms_mcs(&b
, &v
, src_pos
);
1334 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1339 if (!isl_swizzle_is_identity(key
->src_swizzle
)) {
1340 color
= swizzle_color(&b
, color
, key
->src_swizzle
,
1341 key
->texture_data_type
);
1344 if (!isl_swizzle_is_identity(key
->dst_swizzle
)) {
1345 color
= swizzle_color(&b
, color
, isl_swizzle_invert(key
->dst_swizzle
),
1349 if (key
->dst_bpc
!= key
->src_bpc
) {
1350 assert(isl_swizzle_is_identity(key
->src_swizzle
));
1351 assert(isl_swizzle_is_identity(key
->dst_swizzle
));
1352 color
= bit_cast_color(&b
, color
, key
);
1355 if (key
->dst_format
)
1356 color
= convert_color(&b
, color
, key
);
1359 /* The destination image is bound as a red texture three times as wide
1360 * as the actual image. Our shader is effectively running one color
1361 * component at a time. We need to pick off the appropriate component
1362 * from the source color and write that to destination red.
1364 assert(dst_pos
->num_components
== 2);
1366 nir_ssa_def
*color_component
=
1367 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1368 nir_channel(&b
, color
, 0),
1369 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1370 nir_channel(&b
, color
, 1),
1371 nir_channel(&b
, color
, 2)));
1373 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1374 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1377 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1383 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1384 struct blorp_params
*params
,
1385 const struct brw_blorp_blit_prog_key
*prog_key
)
1387 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1388 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1391 void *mem_ctx
= ralloc_context(NULL
);
1393 const unsigned *program
;
1394 struct brw_wm_prog_data prog_data
;
1396 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1397 nir
->info
.name
= ralloc_strdup(nir
, "BLORP-blit");
1399 struct brw_wm_prog_key wm_key
;
1400 brw_blorp_init_wm_prog_key(&wm_key
);
1401 wm_key
.tex
.compressed_multisample_layout_mask
=
1402 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1403 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1404 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1406 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1410 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1411 program
, prog_data
.base
.program_size
,
1412 &prog_data
.base
, sizeof(prog_data
),
1413 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1415 ralloc_free(mem_ctx
);
1420 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1421 GLfloat src0
, GLfloat src1
,
1422 GLfloat dst0
, GLfloat dst1
,
1425 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1427 /* When not mirroring a coordinate (say, X), we need:
1428 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1430 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1432 * blorp program uses "round toward zero" to convert the
1433 * transformed floating point coordinates to integer coordinates,
1434 * whereas the behaviour we actually want is "round to nearest",
1435 * so 0.5 provides the necessary correction.
1437 xform
->multiplier
= scale
;
1438 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1440 /* When mirroring X we need:
1441 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1443 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1445 xform
->multiplier
= -scale
;
1446 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1451 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1452 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1454 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1455 struct isl_extent2d px_size_sa
=
1456 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1457 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1458 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1459 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1460 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1462 *tile_x_px
= info
->tile_x_sa
;
1463 *tile_y_px
= info
->tile_y_sa
;
1468 blorp_surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1469 struct brw_blorp_surface_info
*info
)
1473 /* Just bail if we have nothing to do. */
1474 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1475 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1476 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1479 /* If this gets triggered then we've gotten here twice which. This
1480 * shouldn't happen thanks to the above early return.
1482 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1484 uint32_t layer
= 0, z
= 0;
1485 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1486 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1488 layer
= info
->view
.base_array_layer
;
1490 uint32_t byte_offset
;
1491 isl_surf_get_image_surf(isl_dev
, &info
->surf
,
1492 info
->view
.base_level
, layer
, z
,
1494 &byte_offset
, &info
->tile_x_sa
, &info
->tile_y_sa
);
1495 info
->addr
.offset
+= byte_offset
;
1497 uint32_t tile_x_px
, tile_y_px
;
1498 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1500 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we place
1501 * the image at the tile boundary and offset our sampling or rendering.
1502 * For this reason, we need to grow the image by the offset to ensure that
1503 * the hardware doesn't think we've gone past the edge.
1505 info
->surf
.logical_level0_px
.w
+= tile_x_px
;
1506 info
->surf
.logical_level0_px
.h
+= tile_y_px
;
1507 info
->surf
.phys_level0_sa
.w
+= info
->tile_x_sa
;
1508 info
->surf
.phys_level0_sa
.h
+= info
->tile_y_sa
;
1510 /* The view is also different now. */
1511 info
->view
.base_level
= 0;
1512 info
->view
.levels
= 1;
1513 info
->view
.base_array_layer
= 0;
1514 info
->view
.array_len
= 1;
1519 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1520 struct brw_blorp_surface_info
*info
)
1522 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1524 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1525 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1527 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1528 info
->surf
.samples
= 1;
1529 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1533 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1534 struct brw_blorp_surface_info
*info
)
1536 assert(info
->surf
.tiling
== ISL_TILING_W
);
1538 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1539 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1541 /* On gen7+, we don't have interleaved multisampling for color render
1542 * targets so we have to fake it.
1544 * TODO: Are we sure we don't also need to fake it on gen6?
1546 if (isl_dev
->info
->gen
> 6 &&
1547 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1548 surf_fake_interleaved_msaa(isl_dev
, info
);
1551 if (isl_dev
->info
->gen
== 6) {
1552 /* Gen6 stencil buffers have a very large alignment coming in from the
1553 * miptree. It's out-of-bounds for what the surface state can handle.
1554 * Since we have a single layer and level, it doesn't really matter as
1555 * long as we don't pass a bogus value into isl_surf_fill_state().
1557 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1560 /* Now that we've converted everything to a simple 2-D surface with only
1561 * one miplevel, we can go about retiling it.
1563 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1564 info
->surf
.tiling
= ISL_TILING_Y0
;
1565 info
->surf
.logical_level0_px
.width
=
1566 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1567 info
->surf
.logical_level0_px
.height
=
1568 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1569 info
->tile_x_sa
*= 2;
1570 info
->tile_y_sa
/= 2;
1574 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1576 /* The current code doesn't support offsets into the aux buffers. This
1577 * should be possible, but we need to make sure the offset is page
1578 * aligned for both the surface and the aux buffer surface. Generally
1579 * this mean using the page aligned offset for the aux buffer.
1581 * Currently the cases where we must split the blit are limited to cases
1582 * where we don't have a aux buffer.
1584 if (surf
->aux_addr
.buffer
!= NULL
)
1587 /* We can't support splitting the blit for gen <= 7, because the qpitch
1588 * size is calculated by the hardware based on the surface height for
1589 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1591 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1598 can_shrink_surfaces(const struct blorp_params
*params
)
1601 can_shrink_surface(¶ms
->src
) &&
1602 can_shrink_surface(¶ms
->dst
);
1606 get_max_surface_size(const struct gen_device_info
*devinfo
,
1607 const struct blorp_params
*params
)
1609 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1610 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1611 return max
>> 4; /* A smaller restriction when debug is enabled */
1617 double src0
, src1
, dst0
, dst1
;
1622 struct blt_axis x
, y
;
1625 static enum isl_format
1626 get_red_format_for_rgb_format(enum isl_format format
)
1628 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1630 switch (fmtl
->channels
.r
.bits
) {
1632 switch (fmtl
->channels
.r
.type
) {
1634 return ISL_FORMAT_R8_UNORM
;
1636 return ISL_FORMAT_R8_SNORM
;
1638 return ISL_FORMAT_R8_UINT
;
1640 return ISL_FORMAT_R8_SINT
;
1642 unreachable("Invalid 8-bit RGB channel type");
1645 switch (fmtl
->channels
.r
.type
) {
1647 return ISL_FORMAT_R16_UNORM
;
1649 return ISL_FORMAT_R16_SNORM
;
1651 return ISL_FORMAT_R16_FLOAT
;
1653 return ISL_FORMAT_R16_UINT
;
1655 return ISL_FORMAT_R16_SINT
;
1657 unreachable("Invalid 8-bit RGB channel type");
1660 switch (fmtl
->channels
.r
.type
) {
1662 return ISL_FORMAT_R32_FLOAT
;
1664 return ISL_FORMAT_R32_UINT
;
1666 return ISL_FORMAT_R32_SINT
;
1668 unreachable("Invalid 8-bit RGB channel type");
1671 unreachable("Invalid number of red channel bits");
1676 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1677 struct brw_blorp_surface_info
*info
)
1679 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1681 info
->surf
.logical_level0_px
.width
*= 3;
1682 info
->surf
.phys_level0_sa
.width
*= 3;
1683 info
->tile_x_sa
*= 3;
1685 enum isl_format red_format
=
1686 get_red_format_for_rgb_format(info
->view
.format
);
1688 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1689 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1690 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1691 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1693 info
->surf
.format
= info
->view
.format
= red_format
;
1696 enum blit_shrink_status
{
1698 BLIT_WIDTH_SHRINK
= 1,
1699 BLIT_HEIGHT_SHRINK
= 2,
1702 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1703 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1704 * returned, then the blit was successful.
1706 static enum blit_shrink_status
1707 try_blorp_blit(struct blorp_batch
*batch
,
1708 struct blorp_params
*params
,
1709 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1710 struct blt_coords
*coords
)
1712 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1714 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1715 wm_prog_key
->texture_data_type
= nir_type_int
;
1716 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1717 wm_prog_key
->texture_data_type
= nir_type_uint
;
1719 wm_prog_key
->texture_data_type
= nir_type_float
;
1722 /* src_samples and dst_samples are the true sample counts */
1723 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1724 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1726 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1728 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1731 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1732 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1734 /* Round floating point values to nearest integer to avoid "off by one texel"
1735 * kind of errors when blitting.
1737 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1738 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1739 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1740 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1742 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1743 coords
->x
.src0
, coords
->x
.src1
,
1744 coords
->x
.dst0
, coords
->x
.dst1
,
1746 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1747 coords
->y
.src0
, coords
->y
.src1
,
1748 coords
->y
.dst0
, coords
->y
.dst1
,
1752 if (devinfo
->gen
== 4) {
1753 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
1754 * Convert them to a single slice on gen4.
1756 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1757 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1758 wm_prog_key
->need_dst_offset
= true;
1761 if (params
->src
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1762 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->src
);
1763 wm_prog_key
->need_src_offset
= true;
1767 if (devinfo
->gen
> 6 &&
1768 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1769 assert(params
->dst
.surf
.samples
> 1);
1771 /* We must expand the rectangle we send through the rendering pipeline,
1772 * to account for the fact that we are mapping the destination region as
1773 * single-sampled when it is in fact multisampled. We must also align
1774 * it to a multiple of the multisampling pattern, because the
1775 * differences between multisampled and single-sampled surface formats
1776 * will mean that pixels are scrambled within the multisampling pattern.
1777 * TODO: what if this makes the coordinates too large?
1779 * Note: this only works if the destination surface uses the IMS layout.
1780 * If it's UMS, then we have no choice but to set up the rendering
1781 * pipeline as multisampled.
1783 struct isl_extent2d px_size_sa
=
1784 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1785 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1786 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1787 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1788 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1790 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1792 wm_prog_key
->use_kill
= true;
1793 wm_prog_key
->need_dst_offset
= true;
1796 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1797 /* We must modify the rectangle we send through the rendering pipeline
1798 * (and the size and x/y offset of the destination surface), to account
1799 * for the fact that we are mapping it as Y-tiled when it is in fact
1802 * Both Y tiling and W tiling can be understood as organizations of
1803 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1804 * is different, but the layout of the 32-byte sub-tiles within the 4k
1805 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1806 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1807 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1809 * Therefore, to account for the layout differences within the 32-byte
1810 * sub-tiles, we must expand the rectangle so the X coordinates of its
1811 * edges are multiples of 8 (the W sub-tile width), and its Y
1812 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1813 * Then we need to scale the X and Y coordinates of the rectangle to
1814 * account for the differences in aspect ratio between the Y and W
1815 * sub-tiles. We need to modify the layer width and height similarly.
1817 * A correction needs to be applied when MSAA is in use: since
1818 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1819 * we need to align the Y coordinates to multiples of 8, so that when
1820 * they are divided by two they are still multiples of 4.
1822 * Note: Since the x/y offset of the surface will be applied using the
1823 * SURFACE_STATE command packet, it will be invisible to the swizzling
1824 * code in the shader; therefore it needs to be in a multiple of the
1825 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1826 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1827 * buffer), and the miplevel alignment used for stencil buffers is 8
1828 * pixels horizontally and either 4 or 8 pixels vertically (see
1829 * intel_horizontal_texture_alignment_unit() and
1830 * intel_vertical_texture_alignment_unit()).
1832 * Note: Also, since the SURFACE_STATE command packet can only apply
1833 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1834 * vertically, it is important that the offsets will be multiples of
1835 * these sizes after they are converted into Y-tiled coordinates.
1836 * Fortunately they will be, since we know from above that the offsets
1837 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1838 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1840 * TODO: what if this makes the coordinates (or the texture size) too
1843 const unsigned x_align
= 8;
1844 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1845 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1846 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1847 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1848 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1850 /* Retile the surface to Y-tiled */
1851 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1853 wm_prog_key
->dst_tiled_w
= true;
1854 wm_prog_key
->use_kill
= true;
1855 wm_prog_key
->need_dst_offset
= true;
1857 if (params
->dst
.surf
.samples
> 1) {
1858 /* If the destination surface is a W-tiled multisampled stencil
1859 * buffer that we're mapping as Y tiled, then we need to arrange for
1860 * the WM program to run once per sample rather than once per pixel,
1861 * because the memory layout of related samples doesn't match between
1864 wm_prog_key
->persample_msaa_dispatch
= true;
1868 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1869 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1870 * Broadwell adds support for sampling from stencil.
1872 * See the comments above concerning x/y offset alignment for the
1873 * destination surface.
1875 * TODO: what if this makes the texture size too large?
1877 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1879 wm_prog_key
->src_tiled_w
= true;
1880 wm_prog_key
->need_src_offset
= true;
1883 /* tex_samples and rt_samples are the sample counts that are set up in
1886 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1887 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1889 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1890 * use to access the source and destination surfaces.
1892 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1893 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1895 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1896 /* We are blitting from a multisample buffer to a multisample buffer, so
1897 * we must preserve samples within a pixel. This means we have to
1898 * arrange for the WM program to run once per sample rather than once
1901 wm_prog_key
->persample_msaa_dispatch
= true;
1904 params
->num_samples
= params
->dst
.surf
.samples
;
1906 if ((wm_prog_key
->bilinear_filter
||
1907 (wm_prog_key
->blend
&& !wm_prog_key
->blit_scaled
)) &&
1908 batch
->blorp
->isl_dev
->info
->gen
<= 6) {
1909 /* Gen4-5 don't support non-normalized texture coordinates */
1910 wm_prog_key
->src_coords_normalized
= true;
1911 params
->wm_inputs
.src_inv_size
[0] =
1912 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.width
,
1913 params
->src
.view
.base_level
);
1914 params
->wm_inputs
.src_inv_size
[1] =
1915 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.height
,
1916 params
->src
.view
.base_level
);
1919 if (isl_format_get_layout(params
->dst
.view
.format
)->bpb
% 3 == 0) {
1920 /* We can't render to RGB formats natively because they aren't a
1921 * power-of-two size. Instead, we fake them by using a red format
1922 * with the same channel type and size and emitting shader code to
1923 * only write one channel at a time.
1928 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1930 wm_prog_key
->dst_rgb
= true;
1931 wm_prog_key
->need_dst_offset
= true;
1932 } else if (isl_format_is_rgbx(params
->dst
.view
.format
)) {
1933 /* We can handle RGBX formats easily enough by treating them as RGBA */
1934 params
->dst
.view
.format
=
1935 isl_format_rgbx_to_rgba(params
->dst
.view
.format
);
1936 } else if (params
->dst
.view
.format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
1937 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
1938 params
->dst
.view
.format
= ISL_FORMAT_R32_UNORM
;
1939 } else if (params
->dst
.view
.format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
1940 params
->dst
.view
.swizzle
=
1941 isl_swizzle_compose(params
->dst
.view
.swizzle
,
1942 ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
));
1943 params
->dst
.view
.format
= ISL_FORMAT_B4G4R4A4_UNORM
;
1944 } else if (params
->dst
.view
.format
== ISL_FORMAT_L8_UNORM_SRGB
) {
1945 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
1946 params
->dst
.view
.format
= ISL_FORMAT_R8_UNORM
;
1947 } else if (params
->dst
.view
.format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
1948 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
1949 params
->dst
.view
.format
= ISL_FORMAT_R32_UINT
;
1952 if (devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
1953 !isl_swizzle_is_identity(params
->src
.view
.swizzle
)) {
1954 wm_prog_key
->src_swizzle
= params
->src
.view
.swizzle
;
1955 params
->src
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
1957 wm_prog_key
->src_swizzle
= ISL_SWIZZLE_IDENTITY
;
1960 if (!isl_swizzle_supports_rendering(devinfo
, params
->dst
.view
.swizzle
)) {
1961 wm_prog_key
->dst_swizzle
= params
->dst
.view
.swizzle
;
1962 params
->dst
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
1964 wm_prog_key
->dst_swizzle
= ISL_SWIZZLE_IDENTITY
;
1967 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
1968 assert(wm_prog_key
->need_src_offset
);
1969 surf_get_intratile_offset_px(¶ms
->src
,
1970 ¶ms
->wm_inputs
.src_offset
.x
,
1971 ¶ms
->wm_inputs
.src_offset
.y
);
1974 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
1975 assert(wm_prog_key
->need_dst_offset
);
1976 surf_get_intratile_offset_px(¶ms
->dst
,
1977 ¶ms
->wm_inputs
.dst_offset
.x
,
1978 ¶ms
->wm_inputs
.dst_offset
.y
);
1979 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
1980 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
1981 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
1982 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
1985 /* For some texture types, we need to pass the layer through the sampler. */
1986 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
1988 if (!brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
))
1991 if (!blorp_ensure_sf_program(batch
->blorp
, params
))
1994 unsigned result
= 0;
1995 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
1996 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
1997 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
1998 result
|= BLIT_WIDTH_SHRINK
;
1999 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
2000 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
2001 result
|= BLIT_HEIGHT_SHRINK
;
2004 batch
->blorp
->exec(batch
, params
);
2010 /* Adjust split blit source coordinates for the current destination
2014 adjust_split_source_coords(const struct blt_axis
*orig
,
2015 struct blt_axis
*split_coords
,
2018 /* When scale is greater than 0, then we are growing from the start, so
2019 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
2020 * source range shrinks from the end. In that case src0 is adjusted by
2021 * delta1, and src1 is adjusted by delta0.
2023 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
2024 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
2025 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
2026 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
2029 static struct isl_extent2d
2030 get_px_size_sa(const struct isl_surf
*surf
)
2032 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
2034 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
2037 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
2041 shrink_surface_params(const struct isl_device
*dev
,
2042 struct brw_blorp_surface_info
*info
,
2043 double *x0
, double *x1
, double *y0
, double *y1
)
2045 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
2046 struct isl_extent2d px_size_sa
;
2049 blorp_surf_convert_to_single_slice(dev
, info
);
2051 px_size_sa
= get_px_size_sa(&info
->surf
);
2053 /* Because this gets called after we lower compressed images, the tile
2054 * offsets may be non-zero and we need to incorporate them in our
2057 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
2058 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
2059 isl_tiling_get_intratile_offset_sa(info
->surf
.tiling
,
2060 info
->surf
.format
, info
->surf
.row_pitch
,
2061 x_offset_sa
, y_offset_sa
,
2063 &info
->tile_x_sa
, &info
->tile_y_sa
);
2065 info
->addr
.offset
+= byte_offset
;
2067 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
2070 info
->tile_x_sa
= 0;
2072 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
2075 info
->tile_y_sa
= 0;
2077 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
2078 info
->surf
.logical_level0_px
.width
= size
;
2079 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
2081 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
2082 info
->surf
.logical_level0_px
.height
= size
;
2083 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
2087 shrink_surfaces(const struct isl_device
*dev
,
2088 struct blorp_params
*params
,
2089 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2090 struct blt_coords
*coords
)
2092 /* Shrink source surface */
2093 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
2094 &coords
->y
.src0
, &coords
->y
.src1
);
2095 wm_prog_key
->need_src_offset
= false;
2097 /* Shrink destination surface */
2098 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
2099 &coords
->y
.dst0
, &coords
->y
.dst1
);
2100 wm_prog_key
->need_dst_offset
= false;
2104 do_blorp_blit(struct blorp_batch
*batch
,
2105 const struct blorp_params
*orig_params
,
2106 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2107 const struct blt_coords
*orig
)
2109 struct blorp_params params
;
2110 struct blt_coords blit_coords
;
2111 struct blt_coords split_coords
= *orig
;
2112 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
2113 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
2114 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
2115 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
2121 bool x_done
, y_done
;
2122 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
2124 params
= *orig_params
;
2125 blit_coords
= split_coords
;
2127 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
2129 enum blit_shrink_status result
=
2130 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
2132 if (result
& BLIT_WIDTH_SHRINK
) {
2135 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2136 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2138 if (result
& BLIT_HEIGHT_SHRINK
) {
2141 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2142 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2146 assert(can_shrink_surfaces(orig_params
));
2151 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
2152 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
2155 } else if (y_done
) {
2156 split_coords
.x
.dst0
+= w
;
2157 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2158 split_coords
.y
.dst0
= orig
->y
.dst0
;
2159 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2160 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2162 split_coords
.y
.dst0
+= h
;
2163 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2164 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2170 blorp_blit(struct blorp_batch
*batch
,
2171 const struct blorp_surf
*src_surf
,
2172 unsigned src_level
, unsigned src_layer
,
2173 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2174 const struct blorp_surf
*dst_surf
,
2175 unsigned dst_level
, unsigned dst_layer
,
2176 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2177 float src_x0
, float src_y0
,
2178 float src_x1
, float src_y1
,
2179 float dst_x0
, float dst_y0
,
2180 float dst_x1
, float dst_y1
,
2181 GLenum filter
, bool mirror_x
, bool mirror_y
)
2183 struct blorp_params params
;
2184 blorp_params_init(¶ms
);
2186 /* We cannot handle combined depth and stencil. */
2187 if (src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2188 assert(src_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2189 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2190 assert(dst_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2192 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
2193 assert(src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
);
2194 /* Prior to Broadwell, we can't render to R8_UINT */
2195 if (batch
->blorp
->isl_dev
->info
->gen
< 8) {
2196 src_format
= ISL_FORMAT_R8_UNORM
;
2197 dst_format
= ISL_FORMAT_R8_UNORM
;
2201 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2202 src_layer
, src_format
, false);
2203 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2204 dst_layer
, dst_format
, true);
2206 params
.src
.view
.swizzle
= src_swizzle
;
2207 params
.dst
.view
.swizzle
= dst_swizzle
;
2209 struct brw_blorp_blit_prog_key wm_prog_key
= {
2210 .shader_type
= BLORP_SHADER_TYPE_BLIT
2213 /* Scaled blitting or not. */
2214 wm_prog_key
.blit_scaled
=
2215 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2216 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2218 /* Scaling factors used for bilinear filtering in multisample scaled
2221 if (params
.src
.surf
.samples
== 16)
2222 wm_prog_key
.x_scale
= 4.0f
;
2224 wm_prog_key
.x_scale
= 2.0f
;
2225 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2227 if (filter
== GL_LINEAR
&&
2228 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1) {
2229 wm_prog_key
.bilinear_filter
= true;
2232 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
2233 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
2234 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
2235 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
2236 /* We are downsampling a non-integer color buffer, so blend.
2238 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
2240 * "If the source formats are integer types or stencil values, a
2241 * single sample's value is selected for each pixel."
2243 * This implies we should not blend in that case.
2245 wm_prog_key
.blend
= true;
2248 params
.wm_inputs
.rect_grid
.x1
=
2249 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2250 wm_prog_key
.x_scale
- 1.0f
;
2251 params
.wm_inputs
.rect_grid
.y1
=
2252 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2253 wm_prog_key
.y_scale
- 1.0f
;
2255 struct blt_coords coords
= {
2272 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2275 static enum isl_format
2276 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2278 /* The choice of UNORM and UINT formats is very intentional here. Most
2279 * of the time, we want to use a UINT format to avoid any rounding error
2280 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2281 * (It's the only format allowed in conjunction with W-tiling.) Also we
2282 * intentionally use the 4-channel formats whenever we can. This is so
2283 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2284 * even though one of them is 3/4 the size of the other. The choice of
2285 * UNORM vs. UINT is also very intentional because we don't have 8 or
2286 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2287 * Fortunately, the only time we should ever use two different formats in
2288 * the table below is for RGB -> RGBA blits and so we will never have any
2289 * UNORM/UINT mismatch.
2291 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2293 case 8: return ISL_FORMAT_R8_UINT
;
2294 case 16: return ISL_FORMAT_R8G8_UINT
;
2295 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2296 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2297 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2298 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2299 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2300 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2302 unreachable("Unknown format bpb");
2306 case 8: return ISL_FORMAT_R8_UINT
;
2307 case 16: return ISL_FORMAT_R8G8_UINT
;
2308 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2309 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2310 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2311 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2312 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2313 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2315 unreachable("Unknown format bpb");
2320 /** Returns a UINT format that is CCS-compatible with the given format
2322 * The PRM's say absolutely nothing about how render compression works. The
2323 * only thing they provide is a list of formats on which it is and is not
2324 * supported. Empirical testing indicates that the compression is only based
2325 * on the bit-layout of the format and the channel encoding doesn't matter.
2326 * So, while texture views don't work in general, you can create a view as
2327 * long as the bit-layout of the formats are the same.
2329 * Fortunately, for every render compression capable format, the UINT format
2330 * with the same bit layout also supports render compression. This means that
2331 * we only need to handle UINT formats for copy operations. In order to do
2332 * copies between formats with different bit layouts, we attach both with a
2333 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2334 * operation between the two bit layouts.
2336 static enum isl_format
2337 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2339 switch (fmtl
->format
) {
2340 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2341 case ISL_FORMAT_R32G32B32A32_SINT
:
2342 case ISL_FORMAT_R32G32B32A32_UINT
:
2343 case ISL_FORMAT_R32G32B32A32_UNORM
:
2344 case ISL_FORMAT_R32G32B32A32_SNORM
:
2345 case ISL_FORMAT_R32G32B32X32_FLOAT
:
2346 return ISL_FORMAT_R32G32B32A32_UINT
;
2348 case ISL_FORMAT_R16G16B16A16_UNORM
:
2349 case ISL_FORMAT_R16G16B16A16_SNORM
:
2350 case ISL_FORMAT_R16G16B16A16_SINT
:
2351 case ISL_FORMAT_R16G16B16A16_UINT
:
2352 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2353 case ISL_FORMAT_R16G16B16X16_UNORM
:
2354 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2355 return ISL_FORMAT_R16G16B16A16_UINT
;
2357 case ISL_FORMAT_R32G32_FLOAT
:
2358 case ISL_FORMAT_R32G32_SINT
:
2359 case ISL_FORMAT_R32G32_UINT
:
2360 case ISL_FORMAT_R32G32_UNORM
:
2361 case ISL_FORMAT_R32G32_SNORM
:
2362 return ISL_FORMAT_R32G32_UINT
;
2364 case ISL_FORMAT_B8G8R8A8_UNORM
:
2365 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2366 case ISL_FORMAT_R8G8B8A8_UNORM
:
2367 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2368 case ISL_FORMAT_R8G8B8A8_SNORM
:
2369 case ISL_FORMAT_R8G8B8A8_SINT
:
2370 case ISL_FORMAT_R8G8B8A8_UINT
:
2371 case ISL_FORMAT_B8G8R8X8_UNORM
:
2372 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2373 case ISL_FORMAT_R8G8B8X8_UNORM
:
2374 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2375 return ISL_FORMAT_R8G8B8A8_UINT
;
2377 case ISL_FORMAT_R16G16_UNORM
:
2378 case ISL_FORMAT_R16G16_SNORM
:
2379 case ISL_FORMAT_R16G16_SINT
:
2380 case ISL_FORMAT_R16G16_UINT
:
2381 case ISL_FORMAT_R16G16_FLOAT
:
2382 return ISL_FORMAT_R16G16_UINT
;
2384 case ISL_FORMAT_R32_SINT
:
2385 case ISL_FORMAT_R32_UINT
:
2386 case ISL_FORMAT_R32_FLOAT
:
2387 case ISL_FORMAT_R32_UNORM
:
2388 case ISL_FORMAT_R32_SNORM
:
2389 return ISL_FORMAT_R32_UINT
;
2392 unreachable("Not a compressible format");
2397 blorp_surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2398 struct brw_blorp_surface_info
*info
,
2399 uint32_t *x
, uint32_t *y
,
2400 uint32_t *width
, uint32_t *height
)
2402 const struct isl_format_layout
*fmtl
=
2403 isl_format_get_layout(info
->surf
.format
);
2405 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2407 /* This is a compressed surface. We need to convert it to a single
2408 * slice (because compressed layouts don't perfectly match uncompressed
2409 * ones with the same bpb) and divide x, y, width, and height by the
2412 blorp_surf_convert_to_single_slice(isl_dev
, info
);
2414 if (width
&& height
) {
2416 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2417 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2418 assert(*width
% fmtl
->bw
== 0 ||
2419 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2420 assert(*height
% fmtl
->bh
== 0 ||
2421 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2423 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2424 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2428 assert(*x
% fmtl
->bw
== 0);
2429 assert(*y
% fmtl
->bh
== 0);
2434 info
->surf
.logical_level0_px
.width
=
2435 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
2436 info
->surf
.logical_level0_px
.height
=
2437 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
2439 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
2440 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
2441 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2442 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2444 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2445 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2446 info
->tile_x_sa
/= fmtl
->bw
;
2447 info
->tile_y_sa
/= fmtl
->bh
;
2449 /* It's now an uncompressed surface so we need an uncompressed format */
2450 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2454 blorp_copy(struct blorp_batch
*batch
,
2455 const struct blorp_surf
*src_surf
,
2456 unsigned src_level
, unsigned src_layer
,
2457 const struct blorp_surf
*dst_surf
,
2458 unsigned dst_level
, unsigned dst_layer
,
2459 uint32_t src_x
, uint32_t src_y
,
2460 uint32_t dst_x
, uint32_t dst_y
,
2461 uint32_t src_width
, uint32_t src_height
)
2463 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2464 struct blorp_params params
;
2466 if (src_width
== 0 || src_height
== 0)
2469 blorp_params_init(¶ms
);
2470 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2471 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2472 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2473 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2475 struct brw_blorp_blit_prog_key wm_prog_key
= {
2476 .shader_type
= BLORP_SHADER_TYPE_BLIT
2479 const struct isl_format_layout
*src_fmtl
=
2480 isl_format_get_layout(params
.src
.surf
.format
);
2481 const struct isl_format_layout
*dst_fmtl
=
2482 isl_format_get_layout(params
.dst
.surf
.format
);
2484 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2485 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2486 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2487 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2488 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2489 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2491 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2492 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2493 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2494 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2495 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2496 params
.src
.view
.format
= params
.dst
.view
.format
;
2498 params
.src
.view
.format
=
2499 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2501 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2502 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2503 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2504 params
.dst
.view
.format
= params
.src
.view
.format
;
2506 params
.dst
.view
.format
=
2507 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2510 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2511 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2514 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2515 /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
2516 * enabled even though CCS_E doesn't technically do sRGB on SKL because
2517 * we stomp everything to UINT anyway. The one thing we have to be
2518 * careful of is clear colors. Because fast clear colors for sRGB on
2519 * gen9 are encoded as the float values between format conversion and
2520 * sRGB curve application, a given clear color float will convert to the
2521 * same bits regardless of whether the format is UNORM or sRGB.
2522 * Therefore, we can handle sRGB without any special cases.
2524 UNUSED
enum isl_format linear_src_format
=
2525 isl_format_srgb_to_linear(src_surf
->surf
->format
);
2526 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2528 params
.src
.view
.format
));
2530 isl_color_value_pack(¶ms
.src
.clear_color
,
2531 params
.src
.surf
.format
, packed
);
2532 isl_color_value_unpack(¶ms
.src
.clear_color
,
2533 params
.src
.view
.format
, packed
);
2536 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2537 /* See above where we handle linear_src_format */
2538 UNUSED
enum isl_format linear_dst_format
=
2539 isl_format_srgb_to_linear(dst_surf
->surf
->format
);
2540 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2542 params
.dst
.view
.format
));
2544 isl_color_value_pack(¶ms
.dst
.clear_color
,
2545 params
.dst
.surf
.format
, packed
);
2546 isl_color_value_unpack(¶ms
.dst
.clear_color
,
2547 params
.dst
.view
.format
, packed
);
2550 wm_prog_key
.src_bpc
=
2551 isl_format_get_layout(params
.src
.view
.format
)->channels
.r
.bits
;
2552 wm_prog_key
.dst_bpc
=
2553 isl_format_get_layout(params
.dst
.view
.format
)->channels
.r
.bits
;
2555 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2556 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2558 &src_width
, &src_height
);
2559 wm_prog_key
.need_src_offset
= true;
2562 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2563 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2564 &dst_x
, &dst_y
, NULL
, NULL
);
2565 wm_prog_key
.need_dst_offset
= true;
2568 /* Once both surfaces are stompped to uncompressed as needed, the
2569 * destination size is the same as the source size.
2571 uint32_t dst_width
= src_width
;
2572 uint32_t dst_height
= src_height
;
2574 struct blt_coords coords
= {
2577 .src1
= src_x
+ src_width
,
2579 .dst1
= dst_x
+ dst_width
,
2584 .src1
= src_y
+ src_height
,
2586 .dst1
= dst_y
+ dst_height
,
2591 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2594 static enum isl_format
2595 isl_format_for_size(unsigned size_B
)
2598 case 1: return ISL_FORMAT_R8_UINT
;
2599 case 2: return ISL_FORMAT_R8G8_UINT
;
2600 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
2601 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
2602 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
2604 unreachable("Not a power-of-two format size");
2609 * Returns the greatest common divisor of a and b that is a power of two.
2612 gcd_pow2_u64(uint64_t a
, uint64_t b
)
2614 assert(a
> 0 || b
> 0);
2616 unsigned a_log2
= ffsll(a
) - 1;
2617 unsigned b_log2
= ffsll(b
) - 1;
2619 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
2620 * case, the MIN2() will take the other one. If both are 0 then we will
2621 * hit the assert above.
2623 return 1 << MIN2(a_log2
, b_log2
);
2627 do_buffer_copy(struct blorp_batch
*batch
,
2628 struct blorp_address
*src
,
2629 struct blorp_address
*dst
,
2630 int width
, int height
, int block_size
)
2632 /* The actual format we pick doesn't matter as blorp will throw it away.
2633 * The only thing that actually matters is the size.
2635 enum isl_format format
= isl_format_for_size(block_size
);
2638 struct isl_surf surf
;
2639 ok
= isl_surf_init(batch
->blorp
->isl_dev
, &surf
,
2640 .dim
= ISL_SURF_DIM_2D
,
2648 .row_pitch
= width
* block_size
,
2649 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
2650 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
2651 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
2654 struct blorp_surf src_blorp_surf
= {
2659 struct blorp_surf dst_blorp_surf
= {
2664 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
2665 0, 0, 0, 0, width
, height
);
2669 blorp_buffer_copy(struct blorp_batch
*batch
,
2670 struct blorp_address src
,
2671 struct blorp_address dst
,
2674 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
2675 uint64_t copy_size
= size
;
2677 /* This is maximum possible width/height our HW can handle */
2678 uint64_t max_surface_dim
= 1 << (devinfo
->gen
>= 7 ? 14 : 13);
2680 /* First, we compute the biggest format that can be used with the
2681 * given offsets and size.
2684 bs
= gcd_pow2_u64(bs
, src
.offset
);
2685 bs
= gcd_pow2_u64(bs
, dst
.offset
);
2686 bs
= gcd_pow2_u64(bs
, size
);
2688 /* First, we make a bunch of max-sized copies */
2689 uint64_t max_copy_size
= max_surface_dim
* max_surface_dim
* bs
;
2690 while (copy_size
>= max_copy_size
) {
2691 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, max_surface_dim
, bs
);
2692 copy_size
-= max_copy_size
;
2693 src
.offset
+= max_copy_size
;
2694 dst
.offset
+= max_copy_size
;
2697 /* Now make a max-width copy */
2698 uint64_t height
= copy_size
/ (max_surface_dim
* bs
);
2699 assert(height
< max_surface_dim
);
2701 uint64_t rect_copy_size
= height
* max_surface_dim
* bs
;
2702 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, height
, bs
);
2703 copy_size
-= rect_copy_size
;
2704 src
.offset
+= rect_copy_size
;
2705 dst
.offset
+= rect_copy_size
;
2708 /* Finally, make a small copy to finish it off */
2709 if (copy_size
!= 0) {
2710 do_buffer_copy(batch
, &src
, &dst
, copy_size
/ bs
, 1, bs
);