2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "blorp_nir_builder.h"
25 #include "compiler/nir/nir_format_convert.h"
27 #include "blorp_priv.h"
29 #include "util/format_rgb9e5.h"
30 /* header-only include needed for _mesa_unorm_to_float and friends. */
31 #include "mesa/main/format_utils.h"
32 #include "util/u_math.h"
34 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 static const bool split_blorp_blit_debug
= false;
39 * Enum to specify the order of arguments in a sampler message
41 enum sampler_message_arg
43 SAMPLER_MESSAGE_ARG_U_FLOAT
,
44 SAMPLER_MESSAGE_ARG_V_FLOAT
,
45 SAMPLER_MESSAGE_ARG_U_INT
,
46 SAMPLER_MESSAGE_ARG_V_INT
,
47 SAMPLER_MESSAGE_ARG_R_INT
,
48 SAMPLER_MESSAGE_ARG_SI_INT
,
49 SAMPLER_MESSAGE_ARG_MCS_INT
,
50 SAMPLER_MESSAGE_ARG_ZERO_INT
,
53 struct brw_blorp_blit_vars
{
54 /* Input values from brw_blorp_wm_inputs */
55 nir_variable
*v_discard_rect
;
56 nir_variable
*v_rect_grid
;
57 nir_variable
*v_coord_transform
;
58 nir_variable
*v_src_z
;
59 nir_variable
*v_src_offset
;
60 nir_variable
*v_dst_offset
;
61 nir_variable
*v_src_inv_size
;
65 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
66 const struct brw_blorp_blit_prog_key
*key
)
68 #define LOAD_INPUT(name, type)\
69 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
71 LOAD_INPUT(discard_rect
, glsl_vec4_type())
72 LOAD_INPUT(rect_grid
, glsl_vec4_type())
73 LOAD_INPUT(coord_transform
, glsl_vec4_type())
74 LOAD_INPUT(src_z
, glsl_uint_type())
75 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
76 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
77 LOAD_INPUT(src_inv_size
, glsl_vector_type(GLSL_TYPE_FLOAT
, 2))
83 blorp_blit_get_frag_coords(nir_builder
*b
,
84 const struct brw_blorp_blit_prog_key
*key
,
85 struct brw_blorp_blit_vars
*v
)
87 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_frag_coord(b
));
89 /* Account for destination surface intratile offset
91 * Transformation parameters giving translation from destination to source
92 * coordinates don't take into account possible intra-tile destination
93 * offset. Therefore it has to be first subtracted from the incoming
94 * coordinates. Vertices are set up based on coordinates containing the
97 if (key
->need_dst_offset
)
98 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
100 if (key
->persample_msaa_dispatch
) {
101 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
102 nir_load_sample_id(b
));
104 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
109 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
113 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
114 struct brw_blorp_blit_vars
*v
)
116 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
118 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
119 nir_channel(b
, coord_transform
, 3));
120 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
121 nir_channel(b
, coord_transform
, 2));
123 return nir_fadd(b
, nir_fmul(b
, src_pos
, mul
), offset
);
127 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
128 struct brw_blorp_blit_vars
*v
)
130 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
131 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
132 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
133 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
134 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
135 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
137 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
138 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
139 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
140 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
142 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
144 nir_intrinsic_instr
*discard
=
145 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
146 discard
->src
[0] = nir_src_for_ssa(oob
);
147 nir_builder_instr_insert(b
, &discard
->instr
);
150 static nir_tex_instr
*
151 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
152 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
153 nir_alu_type dst_type
)
155 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
159 tex
->dest_type
= dst_type
;
160 tex
->is_array
= false;
161 tex
->is_shadow
= false;
163 /* Blorp only has one texture and it's bound at unit 0 */
164 tex
->texture_index
= 0;
165 tex
->sampler_index
= 0;
167 /* To properly handle 3-D and 2-D array textures, we pull the Z component
168 * from an input. TODO: This is a bit magic; we should probably make this
169 * more explicit in the future.
171 assert(pos
->num_components
>= 2);
172 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
173 nir_load_var(b
, v
->v_src_z
));
175 tex
->src
[0].src_type
= nir_tex_src_coord
;
176 tex
->src
[0].src
= nir_src_for_ssa(pos
);
177 tex
->coord_components
= 3;
179 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
185 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
186 const struct brw_blorp_blit_prog_key
*key
, nir_ssa_def
*pos
)
188 if (key
->need_src_offset
)
189 pos
= nir_fadd(b
, pos
, nir_i2f32(b
, nir_load_var(b
, v
->v_src_offset
)));
191 /* If the sampler requires normalized coordinates, we need to compensate. */
192 if (key
->src_coords_normalized
)
193 pos
= nir_fmul(b
, pos
, nir_load_var(b
, v
->v_src_inv_size
));
196 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2,
197 key
->texture_data_type
);
199 assert(pos
->num_components
== 2);
200 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
201 tex
->src
[1].src_type
= nir_tex_src_lod
;
202 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
204 nir_builder_instr_insert(b
, &tex
->instr
);
206 return &tex
->dest
.ssa
;
210 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
211 nir_ssa_def
*pos
, nir_alu_type dst_type
)
214 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
216 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
217 tex
->src
[1].src_type
= nir_tex_src_lod
;
218 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
220 nir_builder_instr_insert(b
, &tex
->instr
);
222 return &tex
->dest
.ssa
;
226 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
227 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
230 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
231 mcs
!= NULL
? 3 : 2, dst_type
);
233 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
235 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
236 if (pos
->num_components
== 2) {
237 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
239 assert(pos
->num_components
== 3);
240 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
244 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
245 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
248 nir_builder_instr_insert(b
, &tex
->instr
);
250 return &tex
->dest
.ssa
;
254 blorp_blit_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
258 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
259 pos
, 1, nir_type_int
);
261 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
263 nir_builder_instr_insert(b
, &tex
->instr
);
265 return &tex
->dest
.ssa
;
269 * Emit code to compensate for the difference between Y and W tiling.
271 * This code modifies the X and Y coordinates according to the formula:
273 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
275 * (See brw_blorp_build_nir_shader).
277 static inline nir_ssa_def
*
278 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
280 assert(pos
->num_components
== 2);
281 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
282 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
284 /* Given X and Y coordinates that describe an address using Y tiling,
285 * translate to the X and Y coordinates that describe the same address
288 * If we break down the low order bits of X and Y, using a
289 * single letter to represent each low-order bit:
291 * X = A << 7 | 0bBCDEFGH
292 * Y = J << 5 | 0bKLMNP (1)
294 * Then we can apply the Y tiling formula to see the memory offset being
297 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
299 * If we apply the W detiling formula to this memory location, that the
300 * corresponding X' and Y' coordinates are:
302 * X' = A << 6 | 0bBCDPFH (3)
303 * Y' = J << 6 | 0bKLMNEG
305 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
306 * we need to make the following computation:
308 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
309 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
311 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
312 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
313 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
314 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
316 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
317 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
318 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
319 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
321 return nir_vec2(b
, x_W
, y_W
);
325 * Emit code to compensate for the difference between Y and W tiling.
327 * This code modifies the X and Y coordinates according to the formula:
329 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
331 * (See brw_blorp_build_nir_shader).
333 static inline nir_ssa_def
*
334 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
336 assert(pos
->num_components
== 2);
337 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
338 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
340 /* Applying the same logic as above, but in reverse, we obtain the
343 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
344 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
346 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
347 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
348 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
349 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
350 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
352 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
353 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
354 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
356 return nir_vec2(b
, x_Y
, y_Y
);
360 * Emit code to compensate for the difference between MSAA and non-MSAA
363 * This code modifies the X and Y coordinates according to the formula:
365 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
367 * (See brw_blorp_blit_program).
369 static inline nir_ssa_def
*
370 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
371 unsigned num_samples
, enum isl_msaa_layout layout
)
373 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
376 case ISL_MSAA_LAYOUT_NONE
:
377 assert(pos
->num_components
== 2);
379 case ISL_MSAA_LAYOUT_ARRAY
:
380 /* No translation needed */
382 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
383 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
384 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
385 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
386 nir_channel(b
, pos
, 2);
388 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
389 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
390 switch (num_samples
) {
393 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
394 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
397 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
398 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
399 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
401 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
402 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
403 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
404 if (num_samples
== 2) {
407 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
408 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
409 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
414 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
415 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
417 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
419 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
420 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
421 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
422 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
423 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
424 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
425 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
429 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
430 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
432 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
435 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
436 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
437 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
438 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
439 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
440 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
441 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
442 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
446 unreachable("Invalid number of samples for IMS layout");
449 return nir_vec2(b
, x_out
, y_out
);
453 unreachable("Invalid MSAA layout");
458 * Emit code to compensate for the difference between MSAA and non-MSAA
461 * This code modifies the X and Y coordinates according to the formula:
463 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
465 * (See brw_blorp_blit_program).
467 static inline nir_ssa_def
*
468 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
469 unsigned num_samples
, enum isl_msaa_layout layout
)
471 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
474 case ISL_MSAA_LAYOUT_NONE
:
475 /* No translation necessary, and S should already be zero. */
476 assert(pos
->num_components
== 2);
478 case ISL_MSAA_LAYOUT_ARRAY
:
479 /* No translation necessary. */
481 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
482 assert(pos
->num_components
== 2);
484 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
485 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
487 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
488 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
489 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
490 switch (num_samples
) {
493 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
494 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
495 * S = (X & 0b10) >> 1
497 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
498 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
499 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
500 * S = (Y & 0b10) | (X & 0b10) >> 1
502 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
503 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
504 if (num_samples
== 2) {
506 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
508 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
509 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
510 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
511 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
516 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
517 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
518 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
519 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
521 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
522 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
523 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
524 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
525 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
526 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
527 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
531 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
532 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
533 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
534 * S = (Y & 0b100) << 1 | (X & 0b100) |
535 * (Y & 0b10) | (X & 0b10) >> 1
537 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
538 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
539 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
540 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
541 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
542 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
543 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
544 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
548 unreachable("Invalid number of samples for IMS layout");
551 return nir_vec3(b
, x_out
, y_out
, s_out
);
555 unreachable("Invalid MSAA layout");
560 * Count the number of trailing 1 bits in the given value. For example:
562 * count_trailing_one_bits(0) == 0
563 * count_trailing_one_bits(7) == 3
564 * count_trailing_one_bits(11) == 2
566 static inline int count_trailing_one_bits(unsigned value
)
568 #ifdef HAVE___BUILTIN_CTZ
569 return __builtin_ctz(~value
);
571 return util_bitcount(value
& ~(value
+ 1));
576 blorp_nir_combine_samples(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
577 nir_ssa_def
*pos
, unsigned tex_samples
,
578 enum isl_aux_usage tex_aux_usage
,
579 nir_alu_type dst_type
,
580 enum blorp_filter filter
)
582 /* If non-null, this is the outer-most if statement */
583 nir_if
*outer_if
= NULL
;
585 nir_variable
*color
=
586 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
588 nir_ssa_def
*mcs
= NULL
;
589 if (isl_aux_usage_has_mcs(tex_aux_usage
))
590 mcs
= blorp_blit_txf_ms_mcs(b
, v
, pos
);
594 case BLORP_FILTER_AVERAGE
:
595 assert(dst_type
== nir_type_float
);
596 combine_op
= nir_op_fadd
;
599 case BLORP_FILTER_MIN_SAMPLE
:
601 case nir_type_int
: combine_op
= nir_op_imin
; break;
602 case nir_type_uint
: combine_op
= nir_op_umin
; break;
603 case nir_type_float
: combine_op
= nir_op_fmin
; break;
604 default: unreachable("Invalid dst_type");
608 case BLORP_FILTER_MAX_SAMPLE
:
610 case nir_type_int
: combine_op
= nir_op_imax
; break;
611 case nir_type_uint
: combine_op
= nir_op_umax
; break;
612 case nir_type_float
: combine_op
= nir_op_fmax
; break;
613 default: unreachable("Invalid dst_type");
618 unreachable("Invalid filter");
621 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
623 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
625 * This ensures that when all samples have the same value, no numerical
626 * precision is lost, since each addition operation always adds two equal
627 * values, and summing two equal floating point values does not lose
630 * We perform this computation by treating the texture_data array as a
631 * stack and performing the following operations:
633 * - push sample 0 onto stack
634 * - push sample 1 onto stack
635 * - add top two stack entries
636 * - push sample 2 onto stack
637 * - push sample 3 onto stack
638 * - add top two stack entries
639 * - add top two stack entries
640 * - divide top stack entry by 4
642 * Note that after pushing sample i onto the stack, the number of add
643 * operations we do is equal to the number of trailing 1 bits in i. This
644 * works provided the total number of samples is a power of two, which it
645 * always is for i965.
647 * For integer formats, we replace the add operations with average
648 * operations and skip the final division.
650 nir_ssa_def
*texture_data
[5];
651 unsigned stack_depth
= 0;
652 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
653 assert(stack_depth
== util_bitcount(i
)); /* Loop invariant */
655 /* Push sample i onto the stack */
656 assert(stack_depth
< ARRAY_SIZE(texture_data
));
658 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
659 nir_channel(b
, pos
, 1),
661 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
663 if (i
== 0 && isl_aux_usage_has_mcs(tex_aux_usage
)) {
664 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
665 * suggests an optimization:
667 * "A simple optimization with probable large return in
668 * performance is to compare the MCS value to zero (indicating
669 * all samples are on sample slice 0), and sample only from
670 * sample slice 0 using ld2dss if MCS is zero."
672 * Note that in the case where the MCS value is zero, sampling from
673 * sample slice 0 using ld2dss and sampling from sample 0 using
674 * ld2dms are equivalent (since all samples are on sample slice 0).
675 * Since we have already sampled from sample 0, all we need to do is
676 * skip the remaining fetches and averaging if MCS is zero.
678 * It's also trivial to detect when the MCS has the magic clear color
679 * value. In this case, the txf we did on sample 0 will return the
680 * clear color and we can skip the remaining fetches just like we do
683 nir_ssa_def
*mcs_zero
=
684 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
685 if (tex_samples
== 16) {
686 mcs_zero
= nir_iand(b
, mcs_zero
,
687 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
689 nir_ssa_def
*mcs_clear
=
690 blorp_nir_mcs_is_clear_color(b
, mcs
, tex_samples
);
692 nir_if
*if_stmt
= nir_if_create(b
->shader
);
693 if_stmt
->condition
= nir_src_for_ssa(nir_ior(b
, mcs_zero
, mcs_clear
));
694 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
696 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
697 nir_store_var(b
, color
, texture_data
[0], 0xf);
699 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
703 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
704 assert(stack_depth
>= 2);
707 texture_data
[stack_depth
- 1] =
708 nir_build_alu(b
, combine_op
,
709 texture_data
[stack_depth
- 1],
710 texture_data
[stack_depth
],
715 /* We should have just 1 sample on the stack now. */
716 assert(stack_depth
== 1);
718 if (filter
== BLORP_FILTER_AVERAGE
) {
719 assert(dst_type
== nir_type_float
);
720 texture_data
[0] = nir_fmul(b
, texture_data
[0],
721 nir_imm_float(b
, 1.0 / tex_samples
));
724 nir_store_var(b
, color
, texture_data
[0], 0xf);
727 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
729 return nir_load_var(b
, color
);
733 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
734 unsigned tex_samples
,
735 const struct brw_blorp_blit_prog_key
*key
,
736 struct brw_blorp_blit_vars
*v
)
738 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
739 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
740 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
742 /* Translate coordinates to lay out the samples in a rectangular grid
743 * roughly corresponding to sample locations.
745 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
746 /* Adjust coordinates so that integers represent pixel centers rather
749 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
750 /* Clamp the X, Y texture coordinates to properly handle the sampling of
751 * texels on texture edges.
753 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
754 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
755 nir_channel(b
, rect_grid
, 1)));
757 /* Store the fractional parts to be used as bilinear interpolation
760 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
761 /* Round the float coordinates down to nearest integer */
762 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
764 nir_ssa_def
*tex_data
[4];
765 for (unsigned i
= 0; i
< 4; ++i
) {
766 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
767 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
768 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
770 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
771 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
773 /* The MCS value we fetch has to match up with the pixel that we're
774 * sampling from. Since we sample from different pixels in each
775 * iteration of this "for" loop, the call to mcs_fetch() should be
776 * here inside the loop after computing the pixel coordinates.
778 nir_ssa_def
*mcs
= NULL
;
779 if (isl_aux_usage_has_mcs(key
->tex_aux_usage
))
780 mcs
= blorp_blit_txf_ms_mcs(b
, v
, sample_coords_int
);
782 /* Compute sample index and map the sample index to a sample number.
783 * Sample index layout shows the numbering of slots in a rectangular
784 * grid of samples with in a pixel. Sample number layout shows the
785 * rectangular grid of samples roughly corresponding to the real sample
786 * locations with in a pixel.
788 * In the case of 2x MSAA, the layout of sample indices is reversed from
789 * the layout of sample numbers:
791 * sample index layout : --------- sample number layout : ---------
792 * | 0 | 1 | | 1 | 0 |
793 * --------- ---------
795 * In case of 4x MSAA, layout of sample indices matches the layout of
803 * In case of 8x MSAA the two layouts don't match.
804 * sample index layout : --------- sample number layout : ---------
805 * | 0 | 1 | | 3 | 7 |
806 * --------- ---------
807 * | 2 | 3 | | 5 | 0 |
808 * --------- ---------
809 * | 4 | 5 | | 1 | 2 |
810 * --------- ---------
811 * | 6 | 7 | | 4 | 6 |
812 * --------- ---------
814 * Fortunately, this can be done fairly easily as:
815 * S' = (0x17306425 >> (S * 4)) & 0xf
817 * In the case of 16x MSAA the two layouts don't match.
818 * Sample index layout: Sample number layout:
819 * --------------------- ---------------------
820 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
821 * --------------------- ---------------------
822 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
823 * --------------------- ---------------------
824 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
825 * --------------------- ---------------------
826 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
827 * --------------------- ---------------------
829 * This is equivalent to
830 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
832 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
833 nir_ssa_def
*sample
=
834 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
835 key
->x_scale
* key
->y_scale
));
836 sample
= nir_f2i32(b
, sample
);
838 if (tex_samples
== 2) {
839 sample
= nir_isub(b
, nir_imm_int(b
, 1), sample
);
840 } else if (tex_samples
== 8) {
841 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
842 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
843 nir_imm_int(b
, 0xf));
844 } else if (tex_samples
== 16) {
845 nir_ssa_def
*sample_low
=
846 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
847 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
848 nir_imm_int(b
, 0xf));
849 nir_ssa_def
*sample_high
=
850 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
851 nir_ishl(b
, nir_iadd(b
, sample
,
854 nir_imm_int(b
, 0xf));
856 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
857 sample_low
, sample_high
);
859 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
860 nir_channel(b
, sample_coords_int
, 1),
862 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
865 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
866 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
867 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
868 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
872 /** Perform a color bit-cast operation
874 * For copy operations involving CCS, we may need to use different formats for
875 * the source and destination surfaces. The two formats must both be UINT
876 * formats and must have the same size but may have different bit layouts.
877 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
878 * to R16G16_UINT. This function generates code to shuffle bits around to get
879 * us from one to the other.
882 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
883 const struct brw_blorp_blit_prog_key
*key
)
885 if (key
->src_format
== key
->dst_format
)
888 const struct isl_format_layout
*src_fmtl
=
889 isl_format_get_layout(key
->src_format
);
890 const struct isl_format_layout
*dst_fmtl
=
891 isl_format_get_layout(key
->dst_format
);
893 /* They must be formats with the same bit size */
894 assert(src_fmtl
->bpb
== dst_fmtl
->bpb
);
896 if (src_fmtl
->bpb
<= 32) {
897 assert(src_fmtl
->channels
.r
.type
== ISL_UINT
||
898 src_fmtl
->channels
.r
.type
== ISL_UNORM
);
899 assert(dst_fmtl
->channels
.r
.type
== ISL_UINT
||
900 dst_fmtl
->channels
.r
.type
== ISL_UNORM
);
902 nir_ssa_def
*packed
= nir_imm_int(b
, 0);
903 for (unsigned c
= 0; c
< 4; c
++) {
904 if (src_fmtl
->channels_array
[c
].bits
== 0)
907 const unsigned chan_start_bit
= src_fmtl
->channels_array
[c
].start_bit
;
908 const unsigned chan_bits
= src_fmtl
->channels_array
[c
].bits
;
910 nir_ssa_def
*chan
= nir_channel(b
, color
, c
);
911 if (src_fmtl
->channels_array
[c
].type
== ISL_UNORM
)
912 chan
= nir_format_float_to_unorm(b
, chan
, &chan_bits
);
914 packed
= nir_ior(b
, packed
, nir_shift(b
, chan
, chan_start_bit
));
917 nir_ssa_def
*chans
[4] = { };
918 for (unsigned c
= 0; c
< 4; c
++) {
919 if (dst_fmtl
->channels_array
[c
].bits
== 0) {
920 chans
[c
] = nir_imm_int(b
, 0);
924 const unsigned chan_start_bit
= dst_fmtl
->channels_array
[c
].start_bit
;
925 const unsigned chan_bits
= dst_fmtl
->channels_array
[c
].bits
;
926 chans
[c
] = nir_iand(b
, nir_shift(b
, packed
, -(int)chan_start_bit
),
927 nir_imm_int(b
, BITFIELD_MASK(chan_bits
)));
929 if (dst_fmtl
->channels_array
[c
].type
== ISL_UNORM
)
930 chans
[c
] = nir_format_unorm_to_float(b
, chans
[c
], &chan_bits
);
932 color
= nir_vec(b
, chans
, 4);
934 /* This path only supports UINT formats */
935 assert(src_fmtl
->channels
.r
.type
== ISL_UINT
);
936 assert(dst_fmtl
->channels
.r
.type
== ISL_UINT
);
938 const unsigned src_bpc
= src_fmtl
->channels
.r
.bits
;
939 const unsigned dst_bpc
= dst_fmtl
->channels
.r
.bits
;
941 assert(src_fmtl
->channels
.g
.bits
== 0 ||
942 src_fmtl
->channels
.g
.bits
== src_fmtl
->channels
.r
.bits
);
943 assert(src_fmtl
->channels
.b
.bits
== 0 ||
944 src_fmtl
->channels
.b
.bits
== src_fmtl
->channels
.r
.bits
);
945 assert(src_fmtl
->channels
.a
.bits
== 0 ||
946 src_fmtl
->channels
.a
.bits
== src_fmtl
->channels
.r
.bits
);
947 assert(dst_fmtl
->channels
.g
.bits
== 0 ||
948 dst_fmtl
->channels
.g
.bits
== dst_fmtl
->channels
.r
.bits
);
949 assert(dst_fmtl
->channels
.b
.bits
== 0 ||
950 dst_fmtl
->channels
.b
.bits
== dst_fmtl
->channels
.r
.bits
);
951 assert(dst_fmtl
->channels
.a
.bits
== 0 ||
952 dst_fmtl
->channels
.a
.bits
== dst_fmtl
->channels
.r
.bits
);
954 /* Restrict to only the channels we actually have */
955 const unsigned src_channels
=
956 isl_format_get_num_channels(key
->src_format
);
957 color
= nir_channels(b
, color
, (1 << src_channels
) - 1);
959 color
= nir_format_bitcast_uvec_unmasked(b
, color
, src_bpc
, dst_bpc
);
962 /* Blorp likes to assume that colors are vec4s */
963 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
964 nir_ssa_def
*chans
[4] = { u
, u
, u
, u
};
965 for (unsigned i
= 0; i
< color
->num_components
; i
++)
966 chans
[i
] = nir_channel(b
, color
, i
);
967 return nir_vec4(b
, chans
[0], chans
[1], chans
[2], chans
[3]);
971 select_color_channel(struct nir_builder
*b
, nir_ssa_def
*color
,
972 nir_alu_type data_type
,
973 enum isl_channel_select chan
)
975 if (chan
== ISL_CHANNEL_SELECT_ZERO
) {
976 return nir_imm_int(b
, 0);
977 } else if (chan
== ISL_CHANNEL_SELECT_ONE
) {
981 return nir_imm_int(b
, 1);
983 return nir_imm_float(b
, 1);
985 unreachable("Invalid data type");
988 assert((unsigned)(chan
- ISL_CHANNEL_SELECT_RED
) < 4);
989 return nir_channel(b
, color
, chan
- ISL_CHANNEL_SELECT_RED
);
994 swizzle_color(struct nir_builder
*b
, nir_ssa_def
*color
,
995 struct isl_swizzle swizzle
, nir_alu_type data_type
)
998 select_color_channel(b
, color
, data_type
, swizzle
.r
),
999 select_color_channel(b
, color
, data_type
, swizzle
.g
),
1000 select_color_channel(b
, color
, data_type
, swizzle
.b
),
1001 select_color_channel(b
, color
, data_type
, swizzle
.a
));
1004 static nir_ssa_def
*
1005 convert_color(struct nir_builder
*b
, nir_ssa_def
*color
,
1006 const struct brw_blorp_blit_prog_key
*key
)
1008 /* All of our color conversions end up generating a single-channel color
1009 * value that we need to write out.
1013 if (key
->dst_format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
1014 /* The destination image is bound as R32_UINT but the data needs to be
1015 * in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and the
1016 * top 8 need to be zero. We can accomplish this by simply multiplying
1017 * by a factor to scale things down.
1019 unsigned factor
= (1 << 24) - 1;
1020 value
= nir_fsat(b
, nir_channel(b
, color
, 0));
1021 value
= nir_f2i32(b
, nir_fmul(b
, value
, nir_imm_float(b
, factor
)));
1022 } else if (key
->dst_format
== ISL_FORMAT_L8_UNORM_SRGB
) {
1023 value
= nir_format_linear_to_srgb(b
, nir_channel(b
, color
, 0));
1024 } else if (key
->dst_format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
) {
1025 value
= nir_format_linear_to_srgb(b
, color
);
1026 } else if (key
->dst_format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
1027 value
= nir_format_pack_r9g9b9e5(b
, color
);
1029 unreachable("Unsupported format conversion");
1032 nir_ssa_def
*out_comps
[4];
1033 for (unsigned i
= 0; i
< 4; i
++) {
1034 if (i
< value
->num_components
)
1035 out_comps
[i
] = nir_channel(b
, value
, i
);
1037 out_comps
[i
] = nir_ssa_undef(b
, 1, 32);
1039 return nir_vec(b
, out_comps
, 4);
1043 * Generator for WM programs used in BLORP blits.
1045 * The bulk of the work done by the WM program is to wrap and unwrap the
1046 * coordinate transformations used by the hardware to store surfaces in
1047 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
1048 * sample index for a multisampled surface) to a memory offset by the
1049 * following formulas:
1051 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
1052 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
1054 * For a single-sampled surface, or for a multisampled surface using
1055 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
1058 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1059 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1060 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1061 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1063 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1064 * embeds the sample number into bit 1 of the X and Y coordinates:
1066 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1067 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1068 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
1069 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1070 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1071 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1072 * S = (Y & 0b10) | (X & 0b10) >> 1
1074 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1075 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
1078 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1079 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
1080 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1081 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1082 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1083 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1084 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1086 * For X tiling, tile() combines together the low-order bits of the X and Y
1087 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
1088 * bytes wide and 8 rows high:
1090 * tile(x_tiled, X, Y, S) = A
1091 * where A = tile_num << 12 | offset
1092 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
1093 * offset = (Y' & 0b111) << 9
1094 * | (X & 0b111111111)
1096 * Y' = Y + S * qpitch
1097 * detile(x_tiled, A) = (X, Y, S)
1098 * where X = X' / cpp
1101 * Y' = (tile_num / tile_pitch) << 3
1102 * | (A & 0b111000000000) >> 9
1103 * X' = (tile_num % tile_pitch) << 9
1104 * | (A & 0b111111111)
1106 * (In all tiling formulas, cpp is the number of bytes occupied by a single
1107 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
1108 * to fill the width of the surface, and qpitch is the spacing (in rows)
1109 * between array slices).
1111 * For Y tiling, tile() combines together the low-order bits of the X and Y
1112 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
1113 * bytes wide and 32 rows high:
1115 * tile(y_tiled, X, Y, S) = A
1116 * where A = tile_num << 12 | offset
1117 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
1118 * offset = (X' & 0b1110000) << 5
1119 * | (Y' & 0b11111) << 4
1122 * Y' = Y + S * qpitch
1123 * detile(y_tiled, A) = (X, Y, S)
1124 * where X = X' / cpp
1127 * Y' = (tile_num / tile_pitch) << 5
1128 * | (A & 0b111110000) >> 4
1129 * X' = (tile_num % tile_pitch) << 7
1130 * | (A & 0b111000000000) >> 5
1133 * For W tiling, tile() combines together the low-order bits of the X and Y
1134 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1135 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1136 * buffers, which always have cpp = 1 and S=0):
1138 * tile(w_tiled, X, Y, S) = A
1139 * where A = tile_num << 12 | offset
1140 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1141 * offset = (X' & 0b111000) << 6
1142 * | (Y' & 0b111100) << 3
1143 * | (X' & 0b100) << 2
1144 * | (Y' & 0b10) << 2
1145 * | (X' & 0b10) << 1
1149 * Y' = Y + S * qpitch
1150 * detile(w_tiled, A) = (X, Y, S)
1151 * where X = X' / cpp = X'
1152 * Y = Y' % qpitch = Y'
1153 * S = Y / qpitch = 0
1154 * Y' = (tile_num / tile_pitch) << 6
1155 * | (A & 0b111100000) >> 3
1156 * | (A & 0b1000) >> 2
1158 * X' = (tile_num % tile_pitch) << 6
1159 * | (A & 0b111000000000) >> 6
1160 * | (A & 0b10000) >> 2
1161 * | (A & 0b100) >> 1
1164 * Finally, for a non-tiled surface, tile() simply combines together the X and
1165 * Y coordinates in the natural way:
1167 * tile(untiled, X, Y, S) = A
1168 * where A = Y * pitch + X'
1170 * Y' = Y + S * qpitch
1171 * detile(untiled, A) = (X, Y, S)
1172 * where X = X' / cpp
1178 * (In these formulas, pitch is the number of bytes occupied by a single row
1182 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1183 const struct brw_blorp_blit_prog_key
*key
)
1185 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1186 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1189 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1190 /* If the destination image is W tiled and multisampled, then the thread
1191 * must be dispatched once per sample, not once per pixel. This is
1192 * necessary because after conversion between W and Y tiling, there's no
1193 * guarantee that all samples corresponding to a single pixel will still
1196 assert(key
->persample_msaa_dispatch
);
1199 if (key
->persample_msaa_dispatch
) {
1200 /* It only makes sense to do persample dispatch if the render target is
1201 * configured as multisampled.
1203 assert(key
->rt_samples
> 0);
1206 /* Make sure layout is consistent with sample count */
1207 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1208 (key
->tex_samples
<= 1));
1209 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1210 (key
->rt_samples
<= 1));
1211 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1212 (key
->src_samples
<= 1));
1213 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1214 (key
->dst_samples
<= 1));
1217 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1219 struct brw_blorp_blit_vars v
;
1220 brw_blorp_blit_vars_init(&b
, &v
, key
);
1222 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1224 /* Render target and texture hardware don't support W tiling until Gen8. */
1225 const bool rt_tiled_w
= false;
1226 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1228 /* The address that data will be written to is determined by the
1229 * coordinates supplied to the WM thread and the tiling and sample count of
1230 * the render target, according to the formula:
1232 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1234 * If the actual tiling and sample count of the destination surface are not
1235 * the same as the configuration of the render target, then these
1236 * coordinates are wrong and we have to adjust them to compensate for the
1239 if (rt_tiled_w
!= key
->dst_tiled_w
||
1240 key
->rt_samples
!= key
->dst_samples
||
1241 key
->rt_layout
!= key
->dst_layout
) {
1242 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1244 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1245 if (rt_tiled_w
!= key
->dst_tiled_w
)
1246 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1247 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1248 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1252 nir_ssa_def
*comp
= NULL
;
1254 /* The destination image is bound as a red texture three times as wide
1255 * as the actual image. Our shader is effectively running one color
1256 * component at a time. We need to save off the component and adjust
1257 * the destination position.
1259 assert(dst_pos
->num_components
== 2);
1260 nir_ssa_def
*dst_x
= nir_channel(&b
, dst_pos
, 0);
1261 comp
= nir_umod(&b
, dst_x
, nir_imm_int(&b
, 3));
1262 dst_pos
= nir_vec2(&b
, nir_idiv(&b
, dst_x
, nir_imm_int(&b
, 3)),
1263 nir_channel(&b
, dst_pos
, 1));
1266 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1268 * That is: X, Y and S now contain the true coordinates and sample index of
1269 * the data that the WM thread should output.
1271 * If we need to kill pixels that are outside the destination rectangle,
1272 * now is the time to do it.
1275 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1277 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1278 if (dst_pos
->num_components
== 3) {
1279 /* The sample coordinate is an integer that we want left alone but
1280 * blorp_blit_apply_transform() blindly applies the transform to all
1281 * three coordinates. Grab the original sample index.
1283 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1284 nir_channel(&b
, src_pos
, 1),
1285 nir_channel(&b
, dst_pos
, 2));
1288 /* If the source image is not multisampled, then we want to fetch sample
1289 * number 0, because that's the only sample there is.
1291 if (key
->src_samples
== 1)
1292 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1294 /* X, Y, and S are now the coordinates of the pixel in the source image
1295 * that we want to texture from. Exception: if we are blending, then S is
1296 * irrelevant, because we are going to fetch all samples.
1298 switch (key
->filter
) {
1299 case BLORP_FILTER_NONE
:
1300 case BLORP_FILTER_NEAREST
:
1301 case BLORP_FILTER_SAMPLE_0
:
1302 /* We're going to use texelFetch, so we need integers */
1303 if (src_pos
->num_components
== 2) {
1304 src_pos
= nir_f2i32(&b
, src_pos
);
1306 assert(src_pos
->num_components
== 3);
1307 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1308 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1309 nir_channel(&b
, src_pos
, 2));
1312 /* We aren't blending, which means we just want to fetch a single
1313 * sample from the source surface. The address that we want to fetch
1314 * from is related to the X, Y and S values according to the formula:
1316 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1318 * If the actual tiling and sample count of the source surface are
1319 * not the same as the configuration of the texture, then we need to
1320 * adjust the coordinates to compensate for the difference.
1322 if (tex_tiled_w
!= key
->src_tiled_w
||
1323 key
->tex_samples
!= key
->src_samples
||
1324 key
->tex_layout
!= key
->src_layout
) {
1325 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1327 /* Now (X, Y, S) = detile(src_tiling, offset) */
1328 if (tex_tiled_w
!= key
->src_tiled_w
)
1329 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1330 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1331 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1335 if (key
->need_src_offset
)
1336 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1338 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1340 * In other words: X, Y, and S now contain values which, when passed to
1341 * the texturing unit, will cause data to be read from the correct
1342 * memory location. So we can fetch the texel now.
1344 if (key
->src_samples
== 1) {
1345 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1347 nir_ssa_def
*mcs
= NULL
;
1348 if (isl_aux_usage_has_mcs(key
->tex_aux_usage
))
1349 mcs
= blorp_blit_txf_ms_mcs(&b
, &v
, src_pos
);
1351 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1355 case BLORP_FILTER_BILINEAR
:
1356 assert(!key
->src_tiled_w
);
1357 assert(key
->tex_samples
== key
->src_samples
);
1358 assert(key
->tex_layout
== key
->src_layout
);
1360 if (key
->src_samples
== 1) {
1361 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1363 assert(!key
->use_kill
);
1364 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
,
1369 case BLORP_FILTER_AVERAGE
:
1370 case BLORP_FILTER_MIN_SAMPLE
:
1371 case BLORP_FILTER_MAX_SAMPLE
:
1372 assert(!key
->src_tiled_w
);
1373 assert(key
->tex_samples
== key
->src_samples
);
1374 assert(key
->tex_layout
== key
->src_layout
);
1376 /* Resolves (effecively) use texelFetch, so we need integers and we
1377 * don't care about the sample index if we got one.
1379 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1381 if (devinfo
->gen
== 6) {
1382 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1383 * blending we need with a single linear-interpolated texture lookup
1384 * at the center of the sample. The texture coordinates to be odd
1385 * integers so that they correspond to the center of a 2x2 block
1386 * representing the four samples that maxe up a pixel. So we need
1387 * to multiply our X and Y coordinates each by 2 and then add 1.
1389 assert(key
->src_coords_normalized
);
1390 assert(key
->filter
== BLORP_FILTER_AVERAGE
);
1391 src_pos
= nir_fadd(&b
,
1392 nir_i2f32(&b
, src_pos
),
1393 nir_imm_float(&b
, 0.5f
));
1394 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1396 /* Gen7+ hardware doesn't automaticaly blend. */
1397 color
= blorp_nir_combine_samples(&b
, &v
, src_pos
, key
->src_samples
,
1399 key
->texture_data_type
,
1405 unreachable("Invalid blorp filter");
1408 if (!isl_swizzle_is_identity(key
->src_swizzle
)) {
1409 color
= swizzle_color(&b
, color
, key
->src_swizzle
,
1410 key
->texture_data_type
);
1413 if (!isl_swizzle_is_identity(key
->dst_swizzle
)) {
1414 color
= swizzle_color(&b
, color
, isl_swizzle_invert(key
->dst_swizzle
),
1418 if (key
->format_bit_cast
) {
1419 assert(isl_swizzle_is_identity(key
->src_swizzle
));
1420 assert(isl_swizzle_is_identity(key
->dst_swizzle
));
1421 color
= bit_cast_color(&b
, color
, key
);
1422 } else if (key
->dst_format
) {
1423 color
= convert_color(&b
, color
, key
);
1424 } else if (key
->uint32_to_sint
) {
1425 /* Normally the hardware will take care of converting values from/to
1426 * the source and destination formats. But a few cases need help.
1428 * The Skylake PRM, volume 07, page 658 has a programming note:
1430 * "When using SINT or UINT rendertarget surface formats, Blending
1431 * must be DISABLED. The Pre-Blend Color Clamp Enable and Color
1432 * Clamp Range fields are ignored, and an implied clamp to the
1433 * rendertarget surface format is performed."
1435 * For UINT to SINT blits, our sample operation gives us a uint32_t,
1436 * but our render target write expects a signed int32_t number. If we
1437 * simply passed the value along, the hardware would interpret a value
1438 * with bit 31 set as a negative value, clamping it to the largest
1439 * negative number the destination format could represent. But the
1440 * actual source value is a positive number, so we want to clamp it
1441 * to INT_MAX. To fix this, we explicitly take min(color, INT_MAX).
1443 color
= nir_umin(&b
, color
, nir_imm_int(&b
, INT32_MAX
));
1444 } else if (key
->sint32_to_uint
) {
1445 /* Similar to above, but clamping negative numbers to zero. */
1446 color
= nir_imax(&b
, color
, nir_imm_int(&b
, 0));
1450 /* The destination image is bound as a red texture three times as wide
1451 * as the actual image. Our shader is effectively running one color
1452 * component at a time. We need to pick off the appropriate component
1453 * from the source color and write that to destination red.
1455 assert(dst_pos
->num_components
== 2);
1457 nir_ssa_def
*color_component
=
1458 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1459 nir_channel(&b
, color
, 0),
1460 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1461 nir_channel(&b
, color
, 1),
1462 nir_channel(&b
, color
, 2)));
1464 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1465 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1468 if (key
->dst_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1469 nir_variable
*color_out
=
1470 nir_variable_create(b
.shader
, nir_var_shader_out
,
1471 glsl_vec4_type(), "gl_FragColor");
1472 color_out
->data
.location
= FRAG_RESULT_COLOR
;
1473 nir_store_var(&b
, color_out
, color
, 0xf);
1474 } else if (key
->dst_usage
== ISL_SURF_USAGE_DEPTH_BIT
) {
1475 nir_variable
*depth_out
=
1476 nir_variable_create(b
.shader
, nir_var_shader_out
,
1477 glsl_float_type(), "gl_FragDepth");
1478 depth_out
->data
.location
= FRAG_RESULT_DEPTH
;
1479 nir_store_var(&b
, depth_out
, nir_channel(&b
, color
, 0), 0x1);
1480 } else if (key
->dst_usage
== ISL_SURF_USAGE_STENCIL_BIT
) {
1481 nir_variable
*stencil_out
=
1482 nir_variable_create(b
.shader
, nir_var_shader_out
,
1483 glsl_int_type(), "gl_FragStencilRef");
1484 stencil_out
->data
.location
= FRAG_RESULT_STENCIL
;
1485 nir_store_var(&b
, stencil_out
, nir_channel(&b
, color
, 0), 0x1);
1487 unreachable("Invalid destination usage");
1494 brw_blorp_get_blit_kernel(struct blorp_batch
*batch
,
1495 struct blorp_params
*params
,
1496 const struct brw_blorp_blit_prog_key
*prog_key
)
1498 struct blorp_context
*blorp
= batch
->blorp
;
1500 if (blorp
->lookup_shader(batch
, prog_key
, sizeof(*prog_key
),
1501 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1504 void *mem_ctx
= ralloc_context(NULL
);
1506 const unsigned *program
;
1507 struct brw_wm_prog_data prog_data
;
1509 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1510 nir
->info
.name
= ralloc_strdup(nir
, "BLORP-blit");
1512 struct brw_wm_prog_key wm_key
;
1513 brw_blorp_init_wm_prog_key(&wm_key
);
1514 wm_key
.base
.tex
.compressed_multisample_layout_mask
=
1515 isl_aux_usage_has_mcs(prog_key
->tex_aux_usage
);
1516 wm_key
.base
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1517 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1519 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1523 blorp
->upload_shader(batch
, MESA_SHADER_FRAGMENT
,
1524 prog_key
, sizeof(*prog_key
),
1525 program
, prog_data
.base
.program_size
,
1526 &prog_data
.base
, sizeof(prog_data
),
1527 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1529 ralloc_free(mem_ctx
);
1534 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1535 GLfloat src0
, GLfloat src1
,
1536 GLfloat dst0
, GLfloat dst1
,
1539 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1541 /* When not mirroring a coordinate (say, X), we need:
1542 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1544 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1546 * blorp program uses "round toward zero" to convert the
1547 * transformed floating point coordinates to integer coordinates,
1548 * whereas the behaviour we actually want is "round to nearest",
1549 * so 0.5 provides the necessary correction.
1551 xform
->multiplier
= scale
;
1552 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1554 /* When mirroring X we need:
1555 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1557 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1559 xform
->multiplier
= -scale
;
1560 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1565 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1566 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1568 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1569 struct isl_extent2d px_size_sa
=
1570 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1571 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1572 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1573 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1574 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1576 *tile_x_px
= info
->tile_x_sa
;
1577 *tile_y_px
= info
->tile_y_sa
;
1582 blorp_surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1583 struct brw_blorp_surface_info
*info
)
1587 /* It would be insane to try and do this on a compressed surface */
1588 assert(info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1590 /* Just bail if we have nothing to do. */
1591 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1592 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1593 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1596 /* If this gets triggered then we've gotten here twice which. This
1597 * shouldn't happen thanks to the above early return.
1599 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1601 uint32_t layer
= 0, z
= 0;
1602 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1603 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1605 layer
= info
->view
.base_array_layer
;
1607 uint32_t byte_offset
;
1608 isl_surf_get_image_surf(isl_dev
, &info
->surf
,
1609 info
->view
.base_level
, layer
, z
,
1611 &byte_offset
, &info
->tile_x_sa
, &info
->tile_y_sa
);
1612 info
->addr
.offset
+= byte_offset
;
1614 uint32_t tile_x_px
, tile_y_px
;
1615 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1617 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we place
1618 * the image at the tile boundary and offset our sampling or rendering.
1619 * For this reason, we need to grow the image by the offset to ensure that
1620 * the hardware doesn't think we've gone past the edge.
1622 info
->surf
.logical_level0_px
.w
+= tile_x_px
;
1623 info
->surf
.logical_level0_px
.h
+= tile_y_px
;
1624 info
->surf
.phys_level0_sa
.w
+= info
->tile_x_sa
;
1625 info
->surf
.phys_level0_sa
.h
+= info
->tile_y_sa
;
1627 /* The view is also different now. */
1628 info
->view
.base_level
= 0;
1629 info
->view
.levels
= 1;
1630 info
->view
.base_array_layer
= 0;
1631 info
->view
.array_len
= 1;
1636 blorp_surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1637 struct brw_blorp_surface_info
*info
)
1639 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1641 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1642 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1644 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1645 info
->surf
.samples
= 1;
1646 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1650 blorp_surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1651 struct brw_blorp_surface_info
*info
)
1653 assert(info
->surf
.tiling
== ISL_TILING_W
);
1655 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1656 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1658 /* On gen7+, we don't have interleaved multisampling for color render
1659 * targets so we have to fake it.
1661 * TODO: Are we sure we don't also need to fake it on gen6?
1663 if (isl_dev
->info
->gen
> 6 &&
1664 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1665 blorp_surf_fake_interleaved_msaa(isl_dev
, info
);
1668 if (isl_dev
->info
->gen
== 6) {
1669 /* Gen6 stencil buffers have a very large alignment coming in from the
1670 * miptree. It's out-of-bounds for what the surface state can handle.
1671 * Since we have a single layer and level, it doesn't really matter as
1672 * long as we don't pass a bogus value into isl_surf_fill_state().
1674 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1677 /* Now that we've converted everything to a simple 2-D surface with only
1678 * one miplevel, we can go about retiling it.
1680 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1681 info
->surf
.tiling
= ISL_TILING_Y0
;
1682 info
->surf
.logical_level0_px
.width
=
1683 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1684 info
->surf
.logical_level0_px
.height
=
1685 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1686 info
->tile_x_sa
*= 2;
1687 info
->tile_y_sa
/= 2;
1691 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1693 /* The current code doesn't support offsets into the aux buffers. This
1694 * should be possible, but we need to make sure the offset is page
1695 * aligned for both the surface and the aux buffer surface. Generally
1696 * this mean using the page aligned offset for the aux buffer.
1698 * Currently the cases where we must split the blit are limited to cases
1699 * where we don't have a aux buffer.
1701 if (surf
->aux_addr
.buffer
!= NULL
)
1704 /* We can't support splitting the blit for gen <= 7, because the qpitch
1705 * size is calculated by the hardware based on the surface height for
1706 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1708 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1715 get_max_surface_size(const struct gen_device_info
*devinfo
,
1716 const struct brw_blorp_surface_info
*surf
)
1718 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1719 if (split_blorp_blit_debug
&& can_shrink_surface(surf
))
1720 return max
>> 4; /* A smaller restriction when debug is enabled */
1726 double src0
, src1
, dst0
, dst1
;
1731 struct blt_axis x
, y
;
1734 static enum isl_format
1735 get_red_format_for_rgb_format(enum isl_format format
)
1737 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1739 switch (fmtl
->channels
.r
.bits
) {
1741 switch (fmtl
->channels
.r
.type
) {
1743 return ISL_FORMAT_R8_UNORM
;
1745 return ISL_FORMAT_R8_SNORM
;
1747 return ISL_FORMAT_R8_UINT
;
1749 return ISL_FORMAT_R8_SINT
;
1751 unreachable("Invalid 8-bit RGB channel type");
1754 switch (fmtl
->channels
.r
.type
) {
1756 return ISL_FORMAT_R16_UNORM
;
1758 return ISL_FORMAT_R16_SNORM
;
1760 return ISL_FORMAT_R16_FLOAT
;
1762 return ISL_FORMAT_R16_UINT
;
1764 return ISL_FORMAT_R16_SINT
;
1766 unreachable("Invalid 8-bit RGB channel type");
1769 switch (fmtl
->channels
.r
.type
) {
1771 return ISL_FORMAT_R32_FLOAT
;
1773 return ISL_FORMAT_R32_UINT
;
1775 return ISL_FORMAT_R32_SINT
;
1777 unreachable("Invalid 8-bit RGB channel type");
1780 unreachable("Invalid number of red channel bits");
1785 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1786 struct brw_blorp_surface_info
*info
)
1788 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1790 info
->surf
.logical_level0_px
.width
*= 3;
1791 info
->surf
.phys_level0_sa
.width
*= 3;
1792 info
->tile_x_sa
*= 3;
1794 enum isl_format red_format
=
1795 get_red_format_for_rgb_format(info
->view
.format
);
1797 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1798 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1799 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1800 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1802 info
->surf
.format
= info
->view
.format
= red_format
;
1805 enum blit_shrink_status
{
1807 BLIT_SRC_WIDTH_SHRINK
= (1 << 0),
1808 BLIT_DST_WIDTH_SHRINK
= (1 << 1),
1809 BLIT_SRC_HEIGHT_SHRINK
= (1 << 2),
1810 BLIT_DST_HEIGHT_SHRINK
= (1 << 3),
1813 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1814 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1815 * returned, then the blit was successful.
1817 static enum blit_shrink_status
1818 try_blorp_blit(struct blorp_batch
*batch
,
1819 struct blorp_params
*params
,
1820 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1821 struct blt_coords
*coords
)
1823 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1825 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1826 if (devinfo
->gen
>= 7) {
1827 /* We can render as depth on Gen5 but there's no real advantage since
1828 * it doesn't support MSAA or HiZ. On Gen4, we can't always render
1829 * to depth due to issues with depth buffers and mip-mapping. On
1830 * Gen6, we can do everything but we have weird offsetting for HiZ
1831 * and stencil. It's easier to just render using the color pipe
1832 * on those platforms.
1834 wm_prog_key
->dst_usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1836 wm_prog_key
->dst_usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1838 } else if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1839 assert(params
->dst
.surf
.format
== ISL_FORMAT_R8_UINT
);
1840 if (devinfo
->gen
>= 9) {
1841 wm_prog_key
->dst_usage
= ISL_SURF_USAGE_STENCIL_BIT
;
1843 wm_prog_key
->dst_usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1846 wm_prog_key
->dst_usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1849 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1850 wm_prog_key
->texture_data_type
= nir_type_int
;
1851 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1852 wm_prog_key
->texture_data_type
= nir_type_uint
;
1854 wm_prog_key
->texture_data_type
= nir_type_float
;
1857 /* src_samples and dst_samples are the true sample counts */
1858 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1859 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1861 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1863 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1866 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1867 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1869 /* Round floating point values to nearest integer to avoid "off by one texel"
1870 * kind of errors when blitting.
1872 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1873 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1874 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1875 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1877 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1878 coords
->x
.src0
, coords
->x
.src1
,
1879 coords
->x
.dst0
, coords
->x
.dst1
,
1881 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1882 coords
->y
.src0
, coords
->y
.src1
,
1883 coords
->y
.dst0
, coords
->y
.dst1
,
1887 if (devinfo
->gen
== 4) {
1888 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
1889 * Convert them to a single slice on gen4.
1891 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1892 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1893 wm_prog_key
->need_dst_offset
= true;
1896 if (params
->src
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1897 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->src
);
1898 wm_prog_key
->need_src_offset
= true;
1902 if (devinfo
->gen
> 6 &&
1903 !isl_surf_usage_is_depth_or_stencil(wm_prog_key
->dst_usage
) &&
1904 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1905 assert(params
->dst
.surf
.samples
> 1);
1907 /* We must expand the rectangle we send through the rendering pipeline,
1908 * to account for the fact that we are mapping the destination region as
1909 * single-sampled when it is in fact multisampled. We must also align
1910 * it to a multiple of the multisampling pattern, because the
1911 * differences between multisampled and single-sampled surface formats
1912 * will mean that pixels are scrambled within the multisampling pattern.
1913 * TODO: what if this makes the coordinates too large?
1915 * Note: this only works if the destination surface uses the IMS layout.
1916 * If it's UMS, then we have no choice but to set up the rendering
1917 * pipeline as multisampled.
1919 struct isl_extent2d px_size_sa
=
1920 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1921 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1922 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1923 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1924 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1926 blorp_surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1928 wm_prog_key
->use_kill
= true;
1929 wm_prog_key
->need_dst_offset
= true;
1932 if (params
->dst
.surf
.tiling
== ISL_TILING_W
&&
1933 wm_prog_key
->dst_usage
!= ISL_SURF_USAGE_STENCIL_BIT
) {
1934 /* We must modify the rectangle we send through the rendering pipeline
1935 * (and the size and x/y offset of the destination surface), to account
1936 * for the fact that we are mapping it as Y-tiled when it is in fact
1939 * Both Y tiling and W tiling can be understood as organizations of
1940 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1941 * is different, but the layout of the 32-byte sub-tiles within the 4k
1942 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1943 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1944 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1946 * Therefore, to account for the layout differences within the 32-byte
1947 * sub-tiles, we must expand the rectangle so the X coordinates of its
1948 * edges are multiples of 8 (the W sub-tile width), and its Y
1949 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1950 * Then we need to scale the X and Y coordinates of the rectangle to
1951 * account for the differences in aspect ratio between the Y and W
1952 * sub-tiles. We need to modify the layer width and height similarly.
1954 * A correction needs to be applied when MSAA is in use: since
1955 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1956 * we need to align the Y coordinates to multiples of 8, so that when
1957 * they are divided by two they are still multiples of 4.
1959 * Note: Since the x/y offset of the surface will be applied using the
1960 * SURFACE_STATE command packet, it will be invisible to the swizzling
1961 * code in the shader; therefore it needs to be in a multiple of the
1962 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1963 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1964 * buffer), and the miplevel alignment used for stencil buffers is 8
1965 * pixels horizontally and either 4 or 8 pixels vertically (see
1966 * intel_horizontal_texture_alignment_unit() and
1967 * intel_vertical_texture_alignment_unit()).
1969 * Note: Also, since the SURFACE_STATE command packet can only apply
1970 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1971 * vertically, it is important that the offsets will be multiples of
1972 * these sizes after they are converted into Y-tiled coordinates.
1973 * Fortunately they will be, since we know from above that the offsets
1974 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1975 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1977 * TODO: what if this makes the coordinates (or the texture size) too
1980 const unsigned x_align
= 8;
1981 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1982 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1983 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1984 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1985 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1987 /* Retile the surface to Y-tiled */
1988 blorp_surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1990 wm_prog_key
->dst_tiled_w
= true;
1991 wm_prog_key
->use_kill
= true;
1992 wm_prog_key
->need_dst_offset
= true;
1994 if (params
->dst
.surf
.samples
> 1) {
1995 /* If the destination surface is a W-tiled multisampled stencil
1996 * buffer that we're mapping as Y tiled, then we need to arrange for
1997 * the WM program to run once per sample rather than once per pixel,
1998 * because the memory layout of related samples doesn't match between
2001 wm_prog_key
->persample_msaa_dispatch
= true;
2005 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
2006 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
2007 * Broadwell adds support for sampling from stencil.
2009 * See the comments above concerning x/y offset alignment for the
2010 * destination surface.
2012 * TODO: what if this makes the texture size too large?
2014 blorp_surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
2016 wm_prog_key
->src_tiled_w
= true;
2017 wm_prog_key
->need_src_offset
= true;
2020 /* tex_samples and rt_samples are the sample counts that are set up in
2023 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
2024 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
2026 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2027 * use to access the source and destination surfaces.
2029 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
2030 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
2032 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
2033 /* We are blitting from a multisample buffer to a multisample buffer, so
2034 * we must preserve samples within a pixel. This means we have to
2035 * arrange for the WM program to run once per sample rather than once
2038 wm_prog_key
->persample_msaa_dispatch
= true;
2041 params
->num_samples
= params
->dst
.surf
.samples
;
2043 if ((wm_prog_key
->filter
== BLORP_FILTER_AVERAGE
||
2044 wm_prog_key
->filter
== BLORP_FILTER_BILINEAR
) &&
2045 batch
->blorp
->isl_dev
->info
->gen
<= 6) {
2046 /* Gen4-5 don't support non-normalized texture coordinates */
2047 wm_prog_key
->src_coords_normalized
= true;
2048 params
->wm_inputs
.src_inv_size
[0] =
2049 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.width
,
2050 params
->src
.view
.base_level
);
2051 params
->wm_inputs
.src_inv_size
[1] =
2052 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.height
,
2053 params
->src
.view
.base_level
);
2056 if (isl_format_get_layout(params
->dst
.view
.format
)->bpb
% 3 == 0) {
2057 /* We can't render to RGB formats natively because they aren't a
2058 * power-of-two size. Instead, we fake them by using a red format
2059 * with the same channel type and size and emitting shader code to
2060 * only write one channel at a time.
2065 /* If it happens to be sRGB, we need to force a conversion */
2066 if (params
->dst
.view
.format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
)
2067 wm_prog_key
->dst_format
= ISL_FORMAT_R8G8B8_UNORM_SRGB
;
2069 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
->dst
);
2071 wm_prog_key
->dst_rgb
= true;
2072 wm_prog_key
->need_dst_offset
= true;
2073 } else if (isl_format_is_rgbx(params
->dst
.view
.format
)) {
2074 /* We can handle RGBX formats easily enough by treating them as RGBA */
2075 params
->dst
.view
.format
=
2076 isl_format_rgbx_to_rgba(params
->dst
.view
.format
);
2077 } else if (params
->dst
.view
.format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
&&
2078 wm_prog_key
->dst_usage
!= ISL_SURF_USAGE_DEPTH_BIT
) {
2079 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2080 params
->dst
.view
.format
= ISL_FORMAT_R32_UINT
;
2081 } else if (params
->dst
.view
.format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
2082 params
->dst
.view
.swizzle
=
2083 isl_swizzle_compose(params
->dst
.view
.swizzle
,
2084 ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
));
2085 params
->dst
.view
.format
= ISL_FORMAT_B4G4R4A4_UNORM
;
2086 } else if (params
->dst
.view
.format
== ISL_FORMAT_L8_UNORM_SRGB
) {
2087 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2088 params
->dst
.view
.format
= ISL_FORMAT_R8_UNORM
;
2089 } else if (params
->dst
.view
.format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
2090 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2091 params
->dst
.view
.format
= ISL_FORMAT_R32_UINT
;
2094 if (devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
2095 !isl_swizzle_is_identity(params
->src
.view
.swizzle
)) {
2096 wm_prog_key
->src_swizzle
= params
->src
.view
.swizzle
;
2097 params
->src
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
2099 wm_prog_key
->src_swizzle
= ISL_SWIZZLE_IDENTITY
;
2102 if (!isl_swizzle_supports_rendering(devinfo
, params
->dst
.view
.swizzle
)) {
2103 wm_prog_key
->dst_swizzle
= params
->dst
.view
.swizzle
;
2104 params
->dst
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
2106 wm_prog_key
->dst_swizzle
= ISL_SWIZZLE_IDENTITY
;
2109 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
2110 assert(wm_prog_key
->need_src_offset
);
2111 surf_get_intratile_offset_px(¶ms
->src
,
2112 ¶ms
->wm_inputs
.src_offset
.x
,
2113 ¶ms
->wm_inputs
.src_offset
.y
);
2116 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
2117 assert(wm_prog_key
->need_dst_offset
);
2118 surf_get_intratile_offset_px(¶ms
->dst
,
2119 ¶ms
->wm_inputs
.dst_offset
.x
,
2120 ¶ms
->wm_inputs
.dst_offset
.y
);
2121 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
2122 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
2123 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
2124 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
2127 /* For some texture types, we need to pass the layer through the sampler. */
2128 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
2130 if (!brw_blorp_get_blit_kernel(batch
, params
, wm_prog_key
))
2133 if (!blorp_ensure_sf_program(batch
, params
))
2136 unsigned result
= 0;
2137 unsigned max_src_surface_size
= get_max_surface_size(devinfo
, ¶ms
->src
);
2138 if (params
->src
.surf
.logical_level0_px
.width
> max_src_surface_size
)
2139 result
|= BLIT_SRC_WIDTH_SHRINK
;
2140 if (params
->src
.surf
.logical_level0_px
.height
> max_src_surface_size
)
2141 result
|= BLIT_SRC_HEIGHT_SHRINK
;
2143 unsigned max_dst_surface_size
= get_max_surface_size(devinfo
, ¶ms
->dst
);
2144 if (params
->dst
.surf
.logical_level0_px
.width
> max_dst_surface_size
)
2145 result
|= BLIT_DST_WIDTH_SHRINK
;
2146 if (params
->dst
.surf
.logical_level0_px
.height
> max_dst_surface_size
)
2147 result
|= BLIT_DST_HEIGHT_SHRINK
;
2150 if (wm_prog_key
->dst_usage
== ISL_SURF_USAGE_DEPTH_BIT
) {
2151 params
->depth
= params
->dst
;
2152 memset(¶ms
->dst
, 0, sizeof(params
->dst
));
2153 } else if (wm_prog_key
->dst_usage
== ISL_SURF_USAGE_STENCIL_BIT
) {
2154 params
->stencil
= params
->dst
;
2155 params
->stencil_mask
= 0xff;
2156 memset(¶ms
->dst
, 0, sizeof(params
->dst
));
2159 batch
->blorp
->exec(batch
, params
);
2165 /* Adjust split blit source coordinates for the current destination
2169 adjust_split_source_coords(const struct blt_axis
*orig
,
2170 struct blt_axis
*split_coords
,
2173 /* When scale is greater than 0, then we are growing from the start, so
2174 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
2175 * source range shrinks from the end. In that case src0 is adjusted by
2176 * delta1, and src1 is adjusted by delta0.
2178 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
2179 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
2180 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
2181 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
2184 static struct isl_extent2d
2185 get_px_size_sa(const struct isl_surf
*surf
)
2187 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
2189 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
2192 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
2196 shrink_surface_params(const struct isl_device
*dev
,
2197 struct brw_blorp_surface_info
*info
,
2198 double *x0
, double *x1
, double *y0
, double *y1
)
2200 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
2201 struct isl_extent2d px_size_sa
;
2204 blorp_surf_convert_to_single_slice(dev
, info
);
2206 px_size_sa
= get_px_size_sa(&info
->surf
);
2208 /* Because this gets called after we lower compressed images, the tile
2209 * offsets may be non-zero and we need to incorporate them in our
2212 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
2213 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
2214 isl_tiling_get_intratile_offset_sa(info
->surf
.tiling
,
2215 info
->surf
.format
, info
->surf
.row_pitch_B
,
2216 x_offset_sa
, y_offset_sa
,
2218 &info
->tile_x_sa
, &info
->tile_y_sa
);
2220 info
->addr
.offset
+= byte_offset
;
2222 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
2225 info
->tile_x_sa
= 0;
2227 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
2230 info
->tile_y_sa
= 0;
2232 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
2233 info
->surf
.logical_level0_px
.width
= size
;
2234 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
2236 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
2237 info
->surf
.logical_level0_px
.height
= size
;
2238 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
2242 do_blorp_blit(struct blorp_batch
*batch
,
2243 const struct blorp_params
*orig_params
,
2244 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2245 const struct blt_coords
*orig
)
2247 struct blorp_params params
;
2248 struct blt_coords blit_coords
;
2249 struct blt_coords split_coords
= *orig
;
2250 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
2251 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
2252 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
2253 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
2259 enum blit_shrink_status shrink
= BLIT_NO_SHRINK
;
2260 if (split_blorp_blit_debug
) {
2261 if (can_shrink_surface(&orig_params
->src
))
2262 shrink
|= BLIT_SRC_WIDTH_SHRINK
| BLIT_SRC_HEIGHT_SHRINK
;
2263 if (can_shrink_surface(&orig_params
->dst
))
2264 shrink
|= BLIT_DST_WIDTH_SHRINK
| BLIT_DST_HEIGHT_SHRINK
;
2267 bool x_done
, y_done
;
2269 params
= *orig_params
;
2270 blit_coords
= split_coords
;
2272 if (shrink
& (BLIT_SRC_WIDTH_SHRINK
| BLIT_SRC_HEIGHT_SHRINK
)) {
2273 shrink_surface_params(batch
->blorp
->isl_dev
, ¶ms
.src
,
2274 &blit_coords
.x
.src0
, &blit_coords
.x
.src1
,
2275 &blit_coords
.y
.src0
, &blit_coords
.y
.src1
);
2276 wm_prog_key
->need_src_offset
= false;
2279 if (shrink
& (BLIT_DST_WIDTH_SHRINK
| BLIT_DST_HEIGHT_SHRINK
)) {
2280 shrink_surface_params(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2281 &blit_coords
.x
.dst0
, &blit_coords
.x
.dst1
,
2282 &blit_coords
.y
.dst0
, &blit_coords
.y
.dst1
);
2283 wm_prog_key
->need_dst_offset
= false;
2286 enum blit_shrink_status result
=
2287 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
2289 if (result
& (BLIT_SRC_WIDTH_SHRINK
| BLIT_SRC_HEIGHT_SHRINK
))
2290 assert(can_shrink_surface(&orig_params
->src
));
2292 if (result
& (BLIT_DST_WIDTH_SHRINK
| BLIT_DST_HEIGHT_SHRINK
))
2293 assert(can_shrink_surface(&orig_params
->dst
));
2295 if (result
& (BLIT_SRC_WIDTH_SHRINK
| BLIT_DST_WIDTH_SHRINK
)) {
2298 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2299 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2301 if (result
& (BLIT_SRC_HEIGHT_SHRINK
| BLIT_DST_HEIGHT_SHRINK
)) {
2304 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2305 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2309 /* We may get less bits set on result than we had already, so make
2310 * sure we remember all the ways in which a resize is required.
2316 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
2317 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
2320 } else if (y_done
) {
2321 split_coords
.x
.dst0
+= w
;
2322 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2323 split_coords
.y
.dst0
= orig
->y
.dst0
;
2324 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2325 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2327 split_coords
.y
.dst0
+= h
;
2328 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2329 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2335 blorp_blit(struct blorp_batch
*batch
,
2336 const struct blorp_surf
*src_surf
,
2337 unsigned src_level
, unsigned src_layer
,
2338 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2339 const struct blorp_surf
*dst_surf
,
2340 unsigned dst_level
, unsigned dst_layer
,
2341 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2342 float src_x0
, float src_y0
,
2343 float src_x1
, float src_y1
,
2344 float dst_x0
, float dst_y0
,
2345 float dst_x1
, float dst_y1
,
2346 enum blorp_filter filter
,
2347 bool mirror_x
, bool mirror_y
)
2349 struct blorp_params params
;
2350 blorp_params_init(¶ms
);
2352 /* We cannot handle combined depth and stencil. */
2353 if (src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2354 assert(src_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2355 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2356 assert(dst_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2358 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
2359 assert(src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
);
2360 /* Prior to Broadwell, we can't render to R8_UINT */
2361 if (batch
->blorp
->isl_dev
->info
->gen
< 8) {
2362 src_format
= ISL_FORMAT_R8_UNORM
;
2363 dst_format
= ISL_FORMAT_R8_UNORM
;
2367 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2368 src_layer
, src_format
, false);
2369 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2370 dst_layer
, dst_format
, true);
2372 params
.src
.view
.swizzle
= src_swizzle
;
2373 params
.dst
.view
.swizzle
= dst_swizzle
;
2375 const struct isl_format_layout
*src_fmtl
=
2376 isl_format_get_layout(params
.src
.view
.format
);
2378 struct brw_blorp_blit_prog_key wm_prog_key
= {
2379 .shader_type
= BLORP_SHADER_TYPE_BLIT
,
2381 .sint32_to_uint
= src_fmtl
->channels
.r
.bits
== 32 &&
2382 isl_format_has_sint_channel(params
.src
.view
.format
) &&
2383 isl_format_has_uint_channel(params
.dst
.view
.format
),
2384 .uint32_to_sint
= src_fmtl
->channels
.r
.bits
== 32 &&
2385 isl_format_has_uint_channel(params
.src
.view
.format
) &&
2386 isl_format_has_sint_channel(params
.dst
.view
.format
),
2389 /* Scaling factors used for bilinear filtering in multisample scaled
2392 if (params
.src
.surf
.samples
== 16)
2393 wm_prog_key
.x_scale
= 4.0f
;
2395 wm_prog_key
.x_scale
= 2.0f
;
2396 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2398 params
.wm_inputs
.rect_grid
.x1
=
2399 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2400 wm_prog_key
.x_scale
- 1.0f
;
2401 params
.wm_inputs
.rect_grid
.y1
=
2402 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2403 wm_prog_key
.y_scale
- 1.0f
;
2405 struct blt_coords coords
= {
2422 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2425 static enum isl_format
2426 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2428 /* The choice of UNORM and UINT formats is very intentional here. Most
2429 * of the time, we want to use a UINT format to avoid any rounding error
2430 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2431 * (It's the only format allowed in conjunction with W-tiling.) Also we
2432 * intentionally use the 4-channel formats whenever we can. This is so
2433 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2434 * even though one of them is 3/4 the size of the other. The choice of
2435 * UNORM vs. UINT is also very intentional because we don't have 8 or
2436 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2437 * Fortunately, the only time we should ever use two different formats in
2438 * the table below is for RGB -> RGBA blits and so we will never have any
2439 * UNORM/UINT mismatch.
2441 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2443 case 8: return ISL_FORMAT_R8_UINT
;
2444 case 16: return ISL_FORMAT_R8G8_UINT
;
2445 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2446 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2447 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2448 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2449 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2450 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2452 unreachable("Unknown format bpb");
2456 case 8: return ISL_FORMAT_R8_UINT
;
2457 case 16: return ISL_FORMAT_R8G8_UINT
;
2458 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2459 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2460 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2461 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2462 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2463 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2465 unreachable("Unknown format bpb");
2470 /** Returns a UINT format that is CCS-compatible with the given format
2472 * The PRM's say absolutely nothing about how render compression works. The
2473 * only thing they provide is a list of formats on which it is and is not
2474 * supported. Empirical testing indicates that the compression is only based
2475 * on the bit-layout of the format and the channel encoding doesn't matter.
2476 * So, while texture views don't work in general, you can create a view as
2477 * long as the bit-layout of the formats are the same.
2479 * Fortunately, for every render compression capable format, the UINT format
2480 * with the same bit layout also supports render compression. This means that
2481 * we only need to handle UINT formats for copy operations. In order to do
2482 * copies between formats with different bit layouts, we attach both with a
2483 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2484 * operation between the two bit layouts.
2486 static enum isl_format
2487 get_ccs_compatible_copy_format(const struct isl_format_layout
*fmtl
)
2489 switch (fmtl
->format
) {
2490 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2491 case ISL_FORMAT_R32G32B32A32_SINT
:
2492 case ISL_FORMAT_R32G32B32A32_UINT
:
2493 case ISL_FORMAT_R32G32B32A32_UNORM
:
2494 case ISL_FORMAT_R32G32B32A32_SNORM
:
2495 case ISL_FORMAT_R32G32B32X32_FLOAT
:
2496 return ISL_FORMAT_R32G32B32A32_UINT
;
2498 case ISL_FORMAT_R16G16B16A16_UNORM
:
2499 case ISL_FORMAT_R16G16B16A16_SNORM
:
2500 case ISL_FORMAT_R16G16B16A16_SINT
:
2501 case ISL_FORMAT_R16G16B16A16_UINT
:
2502 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2503 case ISL_FORMAT_R16G16B16X16_UNORM
:
2504 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2505 return ISL_FORMAT_R16G16B16A16_UINT
;
2507 case ISL_FORMAT_R32G32_FLOAT
:
2508 case ISL_FORMAT_R32G32_SINT
:
2509 case ISL_FORMAT_R32G32_UINT
:
2510 case ISL_FORMAT_R32G32_UNORM
:
2511 case ISL_FORMAT_R32G32_SNORM
:
2512 return ISL_FORMAT_R32G32_UINT
;
2514 case ISL_FORMAT_B8G8R8A8_UNORM
:
2515 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2516 case ISL_FORMAT_R8G8B8A8_UNORM
:
2517 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2518 case ISL_FORMAT_R8G8B8A8_SNORM
:
2519 case ISL_FORMAT_R8G8B8A8_SINT
:
2520 case ISL_FORMAT_R8G8B8A8_UINT
:
2521 case ISL_FORMAT_B8G8R8X8_UNORM
:
2522 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2523 case ISL_FORMAT_R8G8B8X8_UNORM
:
2524 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2525 return ISL_FORMAT_R8G8B8A8_UINT
;
2527 case ISL_FORMAT_R16G16_UNORM
:
2528 case ISL_FORMAT_R16G16_SNORM
:
2529 case ISL_FORMAT_R16G16_SINT
:
2530 case ISL_FORMAT_R16G16_UINT
:
2531 case ISL_FORMAT_R16G16_FLOAT
:
2532 return ISL_FORMAT_R16G16_UINT
;
2534 case ISL_FORMAT_R32_SINT
:
2535 case ISL_FORMAT_R32_UINT
:
2536 case ISL_FORMAT_R32_FLOAT
:
2537 case ISL_FORMAT_R32_UNORM
:
2538 case ISL_FORMAT_R32_SNORM
:
2539 return ISL_FORMAT_R32_UINT
;
2541 case ISL_FORMAT_B10G10R10A2_UNORM
:
2542 case ISL_FORMAT_B10G10R10A2_UNORM_SRGB
:
2543 case ISL_FORMAT_R10G10B10A2_UNORM
:
2544 case ISL_FORMAT_R10G10B10A2_UNORM_SRGB
:
2545 case ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM
:
2546 case ISL_FORMAT_R10G10B10A2_UINT
:
2547 return ISL_FORMAT_R10G10B10A2_UINT
;
2549 case ISL_FORMAT_R16_UNORM
:
2550 case ISL_FORMAT_R16_SNORM
:
2551 case ISL_FORMAT_R16_SINT
:
2552 case ISL_FORMAT_R16_UINT
:
2553 case ISL_FORMAT_R16_FLOAT
:
2554 return ISL_FORMAT_R16_UINT
;
2556 case ISL_FORMAT_R8G8_UNORM
:
2557 case ISL_FORMAT_R8G8_SNORM
:
2558 case ISL_FORMAT_R8G8_SINT
:
2559 case ISL_FORMAT_R8G8_UINT
:
2560 return ISL_FORMAT_R8G8_UINT
;
2562 case ISL_FORMAT_B5G5R5X1_UNORM
:
2563 case ISL_FORMAT_B5G5R5X1_UNORM_SRGB
:
2564 case ISL_FORMAT_B5G5R5A1_UNORM
:
2565 case ISL_FORMAT_B5G5R5A1_UNORM_SRGB
:
2566 return ISL_FORMAT_B5G5R5A1_UNORM
;
2568 case ISL_FORMAT_A4B4G4R4_UNORM
:
2569 case ISL_FORMAT_B4G4R4A4_UNORM
:
2570 case ISL_FORMAT_B4G4R4A4_UNORM_SRGB
:
2571 return ISL_FORMAT_B4G4R4A4_UNORM
;
2573 case ISL_FORMAT_B5G6R5_UNORM
:
2574 case ISL_FORMAT_B5G6R5_UNORM_SRGB
:
2575 return ISL_FORMAT_B5G6R5_UNORM
;
2577 case ISL_FORMAT_A1B5G5R5_UNORM
:
2578 return ISL_FORMAT_A1B5G5R5_UNORM
;
2580 case ISL_FORMAT_A8_UNORM
:
2581 case ISL_FORMAT_R8_UNORM
:
2582 case ISL_FORMAT_R8_SNORM
:
2583 case ISL_FORMAT_R8_SINT
:
2584 case ISL_FORMAT_R8_UINT
:
2585 return ISL_FORMAT_R8_UINT
;
2588 unreachable("Not a compressible format");
2593 blorp_surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2594 struct brw_blorp_surface_info
*info
,
2595 uint32_t *x
, uint32_t *y
,
2596 uint32_t *width
, uint32_t *height
)
2598 const struct isl_format_layout
*fmtl
=
2599 isl_format_get_layout(info
->surf
.format
);
2601 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2603 /* This is a compressed surface. We need to convert it to a single
2604 * slice (because compressed layouts don't perfectly match uncompressed
2605 * ones with the same bpb) and divide x, y, width, and height by the
2608 blorp_surf_convert_to_single_slice(isl_dev
, info
);
2610 if (width
&& height
) {
2612 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2613 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2614 assert(*width
% fmtl
->bw
== 0 ||
2615 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2616 assert(*height
% fmtl
->bh
== 0 ||
2617 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2619 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2620 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2624 assert(*x
% fmtl
->bw
== 0);
2625 assert(*y
% fmtl
->bh
== 0);
2630 info
->surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&info
->surf
);
2631 info
->surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&info
->surf
);
2633 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2634 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2635 info
->tile_x_sa
/= fmtl
->bw
;
2636 info
->tile_y_sa
/= fmtl
->bh
;
2638 /* It's now an uncompressed surface so we need an uncompressed format */
2639 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2643 blorp_copy(struct blorp_batch
*batch
,
2644 const struct blorp_surf
*src_surf
,
2645 unsigned src_level
, unsigned src_layer
,
2646 const struct blorp_surf
*dst_surf
,
2647 unsigned dst_level
, unsigned dst_layer
,
2648 uint32_t src_x
, uint32_t src_y
,
2649 uint32_t dst_x
, uint32_t dst_y
,
2650 uint32_t src_width
, uint32_t src_height
)
2652 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2653 struct blorp_params params
;
2655 if (src_width
== 0 || src_height
== 0)
2658 blorp_params_init(¶ms
);
2659 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2660 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2661 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2662 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2664 struct brw_blorp_blit_prog_key wm_prog_key
= {
2665 .shader_type
= BLORP_SHADER_TYPE_BLIT
,
2666 .filter
= BLORP_FILTER_NONE
,
2667 .need_src_offset
= src_surf
->tile_x_sa
|| src_surf
->tile_y_sa
,
2668 .need_dst_offset
= dst_surf
->tile_x_sa
|| dst_surf
->tile_y_sa
,
2671 const struct isl_format_layout
*src_fmtl
=
2672 isl_format_get_layout(params
.src
.surf
.format
);
2673 const struct isl_format_layout
*dst_fmtl
=
2674 isl_format_get_layout(params
.dst
.surf
.format
);
2676 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2677 params
.src
.aux_usage
== ISL_AUX_USAGE_HIZ
||
2678 params
.src
.aux_usage
== ISL_AUX_USAGE_HIZ_CCS_WT
||
2679 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2680 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS_CCS
||
2681 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
||
2682 params
.src
.aux_usage
== ISL_AUX_USAGE_STC_CCS
);
2684 if (isl_aux_usage_has_hiz(params
.src
.aux_usage
)) {
2685 /* In order to use HiZ, we have to use the real format for the source.
2686 * Depth <-> Color copies are not allowed.
2688 params
.src
.view
.format
= params
.src
.surf
.format
;
2689 params
.dst
.view
.format
= params
.src
.surf
.format
;
2690 } else if ((params
.dst
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
2691 isl_dev
->info
->gen
>= 7) {
2692 /* On Gen7 and higher, we use actual depth writes for blits into depth
2693 * buffers so we need the real format.
2695 params
.src
.view
.format
= params
.dst
.surf
.format
;
2696 params
.dst
.view
.format
= params
.dst
.surf
.format
;
2697 } else if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2698 params
.dst
.view
.format
= get_ccs_compatible_copy_format(dst_fmtl
);
2699 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2700 params
.src
.view
.format
= get_ccs_compatible_copy_format(src_fmtl
);
2701 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2702 params
.src
.view
.format
= params
.dst
.view
.format
;
2704 params
.src
.view
.format
=
2705 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2707 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2708 params
.src
.view
.format
= get_ccs_compatible_copy_format(src_fmtl
);
2709 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2710 params
.dst
.view
.format
= params
.src
.view
.format
;
2712 params
.dst
.view
.format
=
2713 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2716 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2717 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2720 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2721 /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
2722 * enabled even though CCS_E doesn't technically do sRGB on SKL because
2723 * we stomp everything to UINT anyway. The one thing we have to be
2724 * careful of is clear colors. Because fast clear colors for sRGB on
2725 * gen9 are encoded as the float values between format conversion and
2726 * sRGB curve application, a given clear color float will convert to the
2727 * same bits regardless of whether the format is UNORM or sRGB.
2728 * Therefore, we can handle sRGB without any special cases.
2730 UNUSED
enum isl_format linear_src_format
=
2731 isl_format_srgb_to_linear(src_surf
->surf
->format
);
2732 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2734 params
.src
.view
.format
));
2736 isl_color_value_pack(¶ms
.src
.clear_color
,
2737 linear_src_format
, packed
);
2738 isl_color_value_unpack(¶ms
.src
.clear_color
,
2739 params
.src
.view
.format
, packed
);
2742 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2743 /* See above where we handle linear_src_format */
2744 UNUSED
enum isl_format linear_dst_format
=
2745 isl_format_srgb_to_linear(dst_surf
->surf
->format
);
2746 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2748 params
.dst
.view
.format
));
2750 isl_color_value_pack(¶ms
.dst
.clear_color
,
2751 linear_dst_format
, packed
);
2752 isl_color_value_unpack(¶ms
.dst
.clear_color
,
2753 params
.dst
.view
.format
, packed
);
2756 if (params
.src
.view
.format
!= params
.dst
.view
.format
) {
2757 enum isl_format src_cast_format
= params
.src
.view
.format
;
2758 enum isl_format dst_cast_format
= params
.dst
.view
.format
;
2760 /* The BLORP bitcast code gets confused by RGB formats. Just treat them
2761 * as RGBA and then everything will be happy. This is perfectly safe
2762 * because BLORP likes to treat things as if they have vec4 colors all
2765 if (isl_format_get_layout(src_cast_format
)->bpb
% 3 == 0)
2766 src_cast_format
= isl_format_rgb_to_rgba(src_cast_format
);
2767 if (isl_format_get_layout(dst_cast_format
)->bpb
% 3 == 0)
2768 dst_cast_format
= isl_format_rgb_to_rgba(dst_cast_format
);
2770 if (src_cast_format
!= dst_cast_format
) {
2771 wm_prog_key
.format_bit_cast
= true;
2772 wm_prog_key
.src_format
= src_cast_format
;
2773 wm_prog_key
.dst_format
= dst_cast_format
;
2777 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2778 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2780 &src_width
, &src_height
);
2781 wm_prog_key
.need_src_offset
= true;
2784 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2785 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2786 &dst_x
, &dst_y
, NULL
, NULL
);
2787 wm_prog_key
.need_dst_offset
= true;
2790 /* Once both surfaces are stompped to uncompressed as needed, the
2791 * destination size is the same as the source size.
2793 uint32_t dst_width
= src_width
;
2794 uint32_t dst_height
= src_height
;
2796 struct blt_coords coords
= {
2799 .src1
= src_x
+ src_width
,
2801 .dst1
= dst_x
+ dst_width
,
2806 .src1
= src_y
+ src_height
,
2808 .dst1
= dst_y
+ dst_height
,
2813 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2816 static enum isl_format
2817 isl_format_for_size(unsigned size_B
)
2820 case 1: return ISL_FORMAT_R8_UINT
;
2821 case 2: return ISL_FORMAT_R8G8_UINT
;
2822 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
2823 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
2824 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
2826 unreachable("Not a power-of-two format size");
2831 * Returns the greatest common divisor of a and b that is a power of two.
2834 gcd_pow2_u64(uint64_t a
, uint64_t b
)
2836 assert(a
> 0 || b
> 0);
2838 unsigned a_log2
= ffsll(a
) - 1;
2839 unsigned b_log2
= ffsll(b
) - 1;
2841 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
2842 * case, the MIN2() will take the other one. If both are 0 then we will
2843 * hit the assert above.
2845 return 1 << MIN2(a_log2
, b_log2
);
2849 do_buffer_copy(struct blorp_batch
*batch
,
2850 struct blorp_address
*src
,
2851 struct blorp_address
*dst
,
2852 int width
, int height
, int block_size
)
2854 /* The actual format we pick doesn't matter as blorp will throw it away.
2855 * The only thing that actually matters is the size.
2857 enum isl_format format
= isl_format_for_size(block_size
);
2860 struct isl_surf surf
;
2861 ok
= isl_surf_init(batch
->blorp
->isl_dev
, &surf
,
2862 .dim
= ISL_SURF_DIM_2D
,
2870 .row_pitch_B
= width
* block_size
,
2871 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
2872 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
2873 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
2876 struct blorp_surf src_blorp_surf
= {
2881 struct blorp_surf dst_blorp_surf
= {
2886 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
2887 0, 0, 0, 0, width
, height
);
2891 blorp_buffer_copy(struct blorp_batch
*batch
,
2892 struct blorp_address src
,
2893 struct blorp_address dst
,
2896 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
2897 uint64_t copy_size
= size
;
2899 /* This is maximum possible width/height our HW can handle */
2900 uint64_t max_surface_dim
= 1 << (devinfo
->gen
>= 7 ? 14 : 13);
2902 /* First, we compute the biggest format that can be used with the
2903 * given offsets and size.
2906 bs
= gcd_pow2_u64(bs
, src
.offset
);
2907 bs
= gcd_pow2_u64(bs
, dst
.offset
);
2908 bs
= gcd_pow2_u64(bs
, size
);
2910 /* First, we make a bunch of max-sized copies */
2911 uint64_t max_copy_size
= max_surface_dim
* max_surface_dim
* bs
;
2912 while (copy_size
>= max_copy_size
) {
2913 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, max_surface_dim
, bs
);
2914 copy_size
-= max_copy_size
;
2915 src
.offset
+= max_copy_size
;
2916 dst
.offset
+= max_copy_size
;
2919 /* Now make a max-width copy */
2920 uint64_t height
= copy_size
/ (max_surface_dim
* bs
);
2921 assert(height
< max_surface_dim
);
2923 uint64_t rect_copy_size
= height
* max_surface_dim
* bs
;
2924 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, height
, bs
);
2925 copy_size
-= rect_copy_size
;
2926 src
.offset
+= rect_copy_size
;
2927 dst
.offset
+= rect_copy_size
;
2930 /* Finally, make a small copy to finish it off */
2931 if (copy_size
!= 0) {
2932 do_buffer_copy(batch
, &src
, &dst
, copy_size
/ bs
, 1, bs
);