2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "blorp_nir_builder.h"
25 #include "compiler/nir/nir_format_convert.h"
27 #include "blorp_priv.h"
29 #include "util/format_rgb9e5.h"
30 /* header-only include needed for _mesa_unorm_to_float and friends. */
31 #include "mesa/main/format_utils.h"
32 #include "util/u_math.h"
34 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 static const bool split_blorp_blit_debug
= false;
38 struct brw_blorp_blit_vars
{
39 /* Input values from brw_blorp_wm_inputs */
40 nir_variable
*v_discard_rect
;
41 nir_variable
*v_rect_grid
;
42 nir_variable
*v_coord_transform
;
43 nir_variable
*v_src_z
;
44 nir_variable
*v_src_offset
;
45 nir_variable
*v_dst_offset
;
46 nir_variable
*v_src_inv_size
;
50 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
51 const struct brw_blorp_blit_prog_key
*key
)
53 #define LOAD_INPUT(name, type)\
54 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
56 LOAD_INPUT(discard_rect
, glsl_vec4_type())
57 LOAD_INPUT(rect_grid
, glsl_vec4_type())
58 LOAD_INPUT(coord_transform
, glsl_vec4_type())
59 LOAD_INPUT(src_z
, glsl_uint_type())
60 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
61 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
62 LOAD_INPUT(src_inv_size
, glsl_vector_type(GLSL_TYPE_FLOAT
, 2))
68 blorp_blit_get_frag_coords(nir_builder
*b
,
69 const struct brw_blorp_blit_prog_key
*key
,
70 struct brw_blorp_blit_vars
*v
)
72 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_frag_coord(b
));
74 /* Account for destination surface intratile offset
76 * Transformation parameters giving translation from destination to source
77 * coordinates don't take into account possible intra-tile destination
78 * offset. Therefore it has to be first subtracted from the incoming
79 * coordinates. Vertices are set up based on coordinates containing the
82 if (key
->need_dst_offset
)
83 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
85 if (key
->persample_msaa_dispatch
) {
86 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
87 nir_load_sample_id(b
));
89 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
94 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
98 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
99 struct brw_blorp_blit_vars
*v
)
101 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
103 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
104 nir_channel(b
, coord_transform
, 3));
105 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
106 nir_channel(b
, coord_transform
, 2));
108 return nir_fadd(b
, nir_fmul(b
, src_pos
, mul
), offset
);
112 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
113 struct brw_blorp_blit_vars
*v
)
115 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
116 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
117 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
118 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
119 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
120 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
122 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
123 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
124 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
125 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
127 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
129 nir_intrinsic_instr
*discard
=
130 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
131 discard
->src
[0] = nir_src_for_ssa(oob
);
132 nir_builder_instr_insert(b
, &discard
->instr
);
135 static nir_tex_instr
*
136 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
137 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
138 nir_alu_type dst_type
)
140 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
144 tex
->dest_type
= dst_type
;
145 tex
->is_array
= false;
146 tex
->is_shadow
= false;
148 /* Blorp only has one texture and it's bound at unit 0 */
149 tex
->texture_index
= 0;
150 tex
->sampler_index
= 0;
152 /* To properly handle 3-D and 2-D array textures, we pull the Z component
153 * from an input. TODO: This is a bit magic; we should probably make this
154 * more explicit in the future.
156 assert(pos
->num_components
>= 2);
157 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
158 nir_load_var(b
, v
->v_src_z
));
160 tex
->src
[0].src_type
= nir_tex_src_coord
;
161 tex
->src
[0].src
= nir_src_for_ssa(pos
);
162 tex
->coord_components
= 3;
164 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
170 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
171 const struct brw_blorp_blit_prog_key
*key
, nir_ssa_def
*pos
)
173 if (key
->need_src_offset
)
174 pos
= nir_fadd(b
, pos
, nir_i2f32(b
, nir_load_var(b
, v
->v_src_offset
)));
176 /* If the sampler requires normalized coordinates, we need to compensate. */
177 if (key
->src_coords_normalized
)
178 pos
= nir_fmul(b
, pos
, nir_load_var(b
, v
->v_src_inv_size
));
181 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2,
182 key
->texture_data_type
);
184 assert(pos
->num_components
== 2);
185 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
186 tex
->src
[1].src_type
= nir_tex_src_lod
;
187 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
189 nir_builder_instr_insert(b
, &tex
->instr
);
191 return &tex
->dest
.ssa
;
195 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
196 nir_ssa_def
*pos
, nir_alu_type dst_type
)
199 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
201 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
202 tex
->src
[1].src_type
= nir_tex_src_lod
;
203 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
205 nir_builder_instr_insert(b
, &tex
->instr
);
207 return &tex
->dest
.ssa
;
211 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
212 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
215 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
216 mcs
!= NULL
? 3 : 2, dst_type
);
218 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
220 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
221 if (pos
->num_components
== 2) {
222 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
224 assert(pos
->num_components
== 3);
225 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
229 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
230 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
233 nir_builder_instr_insert(b
, &tex
->instr
);
235 return &tex
->dest
.ssa
;
239 blorp_blit_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
243 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
244 pos
, 1, nir_type_int
);
246 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
248 nir_builder_instr_insert(b
, &tex
->instr
);
250 return &tex
->dest
.ssa
;
254 * Emit code to compensate for the difference between Y and W tiling.
256 * This code modifies the X and Y coordinates according to the formula:
258 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
260 * (See brw_blorp_build_nir_shader).
262 static inline nir_ssa_def
*
263 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
265 assert(pos
->num_components
== 2);
266 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
267 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
269 /* Given X and Y coordinates that describe an address using Y tiling,
270 * translate to the X and Y coordinates that describe the same address
273 * If we break down the low order bits of X and Y, using a
274 * single letter to represent each low-order bit:
276 * X = A << 7 | 0bBCDEFGH
277 * Y = J << 5 | 0bKLMNP (1)
279 * Then we can apply the Y tiling formula to see the memory offset being
282 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
284 * If we apply the W detiling formula to this memory location, that the
285 * corresponding X' and Y' coordinates are:
287 * X' = A << 6 | 0bBCDPFH (3)
288 * Y' = J << 6 | 0bKLMNEG
290 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
291 * we need to make the following computation:
293 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
294 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
296 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
297 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
298 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
299 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
301 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
302 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
303 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
304 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
306 return nir_vec2(b
, x_W
, y_W
);
310 * Emit code to compensate for the difference between Y and W tiling.
312 * This code modifies the X and Y coordinates according to the formula:
314 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
316 * (See brw_blorp_build_nir_shader).
318 static inline nir_ssa_def
*
319 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
321 assert(pos
->num_components
== 2);
322 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
323 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
325 /* Applying the same logic as above, but in reverse, we obtain the
328 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
329 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
331 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
332 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
333 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
334 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
335 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
337 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
338 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
339 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
341 return nir_vec2(b
, x_Y
, y_Y
);
345 * Emit code to compensate for the difference between MSAA and non-MSAA
348 * This code modifies the X and Y coordinates according to the formula:
350 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
352 * (See brw_blorp_blit_program).
354 static inline nir_ssa_def
*
355 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
356 unsigned num_samples
, enum isl_msaa_layout layout
)
358 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
361 case ISL_MSAA_LAYOUT_NONE
:
362 assert(pos
->num_components
== 2);
364 case ISL_MSAA_LAYOUT_ARRAY
:
365 /* No translation needed */
367 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
368 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
369 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
370 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
371 nir_channel(b
, pos
, 2);
373 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
374 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
375 switch (num_samples
) {
378 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
379 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
382 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
383 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
384 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
386 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
387 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
388 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
389 if (num_samples
== 2) {
392 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
393 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
394 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
399 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
400 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
402 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
404 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
405 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
406 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
407 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
408 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
409 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
410 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
414 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
415 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
417 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
420 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
421 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
422 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
423 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
424 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
425 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
426 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
427 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
431 unreachable("Invalid number of samples for IMS layout");
434 return nir_vec2(b
, x_out
, y_out
);
438 unreachable("Invalid MSAA layout");
443 * Emit code to compensate for the difference between MSAA and non-MSAA
446 * This code modifies the X and Y coordinates according to the formula:
448 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
450 * (See brw_blorp_blit_program).
452 static inline nir_ssa_def
*
453 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
454 unsigned num_samples
, enum isl_msaa_layout layout
)
456 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
459 case ISL_MSAA_LAYOUT_NONE
:
460 /* No translation necessary, and S should already be zero. */
461 assert(pos
->num_components
== 2);
463 case ISL_MSAA_LAYOUT_ARRAY
:
464 /* No translation necessary. */
466 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
467 assert(pos
->num_components
== 2);
469 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
470 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
472 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
473 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
474 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
475 switch (num_samples
) {
478 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
479 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
480 * S = (X & 0b10) >> 1
482 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
483 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
484 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
485 * S = (Y & 0b10) | (X & 0b10) >> 1
487 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
488 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
489 if (num_samples
== 2) {
491 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
493 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
494 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
495 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
496 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
501 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
502 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
503 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
504 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
506 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
507 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
508 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
509 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
510 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
511 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
512 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
516 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
517 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
518 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
519 * S = (Y & 0b100) << 1 | (X & 0b100) |
520 * (Y & 0b10) | (X & 0b10) >> 1
522 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
523 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
524 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
525 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
526 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
527 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
528 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
529 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
533 unreachable("Invalid number of samples for IMS layout");
536 return nir_vec3(b
, x_out
, y_out
, s_out
);
540 unreachable("Invalid MSAA layout");
545 * Count the number of trailing 1 bits in the given value. For example:
547 * count_trailing_one_bits(0) == 0
548 * count_trailing_one_bits(7) == 3
549 * count_trailing_one_bits(11) == 2
551 static inline int count_trailing_one_bits(unsigned value
)
553 #ifdef HAVE___BUILTIN_CTZ
554 return __builtin_ctz(~value
);
556 return util_bitcount(value
& ~(value
+ 1));
561 blorp_nir_combine_samples(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
562 nir_ssa_def
*pos
, unsigned tex_samples
,
563 enum isl_aux_usage tex_aux_usage
,
564 nir_alu_type dst_type
,
565 enum blorp_filter filter
)
567 /* If non-null, this is the outer-most if statement */
568 nir_if
*outer_if
= NULL
;
570 nir_variable
*color
=
571 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
573 nir_ssa_def
*mcs
= NULL
;
574 if (isl_aux_usage_has_mcs(tex_aux_usage
))
575 mcs
= blorp_blit_txf_ms_mcs(b
, v
, pos
);
579 case BLORP_FILTER_AVERAGE
:
580 assert(dst_type
== nir_type_float
);
581 combine_op
= nir_op_fadd
;
584 case BLORP_FILTER_MIN_SAMPLE
:
586 case nir_type_int
: combine_op
= nir_op_imin
; break;
587 case nir_type_uint
: combine_op
= nir_op_umin
; break;
588 case nir_type_float
: combine_op
= nir_op_fmin
; break;
589 default: unreachable("Invalid dst_type");
593 case BLORP_FILTER_MAX_SAMPLE
:
595 case nir_type_int
: combine_op
= nir_op_imax
; break;
596 case nir_type_uint
: combine_op
= nir_op_umax
; break;
597 case nir_type_float
: combine_op
= nir_op_fmax
; break;
598 default: unreachable("Invalid dst_type");
603 unreachable("Invalid filter");
606 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
608 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
610 * This ensures that when all samples have the same value, no numerical
611 * precision is lost, since each addition operation always adds two equal
612 * values, and summing two equal floating point values does not lose
615 * We perform this computation by treating the texture_data array as a
616 * stack and performing the following operations:
618 * - push sample 0 onto stack
619 * - push sample 1 onto stack
620 * - add top two stack entries
621 * - push sample 2 onto stack
622 * - push sample 3 onto stack
623 * - add top two stack entries
624 * - add top two stack entries
625 * - divide top stack entry by 4
627 * Note that after pushing sample i onto the stack, the number of add
628 * operations we do is equal to the number of trailing 1 bits in i. This
629 * works provided the total number of samples is a power of two, which it
630 * always is for i965.
632 * For integer formats, we replace the add operations with average
633 * operations and skip the final division.
635 nir_ssa_def
*texture_data
[5];
636 unsigned stack_depth
= 0;
637 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
638 assert(stack_depth
== util_bitcount(i
)); /* Loop invariant */
640 /* Push sample i onto the stack */
641 assert(stack_depth
< ARRAY_SIZE(texture_data
));
643 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
644 nir_channel(b
, pos
, 1),
646 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
648 if (i
== 0 && isl_aux_usage_has_mcs(tex_aux_usage
)) {
649 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
650 * suggests an optimization:
652 * "A simple optimization with probable large return in
653 * performance is to compare the MCS value to zero (indicating
654 * all samples are on sample slice 0), and sample only from
655 * sample slice 0 using ld2dss if MCS is zero."
657 * Note that in the case where the MCS value is zero, sampling from
658 * sample slice 0 using ld2dss and sampling from sample 0 using
659 * ld2dms are equivalent (since all samples are on sample slice 0).
660 * Since we have already sampled from sample 0, all we need to do is
661 * skip the remaining fetches and averaging if MCS is zero.
663 * It's also trivial to detect when the MCS has the magic clear color
664 * value. In this case, the txf we did on sample 0 will return the
665 * clear color and we can skip the remaining fetches just like we do
668 nir_ssa_def
*mcs_zero
=
669 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
670 if (tex_samples
== 16) {
671 mcs_zero
= nir_iand(b
, mcs_zero
,
672 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
674 nir_ssa_def
*mcs_clear
=
675 blorp_nir_mcs_is_clear_color(b
, mcs
, tex_samples
);
677 nir_if
*if_stmt
= nir_if_create(b
->shader
);
678 if_stmt
->condition
= nir_src_for_ssa(nir_ior(b
, mcs_zero
, mcs_clear
));
679 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
681 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
682 nir_store_var(b
, color
, texture_data
[0], 0xf);
684 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
688 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
689 assert(stack_depth
>= 2);
692 texture_data
[stack_depth
- 1] =
693 nir_build_alu(b
, combine_op
,
694 texture_data
[stack_depth
- 1],
695 texture_data
[stack_depth
],
700 /* We should have just 1 sample on the stack now. */
701 assert(stack_depth
== 1);
703 if (filter
== BLORP_FILTER_AVERAGE
) {
704 assert(dst_type
== nir_type_float
);
705 texture_data
[0] = nir_fmul(b
, texture_data
[0],
706 nir_imm_float(b
, 1.0 / tex_samples
));
709 nir_store_var(b
, color
, texture_data
[0], 0xf);
712 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
714 return nir_load_var(b
, color
);
718 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
719 unsigned tex_samples
,
720 const struct brw_blorp_blit_prog_key
*key
,
721 struct brw_blorp_blit_vars
*v
)
723 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
724 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
725 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
727 /* Translate coordinates to lay out the samples in a rectangular grid
728 * roughly corresponding to sample locations.
730 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
731 /* Adjust coordinates so that integers represent pixel centers rather
734 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
735 /* Clamp the X, Y texture coordinates to properly handle the sampling of
736 * texels on texture edges.
738 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
739 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
740 nir_channel(b
, rect_grid
, 1)));
742 /* Store the fractional parts to be used as bilinear interpolation
745 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
746 /* Round the float coordinates down to nearest integer */
747 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
749 nir_ssa_def
*tex_data
[4];
750 for (unsigned i
= 0; i
< 4; ++i
) {
751 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
752 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
753 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
755 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
756 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
758 /* The MCS value we fetch has to match up with the pixel that we're
759 * sampling from. Since we sample from different pixels in each
760 * iteration of this "for" loop, the call to mcs_fetch() should be
761 * here inside the loop after computing the pixel coordinates.
763 nir_ssa_def
*mcs
= NULL
;
764 if (isl_aux_usage_has_mcs(key
->tex_aux_usage
))
765 mcs
= blorp_blit_txf_ms_mcs(b
, v
, sample_coords_int
);
767 /* Compute sample index and map the sample index to a sample number.
768 * Sample index layout shows the numbering of slots in a rectangular
769 * grid of samples with in a pixel. Sample number layout shows the
770 * rectangular grid of samples roughly corresponding to the real sample
771 * locations with in a pixel.
773 * In the case of 2x MSAA, the layout of sample indices is reversed from
774 * the layout of sample numbers:
776 * sample index layout : --------- sample number layout : ---------
777 * | 0 | 1 | | 1 | 0 |
778 * --------- ---------
780 * In case of 4x MSAA, layout of sample indices matches the layout of
788 * In case of 8x MSAA the two layouts don't match.
789 * sample index layout : --------- sample number layout : ---------
790 * | 0 | 1 | | 3 | 7 |
791 * --------- ---------
792 * | 2 | 3 | | 5 | 0 |
793 * --------- ---------
794 * | 4 | 5 | | 1 | 2 |
795 * --------- ---------
796 * | 6 | 7 | | 4 | 6 |
797 * --------- ---------
799 * Fortunately, this can be done fairly easily as:
800 * S' = (0x17306425 >> (S * 4)) & 0xf
802 * In the case of 16x MSAA the two layouts don't match.
803 * Sample index layout: Sample number layout:
804 * --------------------- ---------------------
805 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
806 * --------------------- ---------------------
807 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
808 * --------------------- ---------------------
809 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
810 * --------------------- ---------------------
811 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
812 * --------------------- ---------------------
814 * This is equivalent to
815 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
817 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
818 nir_ssa_def
*sample
=
819 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
820 key
->x_scale
* key
->y_scale
));
821 sample
= nir_f2i32(b
, sample
);
823 if (tex_samples
== 2) {
824 sample
= nir_isub(b
, nir_imm_int(b
, 1), sample
);
825 } else if (tex_samples
== 8) {
826 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
827 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
828 nir_imm_int(b
, 0xf));
829 } else if (tex_samples
== 16) {
830 nir_ssa_def
*sample_low
=
831 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
832 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
833 nir_imm_int(b
, 0xf));
834 nir_ssa_def
*sample_high
=
835 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
836 nir_ishl(b
, nir_iadd(b
, sample
,
839 nir_imm_int(b
, 0xf));
841 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
842 sample_low
, sample_high
);
844 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
845 nir_channel(b
, sample_coords_int
, 1),
847 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
850 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
851 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
852 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
853 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
857 /** Perform a color bit-cast operation
859 * For copy operations involving CCS, we may need to use different formats for
860 * the source and destination surfaces. The two formats must both be UINT
861 * formats and must have the same size but may have different bit layouts.
862 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
863 * to R16G16_UINT. This function generates code to shuffle bits around to get
864 * us from one to the other.
867 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
868 const struct brw_blorp_blit_prog_key
*key
)
870 if (key
->src_format
== key
->dst_format
)
873 const struct isl_format_layout
*src_fmtl
=
874 isl_format_get_layout(key
->src_format
);
875 const struct isl_format_layout
*dst_fmtl
=
876 isl_format_get_layout(key
->dst_format
);
878 /* They must be formats with the same bit size */
879 assert(src_fmtl
->bpb
== dst_fmtl
->bpb
);
881 if (src_fmtl
->bpb
<= 32) {
882 assert(src_fmtl
->channels
.r
.type
== ISL_UINT
||
883 src_fmtl
->channels
.r
.type
== ISL_UNORM
);
884 assert(dst_fmtl
->channels
.r
.type
== ISL_UINT
||
885 dst_fmtl
->channels
.r
.type
== ISL_UNORM
);
887 nir_ssa_def
*packed
= nir_imm_int(b
, 0);
888 for (unsigned c
= 0; c
< 4; c
++) {
889 if (src_fmtl
->channels_array
[c
].bits
== 0)
892 const unsigned chan_start_bit
= src_fmtl
->channels_array
[c
].start_bit
;
893 const unsigned chan_bits
= src_fmtl
->channels_array
[c
].bits
;
895 nir_ssa_def
*chan
= nir_channel(b
, color
, c
);
896 if (src_fmtl
->channels_array
[c
].type
== ISL_UNORM
)
897 chan
= nir_format_float_to_unorm(b
, chan
, &chan_bits
);
899 packed
= nir_ior(b
, packed
, nir_shift(b
, chan
, chan_start_bit
));
902 nir_ssa_def
*chans
[4] = { };
903 for (unsigned c
= 0; c
< 4; c
++) {
904 if (dst_fmtl
->channels_array
[c
].bits
== 0) {
905 chans
[c
] = nir_imm_int(b
, 0);
909 const unsigned chan_start_bit
= dst_fmtl
->channels_array
[c
].start_bit
;
910 const unsigned chan_bits
= dst_fmtl
->channels_array
[c
].bits
;
911 chans
[c
] = nir_iand(b
, nir_shift(b
, packed
, -(int)chan_start_bit
),
912 nir_imm_int(b
, BITFIELD_MASK(chan_bits
)));
914 if (dst_fmtl
->channels_array
[c
].type
== ISL_UNORM
)
915 chans
[c
] = nir_format_unorm_to_float(b
, chans
[c
], &chan_bits
);
917 color
= nir_vec(b
, chans
, 4);
919 /* This path only supports UINT formats */
920 assert(src_fmtl
->channels
.r
.type
== ISL_UINT
);
921 assert(dst_fmtl
->channels
.r
.type
== ISL_UINT
);
923 const unsigned src_bpc
= src_fmtl
->channels
.r
.bits
;
924 const unsigned dst_bpc
= dst_fmtl
->channels
.r
.bits
;
926 assert(src_fmtl
->channels
.g
.bits
== 0 ||
927 src_fmtl
->channels
.g
.bits
== src_fmtl
->channels
.r
.bits
);
928 assert(src_fmtl
->channels
.b
.bits
== 0 ||
929 src_fmtl
->channels
.b
.bits
== src_fmtl
->channels
.r
.bits
);
930 assert(src_fmtl
->channels
.a
.bits
== 0 ||
931 src_fmtl
->channels
.a
.bits
== src_fmtl
->channels
.r
.bits
);
932 assert(dst_fmtl
->channels
.g
.bits
== 0 ||
933 dst_fmtl
->channels
.g
.bits
== dst_fmtl
->channels
.r
.bits
);
934 assert(dst_fmtl
->channels
.b
.bits
== 0 ||
935 dst_fmtl
->channels
.b
.bits
== dst_fmtl
->channels
.r
.bits
);
936 assert(dst_fmtl
->channels
.a
.bits
== 0 ||
937 dst_fmtl
->channels
.a
.bits
== dst_fmtl
->channels
.r
.bits
);
939 /* Restrict to only the channels we actually have */
940 const unsigned src_channels
=
941 isl_format_get_num_channels(key
->src_format
);
942 color
= nir_channels(b
, color
, (1 << src_channels
) - 1);
944 color
= nir_format_bitcast_uvec_unmasked(b
, color
, src_bpc
, dst_bpc
);
947 /* Blorp likes to assume that colors are vec4s */
948 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
949 nir_ssa_def
*chans
[4] = { u
, u
, u
, u
};
950 for (unsigned i
= 0; i
< color
->num_components
; i
++)
951 chans
[i
] = nir_channel(b
, color
, i
);
952 return nir_vec4(b
, chans
[0], chans
[1], chans
[2], chans
[3]);
956 select_color_channel(struct nir_builder
*b
, nir_ssa_def
*color
,
957 nir_alu_type data_type
,
958 enum isl_channel_select chan
)
960 if (chan
== ISL_CHANNEL_SELECT_ZERO
) {
961 return nir_imm_int(b
, 0);
962 } else if (chan
== ISL_CHANNEL_SELECT_ONE
) {
966 return nir_imm_int(b
, 1);
968 return nir_imm_float(b
, 1);
970 unreachable("Invalid data type");
973 assert((unsigned)(chan
- ISL_CHANNEL_SELECT_RED
) < 4);
974 return nir_channel(b
, color
, chan
- ISL_CHANNEL_SELECT_RED
);
979 swizzle_color(struct nir_builder
*b
, nir_ssa_def
*color
,
980 struct isl_swizzle swizzle
, nir_alu_type data_type
)
983 select_color_channel(b
, color
, data_type
, swizzle
.r
),
984 select_color_channel(b
, color
, data_type
, swizzle
.g
),
985 select_color_channel(b
, color
, data_type
, swizzle
.b
),
986 select_color_channel(b
, color
, data_type
, swizzle
.a
));
990 convert_color(struct nir_builder
*b
, nir_ssa_def
*color
,
991 const struct brw_blorp_blit_prog_key
*key
)
993 /* All of our color conversions end up generating a single-channel color
994 * value that we need to write out.
998 if (key
->dst_format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
999 /* The destination image is bound as R32_UINT but the data needs to be
1000 * in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and the
1001 * top 8 need to be zero. We can accomplish this by simply multiplying
1002 * by a factor to scale things down.
1004 unsigned factor
= (1 << 24) - 1;
1005 value
= nir_fsat(b
, nir_channel(b
, color
, 0));
1006 value
= nir_f2i32(b
, nir_fmul(b
, value
, nir_imm_float(b
, factor
)));
1007 } else if (key
->dst_format
== ISL_FORMAT_L8_UNORM_SRGB
) {
1008 value
= nir_format_linear_to_srgb(b
, nir_channel(b
, color
, 0));
1009 } else if (key
->dst_format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
) {
1010 value
= nir_format_linear_to_srgb(b
, color
);
1011 } else if (key
->dst_format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
1012 value
= nir_format_pack_r9g9b9e5(b
, color
);
1014 unreachable("Unsupported format conversion");
1017 nir_ssa_def
*out_comps
[4];
1018 for (unsigned i
= 0; i
< 4; i
++) {
1019 if (i
< value
->num_components
)
1020 out_comps
[i
] = nir_channel(b
, value
, i
);
1022 out_comps
[i
] = nir_ssa_undef(b
, 1, 32);
1024 return nir_vec(b
, out_comps
, 4);
1028 * Generator for WM programs used in BLORP blits.
1030 * The bulk of the work done by the WM program is to wrap and unwrap the
1031 * coordinate transformations used by the hardware to store surfaces in
1032 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
1033 * sample index for a multisampled surface) to a memory offset by the
1034 * following formulas:
1036 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
1037 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
1039 * For a single-sampled surface, or for a multisampled surface using
1040 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
1043 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1044 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1045 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1046 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1048 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1049 * embeds the sample number into bit 1 of the X and Y coordinates:
1051 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1052 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1053 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
1054 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1055 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1056 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1057 * S = (Y & 0b10) | (X & 0b10) >> 1
1059 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1060 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
1063 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1064 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
1065 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1066 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1067 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1068 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1069 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1071 * For X tiling, tile() combines together the low-order bits of the X and Y
1072 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
1073 * bytes wide and 8 rows high:
1075 * tile(x_tiled, X, Y, S) = A
1076 * where A = tile_num << 12 | offset
1077 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
1078 * offset = (Y' & 0b111) << 9
1079 * | (X & 0b111111111)
1081 * Y' = Y + S * qpitch
1082 * detile(x_tiled, A) = (X, Y, S)
1083 * where X = X' / cpp
1086 * Y' = (tile_num / tile_pitch) << 3
1087 * | (A & 0b111000000000) >> 9
1088 * X' = (tile_num % tile_pitch) << 9
1089 * | (A & 0b111111111)
1091 * (In all tiling formulas, cpp is the number of bytes occupied by a single
1092 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
1093 * to fill the width of the surface, and qpitch is the spacing (in rows)
1094 * between array slices).
1096 * For Y tiling, tile() combines together the low-order bits of the X and Y
1097 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
1098 * bytes wide and 32 rows high:
1100 * tile(y_tiled, X, Y, S) = A
1101 * where A = tile_num << 12 | offset
1102 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
1103 * offset = (X' & 0b1110000) << 5
1104 * | (Y' & 0b11111) << 4
1107 * Y' = Y + S * qpitch
1108 * detile(y_tiled, A) = (X, Y, S)
1109 * where X = X' / cpp
1112 * Y' = (tile_num / tile_pitch) << 5
1113 * | (A & 0b111110000) >> 4
1114 * X' = (tile_num % tile_pitch) << 7
1115 * | (A & 0b111000000000) >> 5
1118 * For W tiling, tile() combines together the low-order bits of the X and Y
1119 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1120 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1121 * buffers, which always have cpp = 1 and S=0):
1123 * tile(w_tiled, X, Y, S) = A
1124 * where A = tile_num << 12 | offset
1125 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1126 * offset = (X' & 0b111000) << 6
1127 * | (Y' & 0b111100) << 3
1128 * | (X' & 0b100) << 2
1129 * | (Y' & 0b10) << 2
1130 * | (X' & 0b10) << 1
1134 * Y' = Y + S * qpitch
1135 * detile(w_tiled, A) = (X, Y, S)
1136 * where X = X' / cpp = X'
1137 * Y = Y' % qpitch = Y'
1138 * S = Y / qpitch = 0
1139 * Y' = (tile_num / tile_pitch) << 6
1140 * | (A & 0b111100000) >> 3
1141 * | (A & 0b1000) >> 2
1143 * X' = (tile_num % tile_pitch) << 6
1144 * | (A & 0b111000000000) >> 6
1145 * | (A & 0b10000) >> 2
1146 * | (A & 0b100) >> 1
1149 * Finally, for a non-tiled surface, tile() simply combines together the X and
1150 * Y coordinates in the natural way:
1152 * tile(untiled, X, Y, S) = A
1153 * where A = Y * pitch + X'
1155 * Y' = Y + S * qpitch
1156 * detile(untiled, A) = (X, Y, S)
1157 * where X = X' / cpp
1163 * (In these formulas, pitch is the number of bytes occupied by a single row
1167 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1168 const struct brw_blorp_blit_prog_key
*key
)
1170 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1171 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1174 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1175 /* If the destination image is W tiled and multisampled, then the thread
1176 * must be dispatched once per sample, not once per pixel. This is
1177 * necessary because after conversion between W and Y tiling, there's no
1178 * guarantee that all samples corresponding to a single pixel will still
1181 assert(key
->persample_msaa_dispatch
);
1184 if (key
->persample_msaa_dispatch
) {
1185 /* It only makes sense to do persample dispatch if the render target is
1186 * configured as multisampled.
1188 assert(key
->rt_samples
> 0);
1191 /* Make sure layout is consistent with sample count */
1192 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1193 (key
->tex_samples
<= 1));
1194 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1195 (key
->rt_samples
<= 1));
1196 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1197 (key
->src_samples
<= 1));
1198 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1199 (key
->dst_samples
<= 1));
1202 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1204 struct brw_blorp_blit_vars v
;
1205 brw_blorp_blit_vars_init(&b
, &v
, key
);
1207 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1209 /* Render target and texture hardware don't support W tiling until Gen8. */
1210 const bool rt_tiled_w
= false;
1211 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1213 /* The address that data will be written to is determined by the
1214 * coordinates supplied to the WM thread and the tiling and sample count of
1215 * the render target, according to the formula:
1217 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1219 * If the actual tiling and sample count of the destination surface are not
1220 * the same as the configuration of the render target, then these
1221 * coordinates are wrong and we have to adjust them to compensate for the
1224 if (rt_tiled_w
!= key
->dst_tiled_w
||
1225 key
->rt_samples
!= key
->dst_samples
||
1226 key
->rt_layout
!= key
->dst_layout
) {
1227 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1229 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1230 if (rt_tiled_w
!= key
->dst_tiled_w
)
1231 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1232 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1233 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1237 nir_ssa_def
*comp
= NULL
;
1239 /* The destination image is bound as a red texture three times as wide
1240 * as the actual image. Our shader is effectively running one color
1241 * component at a time. We need to save off the component and adjust
1242 * the destination position.
1244 assert(dst_pos
->num_components
== 2);
1245 nir_ssa_def
*dst_x
= nir_channel(&b
, dst_pos
, 0);
1246 comp
= nir_umod(&b
, dst_x
, nir_imm_int(&b
, 3));
1247 dst_pos
= nir_vec2(&b
, nir_idiv(&b
, dst_x
, nir_imm_int(&b
, 3)),
1248 nir_channel(&b
, dst_pos
, 1));
1251 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1253 * That is: X, Y and S now contain the true coordinates and sample index of
1254 * the data that the WM thread should output.
1256 * If we need to kill pixels that are outside the destination rectangle,
1257 * now is the time to do it.
1260 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1262 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1263 if (dst_pos
->num_components
== 3) {
1264 /* The sample coordinate is an integer that we want left alone but
1265 * blorp_blit_apply_transform() blindly applies the transform to all
1266 * three coordinates. Grab the original sample index.
1268 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1269 nir_channel(&b
, src_pos
, 1),
1270 nir_channel(&b
, dst_pos
, 2));
1273 /* If the source image is not multisampled, then we want to fetch sample
1274 * number 0, because that's the only sample there is.
1276 if (key
->src_samples
== 1)
1277 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1279 /* X, Y, and S are now the coordinates of the pixel in the source image
1280 * that we want to texture from. Exception: if we are blending, then S is
1281 * irrelevant, because we are going to fetch all samples.
1283 switch (key
->filter
) {
1284 case BLORP_FILTER_NONE
:
1285 case BLORP_FILTER_NEAREST
:
1286 case BLORP_FILTER_SAMPLE_0
:
1287 /* We're going to use texelFetch, so we need integers */
1288 if (src_pos
->num_components
== 2) {
1289 src_pos
= nir_f2i32(&b
, src_pos
);
1291 assert(src_pos
->num_components
== 3);
1292 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1293 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1294 nir_channel(&b
, src_pos
, 2));
1297 /* We aren't blending, which means we just want to fetch a single
1298 * sample from the source surface. The address that we want to fetch
1299 * from is related to the X, Y and S values according to the formula:
1301 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1303 * If the actual tiling and sample count of the source surface are
1304 * not the same as the configuration of the texture, then we need to
1305 * adjust the coordinates to compensate for the difference.
1307 if (tex_tiled_w
!= key
->src_tiled_w
||
1308 key
->tex_samples
!= key
->src_samples
||
1309 key
->tex_layout
!= key
->src_layout
) {
1310 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1312 /* Now (X, Y, S) = detile(src_tiling, offset) */
1313 if (tex_tiled_w
!= key
->src_tiled_w
)
1314 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1315 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1316 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1320 if (key
->need_src_offset
)
1321 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1323 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1325 * In other words: X, Y, and S now contain values which, when passed to
1326 * the texturing unit, will cause data to be read from the correct
1327 * memory location. So we can fetch the texel now.
1329 if (key
->src_samples
== 1) {
1330 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1332 nir_ssa_def
*mcs
= NULL
;
1333 if (isl_aux_usage_has_mcs(key
->tex_aux_usage
))
1334 mcs
= blorp_blit_txf_ms_mcs(&b
, &v
, src_pos
);
1336 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1340 case BLORP_FILTER_BILINEAR
:
1341 assert(!key
->src_tiled_w
);
1342 assert(key
->tex_samples
== key
->src_samples
);
1343 assert(key
->tex_layout
== key
->src_layout
);
1345 if (key
->src_samples
== 1) {
1346 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1348 assert(!key
->use_kill
);
1349 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
,
1354 case BLORP_FILTER_AVERAGE
:
1355 case BLORP_FILTER_MIN_SAMPLE
:
1356 case BLORP_FILTER_MAX_SAMPLE
:
1357 assert(!key
->src_tiled_w
);
1358 assert(key
->tex_samples
== key
->src_samples
);
1359 assert(key
->tex_layout
== key
->src_layout
);
1361 /* Resolves (effecively) use texelFetch, so we need integers and we
1362 * don't care about the sample index if we got one.
1364 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1366 if (devinfo
->gen
== 6) {
1367 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1368 * blending we need with a single linear-interpolated texture lookup
1369 * at the center of the sample. The texture coordinates to be odd
1370 * integers so that they correspond to the center of a 2x2 block
1371 * representing the four samples that maxe up a pixel. So we need
1372 * to multiply our X and Y coordinates each by 2 and then add 1.
1374 assert(key
->src_coords_normalized
);
1375 assert(key
->filter
== BLORP_FILTER_AVERAGE
);
1376 src_pos
= nir_fadd(&b
,
1377 nir_i2f32(&b
, src_pos
),
1378 nir_imm_float(&b
, 0.5f
));
1379 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1381 /* Gen7+ hardware doesn't automaticaly blend. */
1382 color
= blorp_nir_combine_samples(&b
, &v
, src_pos
, key
->src_samples
,
1384 key
->texture_data_type
,
1390 unreachable("Invalid blorp filter");
1393 if (!isl_swizzle_is_identity(key
->src_swizzle
)) {
1394 color
= swizzle_color(&b
, color
, key
->src_swizzle
,
1395 key
->texture_data_type
);
1398 if (!isl_swizzle_is_identity(key
->dst_swizzle
)) {
1399 color
= swizzle_color(&b
, color
, isl_swizzle_invert(key
->dst_swizzle
),
1403 if (key
->format_bit_cast
) {
1404 assert(isl_swizzle_is_identity(key
->src_swizzle
));
1405 assert(isl_swizzle_is_identity(key
->dst_swizzle
));
1406 color
= bit_cast_color(&b
, color
, key
);
1407 } else if (key
->dst_format
) {
1408 color
= convert_color(&b
, color
, key
);
1409 } else if (key
->uint32_to_sint
) {
1410 /* Normally the hardware will take care of converting values from/to
1411 * the source and destination formats. But a few cases need help.
1413 * The Skylake PRM, volume 07, page 658 has a programming note:
1415 * "When using SINT or UINT rendertarget surface formats, Blending
1416 * must be DISABLED. The Pre-Blend Color Clamp Enable and Color
1417 * Clamp Range fields are ignored, and an implied clamp to the
1418 * rendertarget surface format is performed."
1420 * For UINT to SINT blits, our sample operation gives us a uint32_t,
1421 * but our render target write expects a signed int32_t number. If we
1422 * simply passed the value along, the hardware would interpret a value
1423 * with bit 31 set as a negative value, clamping it to the largest
1424 * negative number the destination format could represent. But the
1425 * actual source value is a positive number, so we want to clamp it
1426 * to INT_MAX. To fix this, we explicitly take min(color, INT_MAX).
1428 color
= nir_umin(&b
, color
, nir_imm_int(&b
, INT32_MAX
));
1429 } else if (key
->sint32_to_uint
) {
1430 /* Similar to above, but clamping negative numbers to zero. */
1431 color
= nir_imax(&b
, color
, nir_imm_int(&b
, 0));
1435 /* The destination image is bound as a red texture three times as wide
1436 * as the actual image. Our shader is effectively running one color
1437 * component at a time. We need to pick off the appropriate component
1438 * from the source color and write that to destination red.
1440 assert(dst_pos
->num_components
== 2);
1442 nir_ssa_def
*color_component
=
1443 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1444 nir_channel(&b
, color
, 0),
1445 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1446 nir_channel(&b
, color
, 1),
1447 nir_channel(&b
, color
, 2)));
1449 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1450 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1453 if (key
->dst_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1454 nir_variable
*color_out
=
1455 nir_variable_create(b
.shader
, nir_var_shader_out
,
1456 glsl_vec4_type(), "gl_FragColor");
1457 color_out
->data
.location
= FRAG_RESULT_COLOR
;
1458 nir_store_var(&b
, color_out
, color
, 0xf);
1459 } else if (key
->dst_usage
== ISL_SURF_USAGE_DEPTH_BIT
) {
1460 nir_variable
*depth_out
=
1461 nir_variable_create(b
.shader
, nir_var_shader_out
,
1462 glsl_float_type(), "gl_FragDepth");
1463 depth_out
->data
.location
= FRAG_RESULT_DEPTH
;
1464 nir_store_var(&b
, depth_out
, nir_channel(&b
, color
, 0), 0x1);
1465 } else if (key
->dst_usage
== ISL_SURF_USAGE_STENCIL_BIT
) {
1466 nir_variable
*stencil_out
=
1467 nir_variable_create(b
.shader
, nir_var_shader_out
,
1468 glsl_int_type(), "gl_FragStencilRef");
1469 stencil_out
->data
.location
= FRAG_RESULT_STENCIL
;
1470 nir_store_var(&b
, stencil_out
, nir_channel(&b
, color
, 0), 0x1);
1472 unreachable("Invalid destination usage");
1479 brw_blorp_get_blit_kernel(struct blorp_batch
*batch
,
1480 struct blorp_params
*params
,
1481 const struct brw_blorp_blit_prog_key
*prog_key
)
1483 struct blorp_context
*blorp
= batch
->blorp
;
1485 if (blorp
->lookup_shader(batch
, prog_key
, sizeof(*prog_key
),
1486 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1489 void *mem_ctx
= ralloc_context(NULL
);
1491 const unsigned *program
;
1492 struct brw_wm_prog_data prog_data
;
1494 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1495 nir
->info
.name
= ralloc_strdup(nir
, "BLORP-blit");
1497 struct brw_wm_prog_key wm_key
;
1498 brw_blorp_init_wm_prog_key(&wm_key
);
1499 wm_key
.base
.tex
.compressed_multisample_layout_mask
=
1500 isl_aux_usage_has_mcs(prog_key
->tex_aux_usage
);
1501 wm_key
.base
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1502 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1504 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1508 blorp
->upload_shader(batch
, MESA_SHADER_FRAGMENT
,
1509 prog_key
, sizeof(*prog_key
),
1510 program
, prog_data
.base
.program_size
,
1511 &prog_data
.base
, sizeof(prog_data
),
1512 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1514 ralloc_free(mem_ctx
);
1519 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1520 GLfloat src0
, GLfloat src1
,
1521 GLfloat dst0
, GLfloat dst1
,
1524 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1526 /* When not mirroring a coordinate (say, X), we need:
1527 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1529 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1531 * blorp program uses "round toward zero" to convert the
1532 * transformed floating point coordinates to integer coordinates,
1533 * whereas the behaviour we actually want is "round to nearest",
1534 * so 0.5 provides the necessary correction.
1536 xform
->multiplier
= scale
;
1537 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1539 /* When mirroring X we need:
1540 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1542 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1544 xform
->multiplier
= -scale
;
1545 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1550 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1551 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1553 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1554 struct isl_extent2d px_size_sa
=
1555 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1556 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1557 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1558 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1559 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1561 *tile_x_px
= info
->tile_x_sa
;
1562 *tile_y_px
= info
->tile_y_sa
;
1567 blorp_surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1568 struct brw_blorp_surface_info
*info
)
1572 /* It would be insane to try and do this on a compressed surface */
1573 assert(info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1575 /* Just bail if we have nothing to do. */
1576 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1577 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1578 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1581 /* If this gets triggered then we've gotten here twice which. This
1582 * shouldn't happen thanks to the above early return.
1584 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1586 uint32_t layer
= 0, z
= 0;
1587 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1588 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1590 layer
= info
->view
.base_array_layer
;
1592 uint32_t byte_offset
;
1593 isl_surf_get_image_surf(isl_dev
, &info
->surf
,
1594 info
->view
.base_level
, layer
, z
,
1596 &byte_offset
, &info
->tile_x_sa
, &info
->tile_y_sa
);
1597 info
->addr
.offset
+= byte_offset
;
1599 uint32_t tile_x_px
, tile_y_px
;
1600 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1602 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we place
1603 * the image at the tile boundary and offset our sampling or rendering.
1604 * For this reason, we need to grow the image by the offset to ensure that
1605 * the hardware doesn't think we've gone past the edge.
1607 info
->surf
.logical_level0_px
.w
+= tile_x_px
;
1608 info
->surf
.logical_level0_px
.h
+= tile_y_px
;
1609 info
->surf
.phys_level0_sa
.w
+= info
->tile_x_sa
;
1610 info
->surf
.phys_level0_sa
.h
+= info
->tile_y_sa
;
1612 /* The view is also different now. */
1613 info
->view
.base_level
= 0;
1614 info
->view
.levels
= 1;
1615 info
->view
.base_array_layer
= 0;
1616 info
->view
.array_len
= 1;
1621 blorp_surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1622 struct brw_blorp_surface_info
*info
)
1624 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1626 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1627 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1629 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1630 info
->surf
.samples
= 1;
1631 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1635 blorp_surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1636 struct brw_blorp_surface_info
*info
)
1638 assert(info
->surf
.tiling
== ISL_TILING_W
);
1640 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1641 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1643 /* On gen7+, we don't have interleaved multisampling for color render
1644 * targets so we have to fake it.
1646 * TODO: Are we sure we don't also need to fake it on gen6?
1648 if (isl_dev
->info
->gen
> 6 &&
1649 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1650 blorp_surf_fake_interleaved_msaa(isl_dev
, info
);
1653 if (isl_dev
->info
->gen
== 6) {
1654 /* Gen6 stencil buffers have a very large alignment coming in from the
1655 * miptree. It's out-of-bounds for what the surface state can handle.
1656 * Since we have a single layer and level, it doesn't really matter as
1657 * long as we don't pass a bogus value into isl_surf_fill_state().
1659 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1662 /* Now that we've converted everything to a simple 2-D surface with only
1663 * one miplevel, we can go about retiling it.
1665 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1666 info
->surf
.tiling
= ISL_TILING_Y0
;
1667 info
->surf
.logical_level0_px
.width
=
1668 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1669 info
->surf
.logical_level0_px
.height
=
1670 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1671 info
->tile_x_sa
*= 2;
1672 info
->tile_y_sa
/= 2;
1676 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1678 /* The current code doesn't support offsets into the aux buffers. This
1679 * should be possible, but we need to make sure the offset is page
1680 * aligned for both the surface and the aux buffer surface. Generally
1681 * this mean using the page aligned offset for the aux buffer.
1683 * Currently the cases where we must split the blit are limited to cases
1684 * where we don't have a aux buffer.
1686 if (surf
->aux_addr
.buffer
!= NULL
)
1689 /* We can't support splitting the blit for gen <= 7, because the qpitch
1690 * size is calculated by the hardware based on the surface height for
1691 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1693 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1700 get_max_surface_size(const struct gen_device_info
*devinfo
,
1701 const struct brw_blorp_surface_info
*surf
)
1703 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1704 if (split_blorp_blit_debug
&& can_shrink_surface(surf
))
1705 return max
>> 4; /* A smaller restriction when debug is enabled */
1711 double src0
, src1
, dst0
, dst1
;
1716 struct blt_axis x
, y
;
1719 static enum isl_format
1720 get_red_format_for_rgb_format(enum isl_format format
)
1722 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1724 switch (fmtl
->channels
.r
.bits
) {
1726 switch (fmtl
->channels
.r
.type
) {
1728 return ISL_FORMAT_R8_UNORM
;
1730 return ISL_FORMAT_R8_SNORM
;
1732 return ISL_FORMAT_R8_UINT
;
1734 return ISL_FORMAT_R8_SINT
;
1736 unreachable("Invalid 8-bit RGB channel type");
1739 switch (fmtl
->channels
.r
.type
) {
1741 return ISL_FORMAT_R16_UNORM
;
1743 return ISL_FORMAT_R16_SNORM
;
1745 return ISL_FORMAT_R16_FLOAT
;
1747 return ISL_FORMAT_R16_UINT
;
1749 return ISL_FORMAT_R16_SINT
;
1751 unreachable("Invalid 8-bit RGB channel type");
1754 switch (fmtl
->channels
.r
.type
) {
1756 return ISL_FORMAT_R32_FLOAT
;
1758 return ISL_FORMAT_R32_UINT
;
1760 return ISL_FORMAT_R32_SINT
;
1762 unreachable("Invalid 8-bit RGB channel type");
1765 unreachable("Invalid number of red channel bits");
1770 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1771 struct brw_blorp_surface_info
*info
)
1773 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1775 info
->surf
.logical_level0_px
.width
*= 3;
1776 info
->surf
.phys_level0_sa
.width
*= 3;
1777 info
->tile_x_sa
*= 3;
1779 enum isl_format red_format
=
1780 get_red_format_for_rgb_format(info
->view
.format
);
1782 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1783 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1784 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1785 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1787 info
->surf
.format
= info
->view
.format
= red_format
;
1790 enum blit_shrink_status
{
1792 BLIT_SRC_WIDTH_SHRINK
= (1 << 0),
1793 BLIT_DST_WIDTH_SHRINK
= (1 << 1),
1794 BLIT_SRC_HEIGHT_SHRINK
= (1 << 2),
1795 BLIT_DST_HEIGHT_SHRINK
= (1 << 3),
1798 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1799 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1800 * returned, then the blit was successful.
1802 static enum blit_shrink_status
1803 try_blorp_blit(struct blorp_batch
*batch
,
1804 struct blorp_params
*params
,
1805 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1806 struct blt_coords
*coords
)
1808 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1810 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
1811 if (devinfo
->gen
>= 7) {
1812 /* We can render as depth on Gen5 but there's no real advantage since
1813 * it doesn't support MSAA or HiZ. On Gen4, we can't always render
1814 * to depth due to issues with depth buffers and mip-mapping. On
1815 * Gen6, we can do everything but we have weird offsetting for HiZ
1816 * and stencil. It's easier to just render using the color pipe
1817 * on those platforms.
1819 wm_prog_key
->dst_usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1821 wm_prog_key
->dst_usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1823 } else if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
1824 assert(params
->dst
.surf
.format
== ISL_FORMAT_R8_UINT
);
1825 if (devinfo
->gen
>= 9) {
1826 wm_prog_key
->dst_usage
= ISL_SURF_USAGE_STENCIL_BIT
;
1828 wm_prog_key
->dst_usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1831 wm_prog_key
->dst_usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1834 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1835 wm_prog_key
->texture_data_type
= nir_type_int
;
1836 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1837 wm_prog_key
->texture_data_type
= nir_type_uint
;
1839 wm_prog_key
->texture_data_type
= nir_type_float
;
1842 /* src_samples and dst_samples are the true sample counts */
1843 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1844 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1846 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1848 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1851 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1852 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1854 /* Round floating point values to nearest integer to avoid "off by one texel"
1855 * kind of errors when blitting.
1857 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1858 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1859 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1860 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1862 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1863 coords
->x
.src0
, coords
->x
.src1
,
1864 coords
->x
.dst0
, coords
->x
.dst1
,
1866 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1867 coords
->y
.src0
, coords
->y
.src1
,
1868 coords
->y
.dst0
, coords
->y
.dst1
,
1872 if (devinfo
->gen
== 4) {
1873 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
1874 * Convert them to a single slice on gen4.
1876 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1877 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1878 wm_prog_key
->need_dst_offset
= true;
1881 if (params
->src
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1882 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->src
);
1883 wm_prog_key
->need_src_offset
= true;
1887 if (devinfo
->gen
> 6 &&
1888 !isl_surf_usage_is_depth_or_stencil(wm_prog_key
->dst_usage
) &&
1889 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1890 assert(params
->dst
.surf
.samples
> 1);
1892 /* We must expand the rectangle we send through the rendering pipeline,
1893 * to account for the fact that we are mapping the destination region as
1894 * single-sampled when it is in fact multisampled. We must also align
1895 * it to a multiple of the multisampling pattern, because the
1896 * differences between multisampled and single-sampled surface formats
1897 * will mean that pixels are scrambled within the multisampling pattern.
1898 * TODO: what if this makes the coordinates too large?
1900 * Note: this only works if the destination surface uses the IMS layout.
1901 * If it's UMS, then we have no choice but to set up the rendering
1902 * pipeline as multisampled.
1904 struct isl_extent2d px_size_sa
=
1905 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1906 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1907 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1908 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1909 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1911 blorp_surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1913 wm_prog_key
->use_kill
= true;
1914 wm_prog_key
->need_dst_offset
= true;
1917 if (params
->dst
.surf
.tiling
== ISL_TILING_W
&&
1918 wm_prog_key
->dst_usage
!= ISL_SURF_USAGE_STENCIL_BIT
) {
1919 /* We must modify the rectangle we send through the rendering pipeline
1920 * (and the size and x/y offset of the destination surface), to account
1921 * for the fact that we are mapping it as Y-tiled when it is in fact
1924 * Both Y tiling and W tiling can be understood as organizations of
1925 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1926 * is different, but the layout of the 32-byte sub-tiles within the 4k
1927 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1928 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1929 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1931 * Therefore, to account for the layout differences within the 32-byte
1932 * sub-tiles, we must expand the rectangle so the X coordinates of its
1933 * edges are multiples of 8 (the W sub-tile width), and its Y
1934 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1935 * Then we need to scale the X and Y coordinates of the rectangle to
1936 * account for the differences in aspect ratio between the Y and W
1937 * sub-tiles. We need to modify the layer width and height similarly.
1939 * A correction needs to be applied when MSAA is in use: since
1940 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1941 * we need to align the Y coordinates to multiples of 8, so that when
1942 * they are divided by two they are still multiples of 4.
1944 * Note: Since the x/y offset of the surface will be applied using the
1945 * SURFACE_STATE command packet, it will be invisible to the swizzling
1946 * code in the shader; therefore it needs to be in a multiple of the
1947 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1948 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1949 * buffer), and the miplevel alignment used for stencil buffers is 8
1950 * pixels horizontally and either 4 or 8 pixels vertically (see
1951 * intel_horizontal_texture_alignment_unit() and
1952 * intel_vertical_texture_alignment_unit()).
1954 * Note: Also, since the SURFACE_STATE command packet can only apply
1955 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1956 * vertically, it is important that the offsets will be multiples of
1957 * these sizes after they are converted into Y-tiled coordinates.
1958 * Fortunately they will be, since we know from above that the offsets
1959 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1960 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1962 * TODO: what if this makes the coordinates (or the texture size) too
1965 const unsigned x_align
= 8;
1966 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1967 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1968 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1969 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1970 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1972 /* Retile the surface to Y-tiled */
1973 blorp_surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1975 wm_prog_key
->dst_tiled_w
= true;
1976 wm_prog_key
->use_kill
= true;
1977 wm_prog_key
->need_dst_offset
= true;
1979 if (params
->dst
.surf
.samples
> 1) {
1980 /* If the destination surface is a W-tiled multisampled stencil
1981 * buffer that we're mapping as Y tiled, then we need to arrange for
1982 * the WM program to run once per sample rather than once per pixel,
1983 * because the memory layout of related samples doesn't match between
1986 wm_prog_key
->persample_msaa_dispatch
= true;
1990 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1991 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1992 * Broadwell adds support for sampling from stencil.
1994 * See the comments above concerning x/y offset alignment for the
1995 * destination surface.
1997 * TODO: what if this makes the texture size too large?
1999 blorp_surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
2001 wm_prog_key
->src_tiled_w
= true;
2002 wm_prog_key
->need_src_offset
= true;
2005 /* tex_samples and rt_samples are the sample counts that are set up in
2008 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
2009 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
2011 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2012 * use to access the source and destination surfaces.
2014 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
2015 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
2017 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
2018 /* We are blitting from a multisample buffer to a multisample buffer, so
2019 * we must preserve samples within a pixel. This means we have to
2020 * arrange for the WM program to run once per sample rather than once
2023 wm_prog_key
->persample_msaa_dispatch
= true;
2026 params
->num_samples
= params
->dst
.surf
.samples
;
2028 if ((wm_prog_key
->filter
== BLORP_FILTER_AVERAGE
||
2029 wm_prog_key
->filter
== BLORP_FILTER_BILINEAR
) &&
2030 batch
->blorp
->isl_dev
->info
->gen
<= 6) {
2031 /* Gen4-5 don't support non-normalized texture coordinates */
2032 wm_prog_key
->src_coords_normalized
= true;
2033 params
->wm_inputs
.src_inv_size
[0] =
2034 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.width
,
2035 params
->src
.view
.base_level
);
2036 params
->wm_inputs
.src_inv_size
[1] =
2037 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.height
,
2038 params
->src
.view
.base_level
);
2041 if (isl_format_get_layout(params
->dst
.view
.format
)->bpb
% 3 == 0) {
2042 /* We can't render to RGB formats natively because they aren't a
2043 * power-of-two size. Instead, we fake them by using a red format
2044 * with the same channel type and size and emitting shader code to
2045 * only write one channel at a time.
2050 /* If it happens to be sRGB, we need to force a conversion */
2051 if (params
->dst
.view
.format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
)
2052 wm_prog_key
->dst_format
= ISL_FORMAT_R8G8B8_UNORM_SRGB
;
2054 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
->dst
);
2056 wm_prog_key
->dst_rgb
= true;
2057 wm_prog_key
->need_dst_offset
= true;
2058 } else if (isl_format_is_rgbx(params
->dst
.view
.format
)) {
2059 /* We can handle RGBX formats easily enough by treating them as RGBA */
2060 params
->dst
.view
.format
=
2061 isl_format_rgbx_to_rgba(params
->dst
.view
.format
);
2062 } else if (params
->dst
.view
.format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
&&
2063 wm_prog_key
->dst_usage
!= ISL_SURF_USAGE_DEPTH_BIT
) {
2064 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2065 params
->dst
.view
.format
= ISL_FORMAT_R32_UINT
;
2066 } else if (params
->dst
.view
.format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
2067 params
->dst
.view
.swizzle
=
2068 isl_swizzle_compose(params
->dst
.view
.swizzle
,
2069 ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
));
2070 params
->dst
.view
.format
= ISL_FORMAT_B4G4R4A4_UNORM
;
2071 } else if (params
->dst
.view
.format
== ISL_FORMAT_L8_UNORM_SRGB
) {
2072 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2073 params
->dst
.view
.format
= ISL_FORMAT_R8_UNORM
;
2074 } else if (params
->dst
.view
.format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
2075 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2076 params
->dst
.view
.format
= ISL_FORMAT_R32_UINT
;
2079 if (devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
2080 !isl_swizzle_is_identity(params
->src
.view
.swizzle
)) {
2081 wm_prog_key
->src_swizzle
= params
->src
.view
.swizzle
;
2082 params
->src
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
2084 wm_prog_key
->src_swizzle
= ISL_SWIZZLE_IDENTITY
;
2087 if (!isl_swizzle_supports_rendering(devinfo
, params
->dst
.view
.swizzle
)) {
2088 wm_prog_key
->dst_swizzle
= params
->dst
.view
.swizzle
;
2089 params
->dst
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
2091 wm_prog_key
->dst_swizzle
= ISL_SWIZZLE_IDENTITY
;
2094 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
2095 assert(wm_prog_key
->need_src_offset
);
2096 surf_get_intratile_offset_px(¶ms
->src
,
2097 ¶ms
->wm_inputs
.src_offset
.x
,
2098 ¶ms
->wm_inputs
.src_offset
.y
);
2101 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
2102 assert(wm_prog_key
->need_dst_offset
);
2103 surf_get_intratile_offset_px(¶ms
->dst
,
2104 ¶ms
->wm_inputs
.dst_offset
.x
,
2105 ¶ms
->wm_inputs
.dst_offset
.y
);
2106 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
2107 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
2108 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
2109 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
2112 /* For some texture types, we need to pass the layer through the sampler. */
2113 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
2115 if (!brw_blorp_get_blit_kernel(batch
, params
, wm_prog_key
))
2118 if (!blorp_ensure_sf_program(batch
, params
))
2121 unsigned result
= 0;
2122 unsigned max_src_surface_size
= get_max_surface_size(devinfo
, ¶ms
->src
);
2123 if (params
->src
.surf
.logical_level0_px
.width
> max_src_surface_size
)
2124 result
|= BLIT_SRC_WIDTH_SHRINK
;
2125 if (params
->src
.surf
.logical_level0_px
.height
> max_src_surface_size
)
2126 result
|= BLIT_SRC_HEIGHT_SHRINK
;
2128 unsigned max_dst_surface_size
= get_max_surface_size(devinfo
, ¶ms
->dst
);
2129 if (params
->dst
.surf
.logical_level0_px
.width
> max_dst_surface_size
)
2130 result
|= BLIT_DST_WIDTH_SHRINK
;
2131 if (params
->dst
.surf
.logical_level0_px
.height
> max_dst_surface_size
)
2132 result
|= BLIT_DST_HEIGHT_SHRINK
;
2135 if (wm_prog_key
->dst_usage
== ISL_SURF_USAGE_DEPTH_BIT
) {
2136 params
->depth
= params
->dst
;
2137 memset(¶ms
->dst
, 0, sizeof(params
->dst
));
2138 } else if (wm_prog_key
->dst_usage
== ISL_SURF_USAGE_STENCIL_BIT
) {
2139 params
->stencil
= params
->dst
;
2140 params
->stencil_mask
= 0xff;
2141 memset(¶ms
->dst
, 0, sizeof(params
->dst
));
2144 batch
->blorp
->exec(batch
, params
);
2150 /* Adjust split blit source coordinates for the current destination
2154 adjust_split_source_coords(const struct blt_axis
*orig
,
2155 struct blt_axis
*split_coords
,
2158 /* When scale is greater than 0, then we are growing from the start, so
2159 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
2160 * source range shrinks from the end. In that case src0 is adjusted by
2161 * delta1, and src1 is adjusted by delta0.
2163 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
2164 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
2165 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
2166 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
2169 static struct isl_extent2d
2170 get_px_size_sa(const struct isl_surf
*surf
)
2172 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
2174 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
2177 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
2181 shrink_surface_params(const struct isl_device
*dev
,
2182 struct brw_blorp_surface_info
*info
,
2183 double *x0
, double *x1
, double *y0
, double *y1
)
2185 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
2186 struct isl_extent2d px_size_sa
;
2189 blorp_surf_convert_to_single_slice(dev
, info
);
2191 px_size_sa
= get_px_size_sa(&info
->surf
);
2193 /* Because this gets called after we lower compressed images, the tile
2194 * offsets may be non-zero and we need to incorporate them in our
2197 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
2198 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
2199 isl_tiling_get_intratile_offset_sa(info
->surf
.tiling
,
2200 info
->surf
.format
, info
->surf
.row_pitch_B
,
2201 x_offset_sa
, y_offset_sa
,
2203 &info
->tile_x_sa
, &info
->tile_y_sa
);
2205 info
->addr
.offset
+= byte_offset
;
2207 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
2210 info
->tile_x_sa
= 0;
2212 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
2215 info
->tile_y_sa
= 0;
2217 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
2218 info
->surf
.logical_level0_px
.width
= size
;
2219 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
2221 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
2222 info
->surf
.logical_level0_px
.height
= size
;
2223 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
2227 do_blorp_blit(struct blorp_batch
*batch
,
2228 const struct blorp_params
*orig_params
,
2229 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2230 const struct blt_coords
*orig
)
2232 struct blorp_params params
;
2233 struct blt_coords blit_coords
;
2234 struct blt_coords split_coords
= *orig
;
2235 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
2236 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
2237 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
2238 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
2244 enum blit_shrink_status shrink
= BLIT_NO_SHRINK
;
2245 if (split_blorp_blit_debug
) {
2246 if (can_shrink_surface(&orig_params
->src
))
2247 shrink
|= BLIT_SRC_WIDTH_SHRINK
| BLIT_SRC_HEIGHT_SHRINK
;
2248 if (can_shrink_surface(&orig_params
->dst
))
2249 shrink
|= BLIT_DST_WIDTH_SHRINK
| BLIT_DST_HEIGHT_SHRINK
;
2252 bool x_done
, y_done
;
2254 params
= *orig_params
;
2255 blit_coords
= split_coords
;
2257 if (shrink
& (BLIT_SRC_WIDTH_SHRINK
| BLIT_SRC_HEIGHT_SHRINK
)) {
2258 shrink_surface_params(batch
->blorp
->isl_dev
, ¶ms
.src
,
2259 &blit_coords
.x
.src0
, &blit_coords
.x
.src1
,
2260 &blit_coords
.y
.src0
, &blit_coords
.y
.src1
);
2261 wm_prog_key
->need_src_offset
= false;
2264 if (shrink
& (BLIT_DST_WIDTH_SHRINK
| BLIT_DST_HEIGHT_SHRINK
)) {
2265 shrink_surface_params(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2266 &blit_coords
.x
.dst0
, &blit_coords
.x
.dst1
,
2267 &blit_coords
.y
.dst0
, &blit_coords
.y
.dst1
);
2268 wm_prog_key
->need_dst_offset
= false;
2271 enum blit_shrink_status result
=
2272 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
2274 if (result
& (BLIT_SRC_WIDTH_SHRINK
| BLIT_SRC_HEIGHT_SHRINK
))
2275 assert(can_shrink_surface(&orig_params
->src
));
2277 if (result
& (BLIT_DST_WIDTH_SHRINK
| BLIT_DST_HEIGHT_SHRINK
))
2278 assert(can_shrink_surface(&orig_params
->dst
));
2280 if (result
& (BLIT_SRC_WIDTH_SHRINK
| BLIT_DST_WIDTH_SHRINK
)) {
2283 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2284 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2286 if (result
& (BLIT_SRC_HEIGHT_SHRINK
| BLIT_DST_HEIGHT_SHRINK
)) {
2289 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2290 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2294 /* We may get less bits set on result than we had already, so make
2295 * sure we remember all the ways in which a resize is required.
2301 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
2302 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
2305 } else if (y_done
) {
2306 split_coords
.x
.dst0
+= w
;
2307 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2308 split_coords
.y
.dst0
= orig
->y
.dst0
;
2309 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2310 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2312 split_coords
.y
.dst0
+= h
;
2313 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2314 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2320 blorp_blit(struct blorp_batch
*batch
,
2321 const struct blorp_surf
*src_surf
,
2322 unsigned src_level
, unsigned src_layer
,
2323 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2324 const struct blorp_surf
*dst_surf
,
2325 unsigned dst_level
, unsigned dst_layer
,
2326 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2327 float src_x0
, float src_y0
,
2328 float src_x1
, float src_y1
,
2329 float dst_x0
, float dst_y0
,
2330 float dst_x1
, float dst_y1
,
2331 enum blorp_filter filter
,
2332 bool mirror_x
, bool mirror_y
)
2334 struct blorp_params params
;
2335 blorp_params_init(¶ms
);
2337 /* We cannot handle combined depth and stencil. */
2338 if (src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2339 assert(src_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2340 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2341 assert(dst_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2343 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
2344 assert(src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
);
2345 /* Prior to Broadwell, we can't render to R8_UINT */
2346 if (batch
->blorp
->isl_dev
->info
->gen
< 8) {
2347 src_format
= ISL_FORMAT_R8_UNORM
;
2348 dst_format
= ISL_FORMAT_R8_UNORM
;
2352 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2353 src_layer
, src_format
, false);
2354 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2355 dst_layer
, dst_format
, true);
2357 params
.src
.view
.swizzle
= src_swizzle
;
2358 params
.dst
.view
.swizzle
= dst_swizzle
;
2360 const struct isl_format_layout
*src_fmtl
=
2361 isl_format_get_layout(params
.src
.view
.format
);
2363 struct brw_blorp_blit_prog_key wm_prog_key
= {
2364 .shader_type
= BLORP_SHADER_TYPE_BLIT
,
2366 .sint32_to_uint
= src_fmtl
->channels
.r
.bits
== 32 &&
2367 isl_format_has_sint_channel(params
.src
.view
.format
) &&
2368 isl_format_has_uint_channel(params
.dst
.view
.format
),
2369 .uint32_to_sint
= src_fmtl
->channels
.r
.bits
== 32 &&
2370 isl_format_has_uint_channel(params
.src
.view
.format
) &&
2371 isl_format_has_sint_channel(params
.dst
.view
.format
),
2374 /* Scaling factors used for bilinear filtering in multisample scaled
2377 if (params
.src
.surf
.samples
== 16)
2378 wm_prog_key
.x_scale
= 4.0f
;
2380 wm_prog_key
.x_scale
= 2.0f
;
2381 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2383 params
.wm_inputs
.rect_grid
.x1
=
2384 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2385 wm_prog_key
.x_scale
- 1.0f
;
2386 params
.wm_inputs
.rect_grid
.y1
=
2387 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2388 wm_prog_key
.y_scale
- 1.0f
;
2390 struct blt_coords coords
= {
2407 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2410 static enum isl_format
2411 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2413 /* The choice of UNORM and UINT formats is very intentional here. Most
2414 * of the time, we want to use a UINT format to avoid any rounding error
2415 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2416 * (It's the only format allowed in conjunction with W-tiling.) Also we
2417 * intentionally use the 4-channel formats whenever we can. This is so
2418 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2419 * even though one of them is 3/4 the size of the other. The choice of
2420 * UNORM vs. UINT is also very intentional because we don't have 8 or
2421 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2422 * Fortunately, the only time we should ever use two different formats in
2423 * the table below is for RGB -> RGBA blits and so we will never have any
2424 * UNORM/UINT mismatch.
2426 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2428 case 8: return ISL_FORMAT_R8_UINT
;
2429 case 16: return ISL_FORMAT_R8G8_UINT
;
2430 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2431 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2432 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2433 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2434 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2435 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2437 unreachable("Unknown format bpb");
2441 case 8: return ISL_FORMAT_R8_UINT
;
2442 case 16: return ISL_FORMAT_R8G8_UINT
;
2443 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2444 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2445 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2446 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2447 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2448 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2450 unreachable("Unknown format bpb");
2455 /** Returns a UINT format that is CCS-compatible with the given format
2457 * The PRM's say absolutely nothing about how render compression works. The
2458 * only thing they provide is a list of formats on which it is and is not
2459 * supported. Empirical testing indicates that the compression is only based
2460 * on the bit-layout of the format and the channel encoding doesn't matter.
2461 * So, while texture views don't work in general, you can create a view as
2462 * long as the bit-layout of the formats are the same.
2464 * Fortunately, for every render compression capable format, the UINT format
2465 * with the same bit layout also supports render compression. This means that
2466 * we only need to handle UINT formats for copy operations. In order to do
2467 * copies between formats with different bit layouts, we attach both with a
2468 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2469 * operation between the two bit layouts.
2471 static enum isl_format
2472 get_ccs_compatible_copy_format(const struct isl_format_layout
*fmtl
)
2474 switch (fmtl
->format
) {
2475 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2476 case ISL_FORMAT_R32G32B32A32_SINT
:
2477 case ISL_FORMAT_R32G32B32A32_UINT
:
2478 case ISL_FORMAT_R32G32B32A32_UNORM
:
2479 case ISL_FORMAT_R32G32B32A32_SNORM
:
2480 case ISL_FORMAT_R32G32B32X32_FLOAT
:
2481 return ISL_FORMAT_R32G32B32A32_UINT
;
2483 case ISL_FORMAT_R16G16B16A16_UNORM
:
2484 case ISL_FORMAT_R16G16B16A16_SNORM
:
2485 case ISL_FORMAT_R16G16B16A16_SINT
:
2486 case ISL_FORMAT_R16G16B16A16_UINT
:
2487 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2488 case ISL_FORMAT_R16G16B16X16_UNORM
:
2489 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2490 return ISL_FORMAT_R16G16B16A16_UINT
;
2492 case ISL_FORMAT_R32G32_FLOAT
:
2493 case ISL_FORMAT_R32G32_SINT
:
2494 case ISL_FORMAT_R32G32_UINT
:
2495 case ISL_FORMAT_R32G32_UNORM
:
2496 case ISL_FORMAT_R32G32_SNORM
:
2497 return ISL_FORMAT_R32G32_UINT
;
2499 case ISL_FORMAT_B8G8R8A8_UNORM
:
2500 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2501 case ISL_FORMAT_R8G8B8A8_UNORM
:
2502 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2503 case ISL_FORMAT_R8G8B8A8_SNORM
:
2504 case ISL_FORMAT_R8G8B8A8_SINT
:
2505 case ISL_FORMAT_R8G8B8A8_UINT
:
2506 case ISL_FORMAT_B8G8R8X8_UNORM
:
2507 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2508 case ISL_FORMAT_R8G8B8X8_UNORM
:
2509 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2510 return ISL_FORMAT_R8G8B8A8_UINT
;
2512 case ISL_FORMAT_R16G16_UNORM
:
2513 case ISL_FORMAT_R16G16_SNORM
:
2514 case ISL_FORMAT_R16G16_SINT
:
2515 case ISL_FORMAT_R16G16_UINT
:
2516 case ISL_FORMAT_R16G16_FLOAT
:
2517 return ISL_FORMAT_R16G16_UINT
;
2519 case ISL_FORMAT_R32_SINT
:
2520 case ISL_FORMAT_R32_UINT
:
2521 case ISL_FORMAT_R32_FLOAT
:
2522 case ISL_FORMAT_R32_UNORM
:
2523 case ISL_FORMAT_R32_SNORM
:
2524 return ISL_FORMAT_R32_UINT
;
2526 case ISL_FORMAT_B10G10R10A2_UNORM
:
2527 case ISL_FORMAT_B10G10R10A2_UNORM_SRGB
:
2528 case ISL_FORMAT_R10G10B10A2_UNORM
:
2529 case ISL_FORMAT_R10G10B10A2_UNORM_SRGB
:
2530 case ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM
:
2531 case ISL_FORMAT_R10G10B10A2_UINT
:
2532 return ISL_FORMAT_R10G10B10A2_UINT
;
2534 case ISL_FORMAT_R16_UNORM
:
2535 case ISL_FORMAT_R16_SNORM
:
2536 case ISL_FORMAT_R16_SINT
:
2537 case ISL_FORMAT_R16_UINT
:
2538 case ISL_FORMAT_R16_FLOAT
:
2539 return ISL_FORMAT_R16_UINT
;
2541 case ISL_FORMAT_R8G8_UNORM
:
2542 case ISL_FORMAT_R8G8_SNORM
:
2543 case ISL_FORMAT_R8G8_SINT
:
2544 case ISL_FORMAT_R8G8_UINT
:
2545 return ISL_FORMAT_R8G8_UINT
;
2547 case ISL_FORMAT_B5G5R5X1_UNORM
:
2548 case ISL_FORMAT_B5G5R5X1_UNORM_SRGB
:
2549 case ISL_FORMAT_B5G5R5A1_UNORM
:
2550 case ISL_FORMAT_B5G5R5A1_UNORM_SRGB
:
2551 return ISL_FORMAT_B5G5R5A1_UNORM
;
2553 case ISL_FORMAT_A4B4G4R4_UNORM
:
2554 case ISL_FORMAT_B4G4R4A4_UNORM
:
2555 case ISL_FORMAT_B4G4R4A4_UNORM_SRGB
:
2556 return ISL_FORMAT_B4G4R4A4_UNORM
;
2558 case ISL_FORMAT_B5G6R5_UNORM
:
2559 case ISL_FORMAT_B5G6R5_UNORM_SRGB
:
2560 return ISL_FORMAT_B5G6R5_UNORM
;
2562 case ISL_FORMAT_A1B5G5R5_UNORM
:
2563 return ISL_FORMAT_A1B5G5R5_UNORM
;
2565 case ISL_FORMAT_A8_UNORM
:
2566 case ISL_FORMAT_R8_UNORM
:
2567 case ISL_FORMAT_R8_SNORM
:
2568 case ISL_FORMAT_R8_SINT
:
2569 case ISL_FORMAT_R8_UINT
:
2570 return ISL_FORMAT_R8_UINT
;
2573 unreachable("Not a compressible format");
2578 blorp_surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2579 struct brw_blorp_surface_info
*info
,
2580 uint32_t *x
, uint32_t *y
,
2581 uint32_t *width
, uint32_t *height
)
2583 const struct isl_format_layout
*fmtl
=
2584 isl_format_get_layout(info
->surf
.format
);
2586 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2588 /* This is a compressed surface. We need to convert it to a single
2589 * slice (because compressed layouts don't perfectly match uncompressed
2590 * ones with the same bpb) and divide x, y, width, and height by the
2593 blorp_surf_convert_to_single_slice(isl_dev
, info
);
2595 if (width
&& height
) {
2597 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2598 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2599 assert(*width
% fmtl
->bw
== 0 ||
2600 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2601 assert(*height
% fmtl
->bh
== 0 ||
2602 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2604 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2605 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2609 assert(*x
% fmtl
->bw
== 0);
2610 assert(*y
% fmtl
->bh
== 0);
2615 info
->surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&info
->surf
);
2616 info
->surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&info
->surf
);
2618 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2619 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2620 info
->tile_x_sa
/= fmtl
->bw
;
2621 info
->tile_y_sa
/= fmtl
->bh
;
2623 /* It's now an uncompressed surface so we need an uncompressed format */
2624 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2628 blorp_copy(struct blorp_batch
*batch
,
2629 const struct blorp_surf
*src_surf
,
2630 unsigned src_level
, unsigned src_layer
,
2631 const struct blorp_surf
*dst_surf
,
2632 unsigned dst_level
, unsigned dst_layer
,
2633 uint32_t src_x
, uint32_t src_y
,
2634 uint32_t dst_x
, uint32_t dst_y
,
2635 uint32_t src_width
, uint32_t src_height
)
2637 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2638 struct blorp_params params
;
2640 if (src_width
== 0 || src_height
== 0)
2643 blorp_params_init(¶ms
);
2644 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2645 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2646 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2647 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2649 struct brw_blorp_blit_prog_key wm_prog_key
= {
2650 .shader_type
= BLORP_SHADER_TYPE_BLIT
,
2651 .filter
= BLORP_FILTER_NONE
,
2652 .need_src_offset
= src_surf
->tile_x_sa
|| src_surf
->tile_y_sa
,
2653 .need_dst_offset
= dst_surf
->tile_x_sa
|| dst_surf
->tile_y_sa
,
2656 const struct isl_format_layout
*src_fmtl
=
2657 isl_format_get_layout(params
.src
.surf
.format
);
2658 const struct isl_format_layout
*dst_fmtl
=
2659 isl_format_get_layout(params
.dst
.surf
.format
);
2661 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2662 params
.src
.aux_usage
== ISL_AUX_USAGE_HIZ
||
2663 params
.src
.aux_usage
== ISL_AUX_USAGE_HIZ_CCS_WT
||
2664 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2665 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS_CCS
||
2666 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
||
2667 params
.src
.aux_usage
== ISL_AUX_USAGE_GEN12_CCS_E
||
2668 params
.src
.aux_usage
== ISL_AUX_USAGE_STC_CCS
);
2670 if (isl_aux_usage_has_hiz(params
.src
.aux_usage
)) {
2671 /* In order to use HiZ, we have to use the real format for the source.
2672 * Depth <-> Color copies are not allowed.
2674 params
.src
.view
.format
= params
.src
.surf
.format
;
2675 params
.dst
.view
.format
= params
.src
.surf
.format
;
2676 } else if ((params
.dst
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
2677 isl_dev
->info
->gen
>= 7) {
2678 /* On Gen7 and higher, we use actual depth writes for blits into depth
2679 * buffers so we need the real format.
2681 params
.src
.view
.format
= params
.dst
.surf
.format
;
2682 params
.dst
.view
.format
= params
.dst
.surf
.format
;
2683 } else if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
||
2684 params
.dst
.aux_usage
== ISL_AUX_USAGE_GEN12_CCS_E
) {
2685 params
.dst
.view
.format
= get_ccs_compatible_copy_format(dst_fmtl
);
2686 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
||
2687 params
.src
.aux_usage
== ISL_AUX_USAGE_GEN12_CCS_E
) {
2688 params
.src
.view
.format
= get_ccs_compatible_copy_format(src_fmtl
);
2689 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2690 params
.src
.view
.format
= params
.dst
.view
.format
;
2692 params
.src
.view
.format
=
2693 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2695 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
||
2696 params
.src
.aux_usage
== ISL_AUX_USAGE_GEN12_CCS_E
) {
2697 params
.src
.view
.format
= get_ccs_compatible_copy_format(src_fmtl
);
2698 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2699 params
.dst
.view
.format
= params
.src
.view
.format
;
2701 params
.dst
.view
.format
=
2702 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2705 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2706 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2709 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2710 /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
2711 * enabled even though CCS_E doesn't technically do sRGB on SKL because
2712 * we stomp everything to UINT anyway. The one thing we have to be
2713 * careful of is clear colors. Because fast clear colors for sRGB on
2714 * gen9 are encoded as the float values between format conversion and
2715 * sRGB curve application, a given clear color float will convert to the
2716 * same bits regardless of whether the format is UNORM or sRGB.
2717 * Therefore, we can handle sRGB without any special cases.
2719 UNUSED
enum isl_format linear_src_format
=
2720 isl_format_srgb_to_linear(src_surf
->surf
->format
);
2721 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2723 params
.src
.view
.format
));
2725 isl_color_value_pack(¶ms
.src
.clear_color
,
2726 linear_src_format
, packed
);
2727 isl_color_value_unpack(¶ms
.src
.clear_color
,
2728 params
.src
.view
.format
, packed
);
2731 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2732 /* See above where we handle linear_src_format */
2733 UNUSED
enum isl_format linear_dst_format
=
2734 isl_format_srgb_to_linear(dst_surf
->surf
->format
);
2735 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2737 params
.dst
.view
.format
));
2739 isl_color_value_pack(¶ms
.dst
.clear_color
,
2740 linear_dst_format
, packed
);
2741 isl_color_value_unpack(¶ms
.dst
.clear_color
,
2742 params
.dst
.view
.format
, packed
);
2745 if (params
.src
.view
.format
!= params
.dst
.view
.format
) {
2746 enum isl_format src_cast_format
= params
.src
.view
.format
;
2747 enum isl_format dst_cast_format
= params
.dst
.view
.format
;
2749 /* The BLORP bitcast code gets confused by RGB formats. Just treat them
2750 * as RGBA and then everything will be happy. This is perfectly safe
2751 * because BLORP likes to treat things as if they have vec4 colors all
2754 if (isl_format_get_layout(src_cast_format
)->bpb
% 3 == 0)
2755 src_cast_format
= isl_format_rgb_to_rgba(src_cast_format
);
2756 if (isl_format_get_layout(dst_cast_format
)->bpb
% 3 == 0)
2757 dst_cast_format
= isl_format_rgb_to_rgba(dst_cast_format
);
2759 if (src_cast_format
!= dst_cast_format
) {
2760 wm_prog_key
.format_bit_cast
= true;
2761 wm_prog_key
.src_format
= src_cast_format
;
2762 wm_prog_key
.dst_format
= dst_cast_format
;
2766 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2767 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2769 &src_width
, &src_height
);
2770 wm_prog_key
.need_src_offset
= true;
2773 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2774 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2775 &dst_x
, &dst_y
, NULL
, NULL
);
2776 wm_prog_key
.need_dst_offset
= true;
2779 /* Once both surfaces are stompped to uncompressed as needed, the
2780 * destination size is the same as the source size.
2782 uint32_t dst_width
= src_width
;
2783 uint32_t dst_height
= src_height
;
2785 struct blt_coords coords
= {
2788 .src1
= src_x
+ src_width
,
2790 .dst1
= dst_x
+ dst_width
,
2795 .src1
= src_y
+ src_height
,
2797 .dst1
= dst_y
+ dst_height
,
2802 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2805 static enum isl_format
2806 isl_format_for_size(unsigned size_B
)
2809 case 1: return ISL_FORMAT_R8_UINT
;
2810 case 2: return ISL_FORMAT_R8G8_UINT
;
2811 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
2812 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
2813 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
2815 unreachable("Not a power-of-two format size");
2820 * Returns the greatest common divisor of a and b that is a power of two.
2823 gcd_pow2_u64(uint64_t a
, uint64_t b
)
2825 assert(a
> 0 || b
> 0);
2827 unsigned a_log2
= ffsll(a
) - 1;
2828 unsigned b_log2
= ffsll(b
) - 1;
2830 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
2831 * case, the MIN2() will take the other one. If both are 0 then we will
2832 * hit the assert above.
2834 return 1 << MIN2(a_log2
, b_log2
);
2838 do_buffer_copy(struct blorp_batch
*batch
,
2839 struct blorp_address
*src
,
2840 struct blorp_address
*dst
,
2841 int width
, int height
, int block_size
)
2843 /* The actual format we pick doesn't matter as blorp will throw it away.
2844 * The only thing that actually matters is the size.
2846 enum isl_format format
= isl_format_for_size(block_size
);
2849 struct isl_surf surf
;
2850 ok
= isl_surf_init(batch
->blorp
->isl_dev
, &surf
,
2851 .dim
= ISL_SURF_DIM_2D
,
2859 .row_pitch_B
= width
* block_size
,
2860 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
2861 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
2862 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
2865 struct blorp_surf src_blorp_surf
= {
2870 struct blorp_surf dst_blorp_surf
= {
2875 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
2876 0, 0, 0, 0, width
, height
);
2880 blorp_buffer_copy(struct blorp_batch
*batch
,
2881 struct blorp_address src
,
2882 struct blorp_address dst
,
2885 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
2886 uint64_t copy_size
= size
;
2888 /* This is maximum possible width/height our HW can handle */
2889 uint64_t max_surface_dim
= 1 << (devinfo
->gen
>= 7 ? 14 : 13);
2891 /* First, we compute the biggest format that can be used with the
2892 * given offsets and size.
2895 bs
= gcd_pow2_u64(bs
, src
.offset
);
2896 bs
= gcd_pow2_u64(bs
, dst
.offset
);
2897 bs
= gcd_pow2_u64(bs
, size
);
2899 /* First, we make a bunch of max-sized copies */
2900 uint64_t max_copy_size
= max_surface_dim
* max_surface_dim
* bs
;
2901 while (copy_size
>= max_copy_size
) {
2902 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, max_surface_dim
, bs
);
2903 copy_size
-= max_copy_size
;
2904 src
.offset
+= max_copy_size
;
2905 dst
.offset
+= max_copy_size
;
2908 /* Now make a max-width copy */
2909 uint64_t height
= copy_size
/ (max_surface_dim
* bs
);
2910 assert(height
< max_surface_dim
);
2912 uint64_t rect_copy_size
= height
* max_surface_dim
* bs
;
2913 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, height
, bs
);
2914 copy_size
-= rect_copy_size
;
2915 src
.offset
+= rect_copy_size
;
2916 dst
.offset
+= rect_copy_size
;
2919 /* Finally, make a small copy to finish it off */
2920 if (copy_size
!= 0) {
2921 do_buffer_copy(batch
, &src
, &dst
, copy_size
/ bs
, 1, bs
);