2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/nir/nir_builder.h"
26 #include "blorp_priv.h"
28 /* header-only include needed for _mesa_unorm_to_float and friends. */
29 #include "mesa/main/format_utils.h"
31 #define FILE_DEBUG_FLAG DEBUG_BLORP
33 static const bool split_blorp_blit_debug
= false;
36 * Enum to specify the order of arguments in a sampler message
38 enum sampler_message_arg
40 SAMPLER_MESSAGE_ARG_U_FLOAT
,
41 SAMPLER_MESSAGE_ARG_V_FLOAT
,
42 SAMPLER_MESSAGE_ARG_U_INT
,
43 SAMPLER_MESSAGE_ARG_V_INT
,
44 SAMPLER_MESSAGE_ARG_R_INT
,
45 SAMPLER_MESSAGE_ARG_SI_INT
,
46 SAMPLER_MESSAGE_ARG_MCS_INT
,
47 SAMPLER_MESSAGE_ARG_ZERO_INT
,
50 struct brw_blorp_blit_vars
{
51 /* Input values from brw_blorp_wm_inputs */
52 nir_variable
*v_discard_rect
;
53 nir_variable
*v_rect_grid
;
54 nir_variable
*v_coord_transform
;
55 nir_variable
*v_src_z
;
56 nir_variable
*v_src_offset
;
57 nir_variable
*v_dst_offset
;
60 nir_variable
*frag_coord
;
63 nir_variable
*color_out
;
67 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
68 const struct brw_blorp_blit_prog_key
*key
)
70 /* Blended and scaled blits never use pixel discard. */
71 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
73 #define LOAD_INPUT(name, type)\
74 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
76 LOAD_INPUT(discard_rect
, glsl_vec4_type())
77 LOAD_INPUT(rect_grid
, glsl_vec4_type())
78 LOAD_INPUT(coord_transform
, glsl_vec4_type())
79 LOAD_INPUT(src_z
, glsl_uint_type())
80 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
81 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
85 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
86 glsl_vec4_type(), "gl_FragCoord");
87 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
88 v
->frag_coord
->data
.origin_upper_left
= true;
90 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
91 glsl_vec4_type(), "gl_FragColor");
92 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
96 blorp_blit_get_frag_coords(nir_builder
*b
,
97 const struct brw_blorp_blit_prog_key
*key
,
98 struct brw_blorp_blit_vars
*v
)
100 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_var(b
, v
->frag_coord
));
102 /* Account for destination surface intratile offset
104 * Transformation parameters giving translation from destination to source
105 * coordinates don't take into account possible intra-tile destination
106 * offset. Therefore it has to be first subtracted from the incoming
107 * coordinates. Vertices are set up based on coordinates containing the
110 if (key
->need_dst_offset
)
111 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
113 if (key
->persample_msaa_dispatch
) {
114 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
115 nir_load_sample_id(b
));
117 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
122 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
126 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
127 struct brw_blorp_blit_vars
*v
)
129 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
131 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
132 nir_channel(b
, coord_transform
, 3));
133 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
134 nir_channel(b
, coord_transform
, 2));
136 return nir_ffma(b
, src_pos
, mul
, offset
);
140 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
141 struct brw_blorp_blit_vars
*v
)
143 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
144 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
145 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
146 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
147 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
148 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
150 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
151 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
152 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
153 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
155 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
157 nir_intrinsic_instr
*discard
=
158 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
159 discard
->src
[0] = nir_src_for_ssa(oob
);
160 nir_builder_instr_insert(b
, &discard
->instr
);
163 static nir_tex_instr
*
164 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
165 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
166 nir_alu_type dst_type
)
168 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
172 tex
->dest_type
= dst_type
;
173 tex
->is_array
= false;
174 tex
->is_shadow
= false;
176 /* Blorp only has one texture and it's bound at unit 0 */
179 tex
->texture_index
= 0;
180 tex
->sampler_index
= 0;
182 /* To properly handle 3-D and 2-D array textures, we pull the Z component
183 * from an input. TODO: This is a bit magic; we should probably make this
184 * more explicit in the future.
186 assert(pos
->num_components
>= 2);
187 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
188 nir_load_var(b
, v
->v_src_z
));
190 tex
->src
[0].src_type
= nir_tex_src_coord
;
191 tex
->src
[0].src
= nir_src_for_ssa(pos
);
192 tex
->coord_components
= 3;
194 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
200 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
201 nir_ssa_def
*pos
, nir_alu_type dst_type
)
204 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2, dst_type
);
206 assert(pos
->num_components
== 2);
207 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
208 tex
->src
[1].src_type
= nir_tex_src_lod
;
209 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
211 nir_builder_instr_insert(b
, &tex
->instr
);
213 return &tex
->dest
.ssa
;
217 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
218 nir_ssa_def
*pos
, nir_alu_type dst_type
)
221 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
223 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
224 tex
->src
[1].src_type
= nir_tex_src_lod
;
225 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
227 nir_builder_instr_insert(b
, &tex
->instr
);
229 return &tex
->dest
.ssa
;
233 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
234 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
237 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
238 mcs
!= NULL
? 3 : 2, dst_type
);
240 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
242 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
243 if (pos
->num_components
== 2) {
244 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
246 assert(pos
->num_components
== 3);
247 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
251 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
252 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
255 nir_builder_instr_insert(b
, &tex
->instr
);
257 return &tex
->dest
.ssa
;
261 blorp_nir_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
, nir_ssa_def
*pos
)
264 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
265 pos
, 1, nir_type_int
);
267 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
269 nir_builder_instr_insert(b
, &tex
->instr
);
271 return &tex
->dest
.ssa
;
275 nir_mask_shift_or(struct nir_builder
*b
, nir_ssa_def
*dst
, nir_ssa_def
*src
,
276 uint32_t src_mask
, int src_left_shift
)
278 nir_ssa_def
*masked
= nir_iand(b
, src
, nir_imm_int(b
, src_mask
));
280 nir_ssa_def
*shifted
;
281 if (src_left_shift
> 0) {
282 shifted
= nir_ishl(b
, masked
, nir_imm_int(b
, src_left_shift
));
283 } else if (src_left_shift
< 0) {
284 shifted
= nir_ushr(b
, masked
, nir_imm_int(b
, -src_left_shift
));
286 assert(src_left_shift
== 0);
290 return nir_ior(b
, dst
, shifted
);
294 * Emit code to compensate for the difference between Y and W tiling.
296 * This code modifies the X and Y coordinates according to the formula:
298 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
300 * (See brw_blorp_build_nir_shader).
302 static inline nir_ssa_def
*
303 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
305 assert(pos
->num_components
== 2);
306 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
307 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
309 /* Given X and Y coordinates that describe an address using Y tiling,
310 * translate to the X and Y coordinates that describe the same address
313 * If we break down the low order bits of X and Y, using a
314 * single letter to represent each low-order bit:
316 * X = A << 7 | 0bBCDEFGH
317 * Y = J << 5 | 0bKLMNP (1)
319 * Then we can apply the Y tiling formula to see the memory offset being
322 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
324 * If we apply the W detiling formula to this memory location, that the
325 * corresponding X' and Y' coordinates are:
327 * X' = A << 6 | 0bBCDPFH (3)
328 * Y' = J << 6 | 0bKLMNEG
330 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
331 * we need to make the following computation:
333 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
334 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
336 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
337 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
338 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
339 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
341 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
342 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
343 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
344 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
346 return nir_vec2(b
, x_W
, y_W
);
350 * Emit code to compensate for the difference between Y and W tiling.
352 * This code modifies the X and Y coordinates according to the formula:
354 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
356 * (See brw_blorp_build_nir_shader).
358 static inline nir_ssa_def
*
359 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
361 assert(pos
->num_components
== 2);
362 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
363 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
365 /* Applying the same logic as above, but in reverse, we obtain the
368 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
369 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
371 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
372 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
373 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
374 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
375 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
377 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
378 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
379 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
381 return nir_vec2(b
, x_Y
, y_Y
);
385 * Emit code to compensate for the difference between MSAA and non-MSAA
388 * This code modifies the X and Y coordinates according to the formula:
390 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
392 * (See brw_blorp_blit_program).
394 static inline nir_ssa_def
*
395 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
396 unsigned num_samples
, enum isl_msaa_layout layout
)
398 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
401 case ISL_MSAA_LAYOUT_NONE
:
402 assert(pos
->num_components
== 2);
404 case ISL_MSAA_LAYOUT_ARRAY
:
405 /* No translation needed */
407 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
408 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
409 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
410 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
411 nir_channel(b
, pos
, 2);
413 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
414 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
415 switch (num_samples
) {
418 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
419 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
422 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
423 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
424 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
426 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
427 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
428 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
429 if (num_samples
== 2) {
432 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
433 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
434 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
439 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
440 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
442 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
444 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
445 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
446 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
447 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
448 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
449 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
450 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
454 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
455 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
457 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
460 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
461 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
462 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
463 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
464 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
465 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
466 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
467 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
471 unreachable("Invalid number of samples for IMS layout");
474 return nir_vec2(b
, x_out
, y_out
);
478 unreachable("Invalid MSAA layout");
483 * Emit code to compensate for the difference between MSAA and non-MSAA
486 * This code modifies the X and Y coordinates according to the formula:
488 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
490 * (See brw_blorp_blit_program).
492 static inline nir_ssa_def
*
493 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
494 unsigned num_samples
, enum isl_msaa_layout layout
)
496 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
499 case ISL_MSAA_LAYOUT_NONE
:
500 /* No translation necessary, and S should already be zero. */
501 assert(pos
->num_components
== 2);
503 case ISL_MSAA_LAYOUT_ARRAY
:
504 /* No translation necessary. */
506 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
507 assert(pos
->num_components
== 2);
509 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
510 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
512 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
513 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
514 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
515 switch (num_samples
) {
518 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
519 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
520 * S = (X & 0b10) >> 1
522 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
523 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
524 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
525 * S = (Y & 0b10) | (X & 0b10) >> 1
527 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
528 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
529 if (num_samples
== 2) {
531 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
533 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
534 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
535 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
536 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
541 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
542 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
543 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
544 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
546 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
547 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
548 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
549 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
550 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
551 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
552 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
556 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
557 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
558 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
559 * S = (Y & 0b100) << 1 | (X & 0b100) |
560 * (Y & 0b10) | (X & 0b10) >> 1
562 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
563 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
564 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
565 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
566 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
567 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
568 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
569 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
573 unreachable("Invalid number of samples for IMS layout");
576 return nir_vec3(b
, x_out
, y_out
, s_out
);
580 unreachable("Invalid MSAA layout");
585 * Count the number of trailing 1 bits in the given value. For example:
587 * count_trailing_one_bits(0) == 0
588 * count_trailing_one_bits(7) == 3
589 * count_trailing_one_bits(11) == 2
591 static inline int count_trailing_one_bits(unsigned value
)
593 #ifdef HAVE___BUILTIN_CTZ
594 return __builtin_ctz(~value
);
596 return _mesa_bitcount(value
& ~(value
+ 1));
601 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
602 nir_ssa_def
*pos
, unsigned tex_samples
,
603 enum isl_aux_usage tex_aux_usage
,
604 nir_alu_type dst_type
)
606 /* If non-null, this is the outer-most if statement */
607 nir_if
*outer_if
= NULL
;
609 nir_variable
*color
=
610 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
612 nir_ssa_def
*mcs
= NULL
;
613 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
614 mcs
= blorp_nir_txf_ms_mcs(b
, v
, pos
);
616 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
618 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
620 * This ensures that when all samples have the same value, no numerical
621 * precision is lost, since each addition operation always adds two equal
622 * values, and summing two equal floating point values does not lose
625 * We perform this computation by treating the texture_data array as a
626 * stack and performing the following operations:
628 * - push sample 0 onto stack
629 * - push sample 1 onto stack
630 * - add top two stack entries
631 * - push sample 2 onto stack
632 * - push sample 3 onto stack
633 * - add top two stack entries
634 * - add top two stack entries
635 * - divide top stack entry by 4
637 * Note that after pushing sample i onto the stack, the number of add
638 * operations we do is equal to the number of trailing 1 bits in i. This
639 * works provided the total number of samples is a power of two, which it
640 * always is for i965.
642 * For integer formats, we replace the add operations with average
643 * operations and skip the final division.
645 nir_ssa_def
*texture_data
[5];
646 unsigned stack_depth
= 0;
647 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
648 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
650 /* Push sample i onto the stack */
651 assert(stack_depth
< ARRAY_SIZE(texture_data
));
653 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
654 nir_channel(b
, pos
, 1),
656 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
658 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
659 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
660 * suggests an optimization:
662 * "A simple optimization with probable large return in
663 * performance is to compare the MCS value to zero (indicating
664 * all samples are on sample slice 0), and sample only from
665 * sample slice 0 using ld2dss if MCS is zero."
667 * Note that in the case where the MCS value is zero, sampling from
668 * sample slice 0 using ld2dss and sampling from sample 0 using
669 * ld2dms are equivalent (since all samples are on sample slice 0).
670 * Since we have already sampled from sample 0, all we need to do is
671 * skip the remaining fetches and averaging if MCS is zero.
673 nir_ssa_def
*mcs_zero
=
674 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
675 if (tex_samples
== 16) {
676 mcs_zero
= nir_iand(b
, mcs_zero
,
677 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
680 nir_if
*if_stmt
= nir_if_create(b
->shader
);
681 if_stmt
->condition
= nir_src_for_ssa(mcs_zero
);
682 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
684 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
685 nir_store_var(b
, color
, texture_data
[0], 0xf);
687 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
691 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
692 assert(stack_depth
>= 2);
695 assert(dst_type
== nir_type_float
);
696 texture_data
[stack_depth
- 1] =
697 nir_fadd(b
, texture_data
[stack_depth
- 1],
698 texture_data
[stack_depth
]);
702 /* We should have just 1 sample on the stack now. */
703 assert(stack_depth
== 1);
705 texture_data
[0] = nir_fmul(b
, texture_data
[0],
706 nir_imm_float(b
, 1.0 / tex_samples
));
708 nir_store_var(b
, color
, texture_data
[0], 0xf);
711 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
713 return nir_load_var(b
, color
);
716 static inline nir_ssa_def
*
717 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
721 memset(&v
, 0, sizeof(v
));
725 return nir_build_imm(build
, 4, 32, v
);
729 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
730 unsigned tex_samples
,
731 const struct brw_blorp_blit_prog_key
*key
,
732 struct brw_blorp_blit_vars
*v
)
734 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
735 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
736 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
738 /* Translate coordinates to lay out the samples in a rectangular grid
739 * roughly corresponding to sample locations.
741 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
742 /* Adjust coordinates so that integers represent pixel centers rather
745 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
746 /* Clamp the X, Y texture coordinates to properly handle the sampling of
747 * texels on texture edges.
749 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
750 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
751 nir_channel(b
, rect_grid
, 1)));
753 /* Store the fractional parts to be used as bilinear interpolation
756 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
757 /* Round the float coordinates down to nearest integer */
758 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
760 nir_ssa_def
*tex_data
[4];
761 for (unsigned i
= 0; i
< 4; ++i
) {
762 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
763 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
764 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
766 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
767 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
769 /* The MCS value we fetch has to match up with the pixel that we're
770 * sampling from. Since we sample from different pixels in each
771 * iteration of this "for" loop, the call to mcs_fetch() should be
772 * here inside the loop after computing the pixel coordinates.
774 nir_ssa_def
*mcs
= NULL
;
775 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
776 mcs
= blorp_nir_txf_ms_mcs(b
, v
, sample_coords_int
);
778 /* Compute sample index and map the sample index to a sample number.
779 * Sample index layout shows the numbering of slots in a rectangular
780 * grid of samples with in a pixel. Sample number layout shows the
781 * rectangular grid of samples roughly corresponding to the real sample
782 * locations with in a pixel.
783 * In case of 4x MSAA, layout of sample indices matches the layout of
791 * In case of 8x MSAA the two layouts don't match.
792 * sample index layout : --------- sample number layout : ---------
793 * | 0 | 1 | | 3 | 7 |
794 * --------- ---------
795 * | 2 | 3 | | 5 | 0 |
796 * --------- ---------
797 * | 4 | 5 | | 1 | 2 |
798 * --------- ---------
799 * | 6 | 7 | | 4 | 6 |
800 * --------- ---------
802 * Fortunately, this can be done fairly easily as:
803 * S' = (0x17306425 >> (S * 4)) & 0xf
805 * In the case of 16x MSAA the two layouts don't match.
806 * Sample index layout: Sample number layout:
807 * --------------------- ---------------------
808 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
809 * --------------------- ---------------------
810 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
811 * --------------------- ---------------------
812 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
813 * --------------------- ---------------------
814 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
815 * --------------------- ---------------------
817 * This is equivalent to
818 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
820 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
821 nir_ssa_def
*sample
=
822 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
823 key
->x_scale
* key
->y_scale
));
824 sample
= nir_f2i32(b
, sample
);
826 if (tex_samples
== 8) {
827 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
828 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
829 nir_imm_int(b
, 0xf));
830 } else if (tex_samples
== 16) {
831 nir_ssa_def
*sample_low
=
832 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
833 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
834 nir_imm_int(b
, 0xf));
835 nir_ssa_def
*sample_high
=
836 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
837 nir_ishl(b
, nir_iadd(b
, sample
,
840 nir_imm_int(b
, 0xf));
842 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
843 sample_low
, sample_high
);
845 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
846 nir_channel(b
, sample_coords_int
, 1),
848 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
851 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
852 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
853 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
854 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
858 /** Perform a color bit-cast operation
860 * For copy operations involving CCS, we may need to use different formats for
861 * the source and destination surfaces. The two formats must both be UINT
862 * formats and must have the same size but may have different bit layouts.
863 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
864 * to R16G16_UINT. This function generates code to shuffle bits around to get
865 * us from one to the other.
868 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
869 const struct brw_blorp_blit_prog_key
*key
)
871 assert(key
->texture_data_type
== nir_type_uint
);
873 if (key
->dst_bpc
> key
->src_bpc
) {
874 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
875 nir_ssa_def
*dst_chan
[2] = { u
, u
};
877 unsigned dst_idx
= 0;
878 for (unsigned i
= 0; i
< 4; i
++) {
879 nir_ssa_def
*shifted
= nir_ishl(b
, nir_channel(b
, color
, i
),
880 nir_imm_int(b
, shift
));
882 dst_chan
[dst_idx
] = shifted
;
884 dst_chan
[dst_idx
] = nir_ior(b
, dst_chan
[dst_idx
], shifted
);
887 shift
+= key
->src_bpc
;
888 if (shift
>= key
->dst_bpc
) {
894 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], u
, u
);
896 assert(key
->dst_bpc
< key
->src_bpc
);
898 nir_ssa_def
*mask
= nir_imm_int(b
, ~0u >> (32 - key
->dst_bpc
));
900 nir_ssa_def
*dst_chan
[4];
901 unsigned src_idx
= 0;
903 for (unsigned i
= 0; i
< 4; i
++) {
904 dst_chan
[i
] = nir_iand(b
, nir_ushr(b
, nir_channel(b
, color
, src_idx
),
905 nir_imm_int(b
, shift
)),
907 shift
+= key
->dst_bpc
;
908 if (shift
>= key
->src_bpc
) {
914 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], dst_chan
[2], dst_chan
[3]);
919 * Generator for WM programs used in BLORP blits.
921 * The bulk of the work done by the WM program is to wrap and unwrap the
922 * coordinate transformations used by the hardware to store surfaces in
923 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
924 * sample index for a multisampled surface) to a memory offset by the
925 * following formulas:
927 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
928 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
930 * For a single-sampled surface, or for a multisampled surface using
931 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
934 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
935 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
936 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
937 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
939 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
940 * embeds the sample number into bit 1 of the X and Y coordinates:
942 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
943 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
944 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
945 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
946 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
947 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
948 * S = (Y & 0b10) | (X & 0b10) >> 1
950 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
951 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
954 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
955 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
956 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
957 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
958 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
959 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
960 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
962 * For X tiling, tile() combines together the low-order bits of the X and Y
963 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
964 * bytes wide and 8 rows high:
966 * tile(x_tiled, X, Y, S) = A
967 * where A = tile_num << 12 | offset
968 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
969 * offset = (Y' & 0b111) << 9
970 * | (X & 0b111111111)
972 * Y' = Y + S * qpitch
973 * detile(x_tiled, A) = (X, Y, S)
977 * Y' = (tile_num / tile_pitch) << 3
978 * | (A & 0b111000000000) >> 9
979 * X' = (tile_num % tile_pitch) << 9
980 * | (A & 0b111111111)
982 * (In all tiling formulas, cpp is the number of bytes occupied by a single
983 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
984 * to fill the width of the surface, and qpitch is the spacing (in rows)
985 * between array slices).
987 * For Y tiling, tile() combines together the low-order bits of the X and Y
988 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
989 * bytes wide and 32 rows high:
991 * tile(y_tiled, X, Y, S) = A
992 * where A = tile_num << 12 | offset
993 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
994 * offset = (X' & 0b1110000) << 5
995 * | (Y' & 0b11111) << 4
998 * Y' = Y + S * qpitch
999 * detile(y_tiled, A) = (X, Y, S)
1000 * where X = X' / cpp
1003 * Y' = (tile_num / tile_pitch) << 5
1004 * | (A & 0b111110000) >> 4
1005 * X' = (tile_num % tile_pitch) << 7
1006 * | (A & 0b111000000000) >> 5
1009 * For W tiling, tile() combines together the low-order bits of the X and Y
1010 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1011 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1012 * buffers, which always have cpp = 1 and S=0):
1014 * tile(w_tiled, X, Y, S) = A
1015 * where A = tile_num << 12 | offset
1016 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1017 * offset = (X' & 0b111000) << 6
1018 * | (Y' & 0b111100) << 3
1019 * | (X' & 0b100) << 2
1020 * | (Y' & 0b10) << 2
1021 * | (X' & 0b10) << 1
1025 * Y' = Y + S * qpitch
1026 * detile(w_tiled, A) = (X, Y, S)
1027 * where X = X' / cpp = X'
1028 * Y = Y' % qpitch = Y'
1029 * S = Y / qpitch = 0
1030 * Y' = (tile_num / tile_pitch) << 6
1031 * | (A & 0b111100000) >> 3
1032 * | (A & 0b1000) >> 2
1034 * X' = (tile_num % tile_pitch) << 6
1035 * | (A & 0b111000000000) >> 6
1036 * | (A & 0b10000) >> 2
1037 * | (A & 0b100) >> 1
1040 * Finally, for a non-tiled surface, tile() simply combines together the X and
1041 * Y coordinates in the natural way:
1043 * tile(untiled, X, Y, S) = A
1044 * where A = Y * pitch + X'
1046 * Y' = Y + S * qpitch
1047 * detile(untiled, A) = (X, Y, S)
1048 * where X = X' / cpp
1054 * (In these formulas, pitch is the number of bytes occupied by a single row
1058 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1059 const struct brw_blorp_blit_prog_key
*key
)
1061 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1062 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1065 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1066 /* If the destination image is W tiled and multisampled, then the thread
1067 * must be dispatched once per sample, not once per pixel. This is
1068 * necessary because after conversion between W and Y tiling, there's no
1069 * guarantee that all samples corresponding to a single pixel will still
1072 assert(key
->persample_msaa_dispatch
);
1076 /* We are blending, which means we won't have an opportunity to
1077 * translate the tiling and sample count for the texture surface. So
1078 * the surface state for the texture must be configured with the correct
1079 * tiling and sample count.
1081 assert(!key
->src_tiled_w
);
1082 assert(key
->tex_samples
== key
->src_samples
);
1083 assert(key
->tex_layout
== key
->src_layout
);
1084 assert(key
->tex_samples
> 0);
1087 if (key
->persample_msaa_dispatch
) {
1088 /* It only makes sense to do persample dispatch if the render target is
1089 * configured as multisampled.
1091 assert(key
->rt_samples
> 0);
1094 /* Make sure layout is consistent with sample count */
1095 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1096 (key
->tex_samples
<= 1));
1097 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1098 (key
->rt_samples
<= 1));
1099 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1100 (key
->src_samples
<= 1));
1101 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1102 (key
->dst_samples
<= 1));
1105 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1107 struct brw_blorp_blit_vars v
;
1108 brw_blorp_blit_vars_init(&b
, &v
, key
);
1110 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1112 /* Render target and texture hardware don't support W tiling until Gen8. */
1113 const bool rt_tiled_w
= false;
1114 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1116 /* The address that data will be written to is determined by the
1117 * coordinates supplied to the WM thread and the tiling and sample count of
1118 * the render target, according to the formula:
1120 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1122 * If the actual tiling and sample count of the destination surface are not
1123 * the same as the configuration of the render target, then these
1124 * coordinates are wrong and we have to adjust them to compensate for the
1127 if (rt_tiled_w
!= key
->dst_tiled_w
||
1128 key
->rt_samples
!= key
->dst_samples
||
1129 key
->rt_layout
!= key
->dst_layout
) {
1130 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1132 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1133 if (rt_tiled_w
!= key
->dst_tiled_w
)
1134 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1135 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1136 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1140 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1142 * That is: X, Y and S now contain the true coordinates and sample index of
1143 * the data that the WM thread should output.
1145 * If we need to kill pixels that are outside the destination rectangle,
1146 * now is the time to do it.
1148 if (key
->use_kill
) {
1149 assert(!(key
->blend
&& key
->blit_scaled
));
1150 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1153 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1154 if (dst_pos
->num_components
== 3) {
1155 /* The sample coordinate is an integer that we want left alone but
1156 * blorp_blit_apply_transform() blindly applies the transform to all
1157 * three coordinates. Grab the original sample index.
1159 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1160 nir_channel(&b
, src_pos
, 1),
1161 nir_channel(&b
, dst_pos
, 2));
1164 /* If the source image is not multisampled, then we want to fetch sample
1165 * number 0, because that's the only sample there is.
1167 if (key
->src_samples
== 1)
1168 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1170 /* X, Y, and S are now the coordinates of the pixel in the source image
1171 * that we want to texture from. Exception: if we are blending, then S is
1172 * irrelevant, because we are going to fetch all samples.
1174 if (key
->blend
&& !key
->blit_scaled
) {
1175 /* Resolves (effecively) use texelFetch, so we need integers and we
1176 * don't care about the sample index if we got one.
1178 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1180 if (devinfo
->gen
== 6) {
1181 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1182 * blending we need with a single linear-interpolated texture lookup
1183 * at the center of the sample. The texture coordinates to be odd
1184 * integers so that they correspond to the center of a 2x2 block
1185 * representing the four samples that maxe up a pixel. So we need
1186 * to multiply our X and Y coordinates each by 2 and then add 1.
1188 src_pos
= nir_ishl(&b
, src_pos
, nir_imm_int(&b
, 1));
1189 src_pos
= nir_iadd(&b
, src_pos
, nir_imm_int(&b
, 1));
1190 src_pos
= nir_i2f32(&b
, src_pos
);
1191 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1193 /* Gen7+ hardware doesn't automaticaly blend. */
1194 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1196 key
->texture_data_type
);
1198 } else if (key
->blend
&& key
->blit_scaled
) {
1199 assert(!key
->use_kill
);
1200 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1202 if (key
->bilinear_filter
) {
1203 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1205 /* We're going to use texelFetch, so we need integers */
1206 if (src_pos
->num_components
== 2) {
1207 src_pos
= nir_f2i32(&b
, src_pos
);
1209 assert(src_pos
->num_components
== 3);
1210 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1211 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1212 nir_channel(&b
, src_pos
, 2));
1215 /* We aren't blending, which means we just want to fetch a single
1216 * sample from the source surface. The address that we want to fetch
1217 * from is related to the X, Y and S values according to the formula:
1219 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1221 * If the actual tiling and sample count of the source surface are
1222 * not the same as the configuration of the texture, then we need to
1223 * adjust the coordinates to compensate for the difference.
1225 if (tex_tiled_w
!= key
->src_tiled_w
||
1226 key
->tex_samples
!= key
->src_samples
||
1227 key
->tex_layout
!= key
->src_layout
) {
1228 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1230 /* Now (X, Y, S) = detile(src_tiling, offset) */
1231 if (tex_tiled_w
!= key
->src_tiled_w
)
1232 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1233 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1234 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1238 if (key
->need_src_offset
)
1239 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1241 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1243 * In other words: X, Y, and S now contain values which, when passed to
1244 * the texturing unit, will cause data to be read from the correct
1245 * memory location. So we can fetch the texel now.
1247 if (key
->src_samples
== 1) {
1248 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1250 nir_ssa_def
*mcs
= NULL
;
1251 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1252 mcs
= blorp_nir_txf_ms_mcs(&b
, &v
, src_pos
);
1254 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1259 if (key
->dst_bpc
!= key
->src_bpc
)
1260 color
= bit_cast_color(&b
, color
, key
);
1263 /* The destination image is bound as a red texture three times as wide
1264 * as the actual image. Our shader is effectively running one color
1265 * component at a time. We need to pick off the appropriate component
1266 * from the source color and write that to destination red.
1268 assert(dst_pos
->num_components
== 2);
1270 nir_umod(&b
, nir_channel(&b
, dst_pos
, 0), nir_imm_int(&b
, 3));
1272 nir_ssa_def
*color_component
=
1273 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1274 nir_channel(&b
, color
, 0),
1275 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1276 nir_channel(&b
, color
, 1),
1277 nir_channel(&b
, color
, 2)));
1279 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1280 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1283 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1289 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1290 struct blorp_params
*params
,
1291 const struct brw_blorp_blit_prog_key
*prog_key
)
1293 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1294 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1297 void *mem_ctx
= ralloc_context(NULL
);
1299 const unsigned *program
;
1300 unsigned program_size
;
1301 struct brw_wm_prog_data prog_data
;
1303 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1304 nir
->info
->name
= ralloc_strdup(nir
, "BLORP-blit");
1306 struct brw_wm_prog_key wm_key
;
1307 brw_blorp_init_wm_prog_key(&wm_key
);
1308 wm_key
.tex
.compressed_multisample_layout_mask
=
1309 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1310 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1311 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1313 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1314 &prog_data
, &program_size
);
1317 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1318 program
, program_size
,
1319 &prog_data
.base
, sizeof(prog_data
),
1320 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1322 ralloc_free(mem_ctx
);
1327 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1328 GLfloat src0
, GLfloat src1
,
1329 GLfloat dst0
, GLfloat dst1
,
1332 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1334 /* When not mirroring a coordinate (say, X), we need:
1335 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1337 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1339 * blorp program uses "round toward zero" to convert the
1340 * transformed floating point coordinates to integer coordinates,
1341 * whereas the behaviour we actually want is "round to nearest",
1342 * so 0.5 provides the necessary correction.
1344 xform
->multiplier
= scale
;
1345 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1347 /* When mirroring X we need:
1348 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1350 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1352 xform
->multiplier
= -scale
;
1353 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1358 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1359 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1361 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1362 struct isl_extent2d px_size_sa
=
1363 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1364 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1365 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1366 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1367 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1369 *tile_x_px
= info
->tile_x_sa
;
1370 *tile_y_px
= info
->tile_y_sa
;
1375 surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1376 struct brw_blorp_surface_info
*info
)
1380 /* Just bail if we have nothing to do. */
1381 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1382 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1383 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1386 /* If this gets triggered then we've gotten here twice which. This
1387 * shouldn't happen thanks to the above early return.
1389 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1391 uint32_t layer
= 0, z
= 0;
1392 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1393 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1395 layer
= info
->view
.base_array_layer
;
1397 uint32_t x_offset_sa
, y_offset_sa
;
1398 isl_surf_get_image_offset_sa(&info
->surf
, info
->view
.base_level
,
1399 layer
, z
, &x_offset_sa
, &y_offset_sa
);
1401 uint32_t byte_offset
;
1402 isl_tiling_get_intratile_offset_sa(isl_dev
, info
->surf
.tiling
,
1403 info
->surf
.format
, info
->surf
.row_pitch
,
1404 x_offset_sa
, y_offset_sa
,
1406 &info
->tile_x_sa
, &info
->tile_y_sa
);
1407 info
->addr
.offset
+= byte_offset
;
1409 const uint32_t slice_width_px
=
1410 minify(info
->surf
.logical_level0_px
.width
, info
->view
.base_level
);
1411 const uint32_t slice_height_px
=
1412 minify(info
->surf
.logical_level0_px
.height
, info
->view
.base_level
);
1414 uint32_t tile_x_px
, tile_y_px
;
1415 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1417 struct isl_surf_init_info init_info
= {
1418 .dim
= ISL_SURF_DIM_2D
,
1419 .format
= info
->surf
.format
,
1420 .width
= slice_width_px
+ tile_x_px
,
1421 .height
= slice_height_px
+ tile_y_px
,
1425 .samples
= info
->surf
.samples
,
1426 .row_pitch
= info
->surf
.row_pitch
,
1427 .usage
= info
->surf
.usage
,
1428 .tiling_flags
= 1 << info
->surf
.tiling
,
1431 ok
= isl_surf_init_s(isl_dev
, &info
->surf
, &init_info
);
1434 /* The view is also different now. */
1435 info
->view
.base_level
= 0;
1436 info
->view
.levels
= 1;
1437 info
->view
.base_array_layer
= 0;
1438 info
->view
.array_len
= 1;
1443 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1444 struct brw_blorp_surface_info
*info
)
1446 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1448 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1449 surf_convert_to_single_slice(isl_dev
, info
);
1451 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1452 info
->surf
.samples
= 1;
1453 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1457 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1458 struct brw_blorp_surface_info
*info
)
1460 assert(info
->surf
.tiling
== ISL_TILING_W
);
1462 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1463 surf_convert_to_single_slice(isl_dev
, info
);
1465 /* On gen7+, we don't have interleaved multisampling for color render
1466 * targets so we have to fake it.
1468 * TODO: Are we sure we don't also need to fake it on gen6?
1470 if (isl_dev
->info
->gen
> 6 &&
1471 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1472 surf_fake_interleaved_msaa(isl_dev
, info
);
1475 if (isl_dev
->info
->gen
== 6) {
1476 /* Gen6 stencil buffers have a very large alignment coming in from the
1477 * miptree. It's out-of-bounds for what the surface state can handle.
1478 * Since we have a single layer and level, it doesn't really matter as
1479 * long as we don't pass a bogus value into isl_surf_fill_state().
1481 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1484 /* Now that we've converted everything to a simple 2-D surface with only
1485 * one miplevel, we can go about retiling it.
1487 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1488 info
->surf
.tiling
= ISL_TILING_Y0
;
1489 info
->surf
.logical_level0_px
.width
=
1490 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1491 info
->surf
.logical_level0_px
.height
=
1492 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1493 info
->tile_x_sa
*= 2;
1494 info
->tile_y_sa
/= 2;
1498 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1500 /* The current code doesn't support offsets into the aux buffers. This
1501 * should be possible, but we need to make sure the offset is page
1502 * aligned for both the surface and the aux buffer surface. Generally
1503 * this mean using the page aligned offset for the aux buffer.
1505 * Currently the cases where we must split the blit are limited to cases
1506 * where we don't have a aux buffer.
1508 if (surf
->aux_addr
.buffer
!= NULL
)
1511 /* We can't support splitting the blit for gen <= 7, because the qpitch
1512 * size is calculated by the hardware based on the surface height for
1513 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1515 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1522 can_shrink_surfaces(const struct blorp_params
*params
)
1525 can_shrink_surface(¶ms
->src
) &&
1526 can_shrink_surface(¶ms
->dst
);
1530 get_max_surface_size(const struct gen_device_info
*devinfo
,
1531 const struct blorp_params
*params
)
1533 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1534 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1535 return max
>> 4; /* A smaller restriction when debug is enabled */
1541 double src0
, src1
, dst0
, dst1
;
1546 struct blt_axis x
, y
;
1550 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1551 struct brw_blorp_surface_info
*info
,
1552 uint32_t *x
, uint32_t *width
)
1554 surf_convert_to_single_slice(isl_dev
, info
);
1556 info
->surf
.logical_level0_px
.width
*= 3;
1557 info
->surf
.phys_level0_sa
.width
*= 3;
1561 enum isl_format red_format
;
1562 switch (info
->view
.format
) {
1563 case ISL_FORMAT_R8G8B8_UNORM
:
1564 red_format
= ISL_FORMAT_R8_UNORM
;
1566 case ISL_FORMAT_R8G8B8_UINT
:
1567 red_format
= ISL_FORMAT_R8_UINT
;
1569 case ISL_FORMAT_R16G16B16_UNORM
:
1570 red_format
= ISL_FORMAT_R16_UNORM
;
1572 case ISL_FORMAT_R16G16B16_UINT
:
1573 red_format
= ISL_FORMAT_R16_UINT
;
1575 case ISL_FORMAT_R32G32B32_UINT
:
1576 red_format
= ISL_FORMAT_R32_UINT
;
1579 unreachable("Invalid RGB copy destination format");
1581 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1582 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1583 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1584 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1586 info
->surf
.format
= info
->view
.format
= red_format
;
1590 fake_dest_rgb_with_red(const struct isl_device
*dev
,
1591 struct blorp_params
*params
,
1592 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1593 struct blt_coords
*coords
)
1595 /* Handle RGB destinations for blorp_copy */
1596 const struct isl_format_layout
*dst_fmtl
=
1597 isl_format_get_layout(params
->dst
.surf
.format
);
1599 if (dst_fmtl
->bpb
% 3 == 0) {
1600 uint32_t dst_x
= coords
->x
.dst0
;
1601 uint32_t dst_width
= coords
->x
.dst1
- dst_x
;
1602 surf_fake_rgb_with_red(dev
, ¶ms
->dst
,
1603 &dst_x
, &dst_width
);
1604 coords
->x
.dst0
= dst_x
;
1605 coords
->x
.dst1
= dst_x
+ dst_width
;
1606 wm_prog_key
->dst_rgb
= true;
1607 wm_prog_key
->need_dst_offset
= true;
1611 enum blit_shrink_status
{
1613 BLIT_WIDTH_SHRINK
= 1,
1614 BLIT_HEIGHT_SHRINK
= 2,
1617 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1618 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1619 * returned, then the blit was successful.
1621 static enum blit_shrink_status
1622 try_blorp_blit(struct blorp_batch
*batch
,
1623 struct blorp_params
*params
,
1624 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1625 struct blt_coords
*coords
)
1627 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1629 fake_dest_rgb_with_red(batch
->blorp
->isl_dev
, params
, wm_prog_key
, coords
);
1631 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1632 wm_prog_key
->texture_data_type
= nir_type_int
;
1633 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1634 wm_prog_key
->texture_data_type
= nir_type_uint
;
1636 wm_prog_key
->texture_data_type
= nir_type_float
;
1639 /* src_samples and dst_samples are the true sample counts */
1640 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1641 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1643 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1645 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1648 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1649 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1651 /* Round floating point values to nearest integer to avoid "off by one texel"
1652 * kind of errors when blitting.
1654 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1655 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1656 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1657 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1659 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1660 coords
->x
.src0
, coords
->x
.src1
,
1661 coords
->x
.dst0
, coords
->x
.dst1
,
1663 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1664 coords
->y
.src0
, coords
->y
.src1
,
1665 coords
->y
.dst0
, coords
->y
.dst1
,
1668 if (devinfo
->gen
> 6 &&
1669 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1670 assert(params
->dst
.surf
.samples
> 1);
1672 /* We must expand the rectangle we send through the rendering pipeline,
1673 * to account for the fact that we are mapping the destination region as
1674 * single-sampled when it is in fact multisampled. We must also align
1675 * it to a multiple of the multisampling pattern, because the
1676 * differences between multisampled and single-sampled surface formats
1677 * will mean that pixels are scrambled within the multisampling pattern.
1678 * TODO: what if this makes the coordinates too large?
1680 * Note: this only works if the destination surface uses the IMS layout.
1681 * If it's UMS, then we have no choice but to set up the rendering
1682 * pipeline as multisampled.
1684 struct isl_extent2d px_size_sa
=
1685 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1686 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1687 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1688 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1689 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1691 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1693 wm_prog_key
->use_kill
= true;
1694 wm_prog_key
->need_dst_offset
= true;
1697 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1698 /* We must modify the rectangle we send through the rendering pipeline
1699 * (and the size and x/y offset of the destination surface), to account
1700 * for the fact that we are mapping it as Y-tiled when it is in fact
1703 * Both Y tiling and W tiling can be understood as organizations of
1704 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1705 * is different, but the layout of the 32-byte sub-tiles within the 4k
1706 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1707 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1708 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1710 * Therefore, to account for the layout differences within the 32-byte
1711 * sub-tiles, we must expand the rectangle so the X coordinates of its
1712 * edges are multiples of 8 (the W sub-tile width), and its Y
1713 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1714 * Then we need to scale the X and Y coordinates of the rectangle to
1715 * account for the differences in aspect ratio between the Y and W
1716 * sub-tiles. We need to modify the layer width and height similarly.
1718 * A correction needs to be applied when MSAA is in use: since
1719 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1720 * we need to align the Y coordinates to multiples of 8, so that when
1721 * they are divided by two they are still multiples of 4.
1723 * Note: Since the x/y offset of the surface will be applied using the
1724 * SURFACE_STATE command packet, it will be invisible to the swizzling
1725 * code in the shader; therefore it needs to be in a multiple of the
1726 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1727 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1728 * buffer), and the miplevel alignment used for stencil buffers is 8
1729 * pixels horizontally and either 4 or 8 pixels vertically (see
1730 * intel_horizontal_texture_alignment_unit() and
1731 * intel_vertical_texture_alignment_unit()).
1733 * Note: Also, since the SURFACE_STATE command packet can only apply
1734 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1735 * vertically, it is important that the offsets will be multiples of
1736 * these sizes after they are converted into Y-tiled coordinates.
1737 * Fortunately they will be, since we know from above that the offsets
1738 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1739 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1741 * TODO: what if this makes the coordinates (or the texture size) too
1744 const unsigned x_align
= 8;
1745 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1746 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1747 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1748 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1749 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1751 /* Retile the surface to Y-tiled */
1752 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1754 wm_prog_key
->dst_tiled_w
= true;
1755 wm_prog_key
->use_kill
= true;
1756 wm_prog_key
->need_dst_offset
= true;
1758 if (params
->dst
.surf
.samples
> 1) {
1759 /* If the destination surface is a W-tiled multisampled stencil
1760 * buffer that we're mapping as Y tiled, then we need to arrange for
1761 * the WM program to run once per sample rather than once per pixel,
1762 * because the memory layout of related samples doesn't match between
1765 wm_prog_key
->persample_msaa_dispatch
= true;
1769 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1770 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1771 * Broadwell adds support for sampling from stencil.
1773 * See the comments above concerning x/y offset alignment for the
1774 * destination surface.
1776 * TODO: what if this makes the texture size too large?
1778 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1780 wm_prog_key
->src_tiled_w
= true;
1781 wm_prog_key
->need_src_offset
= true;
1784 /* tex_samples and rt_samples are the sample counts that are set up in
1787 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1788 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1790 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1791 * use to access the source and destination surfaces.
1793 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1794 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1796 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1797 /* We are blitting from a multisample buffer to a multisample buffer, so
1798 * we must preserve samples within a pixel. This means we have to
1799 * arrange for the WM program to run once per sample rather than once
1802 wm_prog_key
->persample_msaa_dispatch
= true;
1805 params
->num_samples
= params
->dst
.surf
.samples
;
1807 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
1808 assert(wm_prog_key
->need_src_offset
);
1809 surf_get_intratile_offset_px(¶ms
->src
,
1810 ¶ms
->wm_inputs
.src_offset
.x
,
1811 ¶ms
->wm_inputs
.src_offset
.y
);
1814 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
1815 assert(wm_prog_key
->need_dst_offset
);
1816 surf_get_intratile_offset_px(¶ms
->dst
,
1817 ¶ms
->wm_inputs
.dst_offset
.x
,
1818 ¶ms
->wm_inputs
.dst_offset
.y
);
1819 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
1820 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
1821 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
1822 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
1825 /* For some texture types, we need to pass the layer through the sampler. */
1826 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
1828 if (!brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
))
1831 unsigned result
= 0;
1832 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
1833 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
1834 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
1835 result
|= BLIT_WIDTH_SHRINK
;
1836 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
1837 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
1838 result
|= BLIT_HEIGHT_SHRINK
;
1841 batch
->blorp
->exec(batch
, params
);
1847 /* Adjust split blit source coordinates for the current destination
1851 adjust_split_source_coords(const struct blt_axis
*orig
,
1852 struct blt_axis
*split_coords
,
1855 /* When scale is greater than 0, then we are growing from the start, so
1856 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
1857 * source range shrinks from the end. In that case src0 is adjusted by
1858 * delta1, and src1 is adjusted by delta0.
1860 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
1861 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
1862 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
1863 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
1866 static struct isl_extent2d
1867 get_px_size_sa(const struct isl_surf
*surf
)
1869 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
1871 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
1874 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
1878 shrink_surface_params(const struct isl_device
*dev
,
1879 struct brw_blorp_surface_info
*info
,
1880 double *x0
, double *x1
, double *y0
, double *y1
)
1882 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
1883 struct isl_extent2d px_size_sa
;
1886 surf_convert_to_single_slice(dev
, info
);
1888 px_size_sa
= get_px_size_sa(&info
->surf
);
1890 /* Because this gets called after we lower compressed images, the tile
1891 * offsets may be non-zero and we need to incorporate them in our
1894 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
1895 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
1896 isl_tiling_get_intratile_offset_sa(dev
, info
->surf
.tiling
,
1897 info
->surf
.format
, info
->surf
.row_pitch
,
1898 x_offset_sa
, y_offset_sa
,
1900 &info
->tile_x_sa
, &info
->tile_y_sa
);
1902 info
->addr
.offset
+= byte_offset
;
1904 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
1907 info
->tile_x_sa
= 0;
1909 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
1912 info
->tile_y_sa
= 0;
1914 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
1915 info
->surf
.logical_level0_px
.width
= size
;
1916 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
1918 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
1919 info
->surf
.logical_level0_px
.height
= size
;
1920 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
1924 shrink_surfaces(const struct isl_device
*dev
,
1925 struct blorp_params
*params
,
1926 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1927 struct blt_coords
*coords
)
1929 /* Shrink source surface */
1930 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
1931 &coords
->y
.src0
, &coords
->y
.src1
);
1932 wm_prog_key
->need_src_offset
= false;
1934 /* Shrink destination surface */
1935 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
1936 &coords
->y
.dst0
, &coords
->y
.dst1
);
1937 wm_prog_key
->need_dst_offset
= false;
1941 do_blorp_blit(struct blorp_batch
*batch
,
1942 const struct blorp_params
*orig_params
,
1943 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1944 const struct blt_coords
*orig
)
1946 struct blorp_params params
;
1947 struct blt_coords blit_coords
;
1948 struct blt_coords split_coords
= *orig
;
1949 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
1950 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
1951 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
1952 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
1958 bool x_done
, y_done
;
1959 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
1961 params
= *orig_params
;
1962 blit_coords
= split_coords
;
1964 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
1966 enum blit_shrink_status result
=
1967 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
1969 if (result
& BLIT_WIDTH_SHRINK
) {
1972 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
1973 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
1975 if (result
& BLIT_HEIGHT_SHRINK
) {
1978 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
1979 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
1983 assert(can_shrink_surfaces(orig_params
));
1988 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
1989 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
1992 } else if (y_done
) {
1993 split_coords
.x
.dst0
+= w
;
1994 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
1995 split_coords
.y
.dst0
= orig
->y
.dst0
;
1996 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
1997 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
1999 split_coords
.y
.dst0
+= h
;
2000 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2001 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2007 blorp_blit(struct blorp_batch
*batch
,
2008 const struct blorp_surf
*src_surf
,
2009 unsigned src_level
, unsigned src_layer
,
2010 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2011 const struct blorp_surf
*dst_surf
,
2012 unsigned dst_level
, unsigned dst_layer
,
2013 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2014 float src_x0
, float src_y0
,
2015 float src_x1
, float src_y1
,
2016 float dst_x0
, float dst_y0
,
2017 float dst_x1
, float dst_y1
,
2018 GLenum filter
, bool mirror_x
, bool mirror_y
)
2020 struct blorp_params params
;
2021 blorp_params_init(¶ms
);
2023 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2024 src_layer
, src_format
, false);
2025 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2026 dst_layer
, dst_format
, true);
2028 params
.src
.view
.swizzle
= src_swizzle
;
2029 params
.dst
.view
.swizzle
= dst_swizzle
;
2031 struct brw_blorp_blit_prog_key wm_prog_key
= {
2032 .shader_type
= BLORP_SHADER_TYPE_BLIT
2035 /* Scaled blitting or not. */
2036 wm_prog_key
.blit_scaled
=
2037 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2038 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2040 /* Scaling factors used for bilinear filtering in multisample scaled
2043 if (params
.src
.surf
.samples
== 16)
2044 wm_prog_key
.x_scale
= 4.0f
;
2046 wm_prog_key
.x_scale
= 2.0f
;
2047 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2049 if (filter
== GL_LINEAR
&&
2050 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1)
2051 wm_prog_key
.bilinear_filter
= true;
2053 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
2054 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
2055 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
2056 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
2057 /* We are downsampling a non-integer color buffer, so blend.
2059 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
2061 * "If the source formats are integer types or stencil values, a
2062 * single sample's value is selected for each pixel."
2064 * This implies we should not blend in that case.
2066 wm_prog_key
.blend
= true;
2069 params
.wm_inputs
.rect_grid
.x1
=
2070 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2071 wm_prog_key
.x_scale
- 1.0f
;
2072 params
.wm_inputs
.rect_grid
.y1
=
2073 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2074 wm_prog_key
.y_scale
- 1.0f
;
2076 struct blt_coords coords
= {
2093 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2096 static enum isl_format
2097 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2099 /* The choice of UNORM and UINT formats is very intentional here. Most
2100 * of the time, we want to use a UINT format to avoid any rounding error
2101 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2102 * (It's the only format allowed in conjunction with W-tiling.) Also we
2103 * intentionally use the 4-channel formats whenever we can. This is so
2104 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2105 * even though one of them is 3/4 the size of the other. The choice of
2106 * UNORM vs. UINT is also very intentional because we don't have 8 or
2107 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2108 * Fortunately, the only time we should ever use two different formats in
2109 * the table below is for RGB -> RGBA blits and so we will never have any
2110 * UNORM/UINT mismatch.
2112 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2114 case 8: return ISL_FORMAT_R8_UINT
;
2115 case 16: return ISL_FORMAT_R8G8_UINT
;
2116 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2117 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2118 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2119 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2120 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2121 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2123 unreachable("Unknown format bpb");
2127 case 8: return ISL_FORMAT_R8_UINT
;
2128 case 16: return ISL_FORMAT_R8G8_UINT
;
2129 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2130 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2131 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2132 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2133 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2134 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2136 unreachable("Unknown format bpb");
2141 /** Returns a UINT format that is CCS-compatible with the given format
2143 * The PRM's say absolutely nothing about how render compression works. The
2144 * only thing they provide is a list of formats on which it is and is not
2145 * supported. Empirical testing indicates that the compression is only based
2146 * on the bit-layout of the format and the channel encoding doesn't matter.
2147 * So, while texture views don't work in general, you can create a view as
2148 * long as the bit-layout of the formats are the same.
2150 * Fortunately, for every render compression capable format, the UINT format
2151 * with the same bit layout also supports render compression. This means that
2152 * we only need to handle UINT formats for copy operations. In order to do
2153 * copies between formats with different bit layouts, we attach both with a
2154 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2155 * operation between the two bit layouts.
2157 static enum isl_format
2158 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2160 switch (fmtl
->format
) {
2161 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2162 case ISL_FORMAT_R32G32B32A32_SINT
:
2163 case ISL_FORMAT_R32G32B32A32_UINT
:
2164 case ISL_FORMAT_R32G32B32A32_UNORM
:
2165 case ISL_FORMAT_R32G32B32A32_SNORM
:
2166 return ISL_FORMAT_R32G32B32A32_UINT
;
2168 case ISL_FORMAT_R16G16B16A16_UNORM
:
2169 case ISL_FORMAT_R16G16B16A16_SNORM
:
2170 case ISL_FORMAT_R16G16B16A16_SINT
:
2171 case ISL_FORMAT_R16G16B16A16_UINT
:
2172 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2173 case ISL_FORMAT_R16G16B16X16_UNORM
:
2174 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2175 return ISL_FORMAT_R16G16B16A16_UINT
;
2177 case ISL_FORMAT_R32G32_FLOAT
:
2178 case ISL_FORMAT_R32G32_SINT
:
2179 case ISL_FORMAT_R32G32_UINT
:
2180 case ISL_FORMAT_R32G32_UNORM
:
2181 case ISL_FORMAT_R32G32_SNORM
:
2182 return ISL_FORMAT_R32G32_UINT
;
2184 case ISL_FORMAT_B8G8R8A8_UNORM
:
2185 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2186 case ISL_FORMAT_R8G8B8A8_UNORM
:
2187 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2188 case ISL_FORMAT_R8G8B8A8_SNORM
:
2189 case ISL_FORMAT_R8G8B8A8_SINT
:
2190 case ISL_FORMAT_R8G8B8A8_UINT
:
2191 case ISL_FORMAT_B8G8R8X8_UNORM
:
2192 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2193 case ISL_FORMAT_R8G8B8X8_UNORM
:
2194 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2195 return ISL_FORMAT_R8G8B8A8_UINT
;
2197 case ISL_FORMAT_R16G16_UNORM
:
2198 case ISL_FORMAT_R16G16_SNORM
:
2199 case ISL_FORMAT_R16G16_SINT
:
2200 case ISL_FORMAT_R16G16_UINT
:
2201 case ISL_FORMAT_R16G16_FLOAT
:
2202 return ISL_FORMAT_R16G16_UINT
;
2204 case ISL_FORMAT_R32_SINT
:
2205 case ISL_FORMAT_R32_UINT
:
2206 case ISL_FORMAT_R32_FLOAT
:
2207 case ISL_FORMAT_R32_UNORM
:
2208 case ISL_FORMAT_R32_SNORM
:
2209 return ISL_FORMAT_R32_UINT
;
2212 unreachable("Not a compressible format");
2216 /* Takes an isl_color_value and returns a color value that is the original
2217 * color value only bit-casted to a UINT format. This value, together with
2218 * the format from get_ccs_compatible_uint_format, will yield the same bit
2219 * value as the original color and format.
2221 static union isl_color_value
2222 bitcast_color_value_to_uint(union isl_color_value color
,
2223 const struct isl_format_layout
*fmtl
)
2225 /* All CCS formats have the same number of bits in each channel */
2226 const struct isl_channel_layout
*chan
= &fmtl
->channels
.r
;
2228 union isl_color_value bits
;
2229 switch (chan
->type
) {
2232 /* Hardware will ignore the high bits so there's no need to cast */
2237 for (unsigned i
= 0; i
< 4; i
++)
2238 bits
.u32
[i
] = _mesa_float_to_unorm(color
.f32
[i
], chan
->bits
);
2242 for (unsigned i
= 0; i
< 4; i
++)
2243 bits
.i32
[i
] = _mesa_float_to_snorm(color
.f32
[i
], chan
->bits
);
2247 switch (chan
->bits
) {
2249 for (unsigned i
= 0; i
< 4; i
++)
2250 bits
.u32
[i
] = _mesa_float_to_half(color
.f32
[i
]);
2258 unreachable("Invalid float format size");
2263 unreachable("Invalid channel type");
2266 switch (fmtl
->format
) {
2267 case ISL_FORMAT_B8G8R8A8_UNORM
:
2268 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2269 case ISL_FORMAT_B8G8R8X8_UNORM
:
2270 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
: {
2271 /* If it's a BGRA format, we need to swap blue and red */
2272 uint32_t tmp
= bits
.u32
[0];
2273 bits
.u32
[0] = bits
.u32
[2];
2279 break; /* Nothing to do */
2286 surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2287 struct brw_blorp_surface_info
*info
,
2288 uint32_t *x
, uint32_t *y
,
2289 uint32_t *width
, uint32_t *height
)
2291 const struct isl_format_layout
*fmtl
=
2292 isl_format_get_layout(info
->surf
.format
);
2294 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2296 /* This is a compressed surface. We need to convert it to a single
2297 * slice (because compressed layouts don't perfectly match uncompressed
2298 * ones with the same bpb) and divide x, y, width, and height by the
2301 surf_convert_to_single_slice(isl_dev
, info
);
2303 if (width
|| height
) {
2305 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2306 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2307 assert(*width
% fmtl
->bw
== 0 ||
2308 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2309 assert(*height
% fmtl
->bh
== 0 ||
2310 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2312 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2313 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2316 assert(*x
% fmtl
->bw
== 0);
2317 assert(*y
% fmtl
->bh
== 0);
2321 info
->surf
.logical_level0_px
.width
=
2322 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
2323 info
->surf
.logical_level0_px
.height
=
2324 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
2326 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
2327 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
2328 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2329 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2331 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2332 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2333 info
->tile_x_sa
/= fmtl
->bw
;
2334 info
->tile_y_sa
/= fmtl
->bh
;
2336 /* It's now an uncompressed surface so we need an uncompressed format */
2337 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2341 blorp_copy(struct blorp_batch
*batch
,
2342 const struct blorp_surf
*src_surf
,
2343 unsigned src_level
, unsigned src_layer
,
2344 const struct blorp_surf
*dst_surf
,
2345 unsigned dst_level
, unsigned dst_layer
,
2346 uint32_t src_x
, uint32_t src_y
,
2347 uint32_t dst_x
, uint32_t dst_y
,
2348 uint32_t src_width
, uint32_t src_height
)
2350 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2351 struct blorp_params params
;
2353 if (src_width
== 0 || src_height
== 0)
2356 blorp_params_init(¶ms
);
2357 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2358 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2359 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2360 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2362 struct brw_blorp_blit_prog_key wm_prog_key
= {
2363 .shader_type
= BLORP_SHADER_TYPE_BLIT
2366 const struct isl_format_layout
*src_fmtl
=
2367 isl_format_get_layout(params
.src
.surf
.format
);
2368 const struct isl_format_layout
*dst_fmtl
=
2369 isl_format_get_layout(params
.dst
.surf
.format
);
2371 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2372 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2373 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2374 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2375 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2376 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2378 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2379 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2380 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2381 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2382 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2383 params
.src
.view
.format
= params
.dst
.view
.format
;
2385 params
.src
.view
.format
=
2386 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2388 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2389 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2390 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2391 params
.dst
.view
.format
= params
.src
.view
.format
;
2393 params
.dst
.view
.format
=
2394 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2397 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2398 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2401 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2402 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2403 src_surf
->surf
->format
,
2404 params
.src
.view
.format
));
2405 params
.src
.clear_color
=
2406 bitcast_color_value_to_uint(params
.src
.clear_color
, src_fmtl
);
2409 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2410 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2411 dst_surf
->surf
->format
,
2412 params
.dst
.view
.format
));
2413 params
.dst
.clear_color
=
2414 bitcast_color_value_to_uint(params
.dst
.clear_color
, dst_fmtl
);
2417 wm_prog_key
.src_bpc
=
2418 isl_format_get_layout(params
.src
.view
.format
)->channels
.r
.bits
;
2419 wm_prog_key
.dst_bpc
=
2420 isl_format_get_layout(params
.dst
.view
.format
)->channels
.r
.bits
;
2422 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2423 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2424 &src_x
, &src_y
, &src_width
, &src_height
);
2425 wm_prog_key
.need_src_offset
= true;
2428 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2429 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2430 &dst_x
, &dst_y
, NULL
, NULL
);
2431 wm_prog_key
.need_dst_offset
= true;
2434 /* Once both surfaces are stompped to uncompressed as needed, the
2435 * destination size is the same as the source size.
2437 uint32_t dst_width
= src_width
;
2438 uint32_t dst_height
= src_height
;
2440 struct blt_coords coords
= {
2443 .src1
= src_x
+ src_width
,
2445 .dst1
= dst_x
+ dst_width
,
2450 .src1
= src_y
+ src_height
,
2452 .dst1
= dst_y
+ dst_height
,
2457 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);