2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/nir/nir_builder.h"
26 #include "blorp_priv.h"
28 /* header-only include needed for _mesa_unorm_to_float and friends. */
29 #include "mesa/main/format_utils.h"
31 #define FILE_DEBUG_FLAG DEBUG_BLORP
33 static const bool split_blorp_blit_debug
= false;
36 * Enum to specify the order of arguments in a sampler message
38 enum sampler_message_arg
40 SAMPLER_MESSAGE_ARG_U_FLOAT
,
41 SAMPLER_MESSAGE_ARG_V_FLOAT
,
42 SAMPLER_MESSAGE_ARG_U_INT
,
43 SAMPLER_MESSAGE_ARG_V_INT
,
44 SAMPLER_MESSAGE_ARG_R_INT
,
45 SAMPLER_MESSAGE_ARG_SI_INT
,
46 SAMPLER_MESSAGE_ARG_MCS_INT
,
47 SAMPLER_MESSAGE_ARG_ZERO_INT
,
50 struct brw_blorp_blit_vars
{
51 /* Input values from brw_blorp_wm_inputs */
52 nir_variable
*v_discard_rect
;
53 nir_variable
*v_rect_grid
;
54 nir_variable
*v_coord_transform
;
55 nir_variable
*v_src_z
;
56 nir_variable
*v_src_offset
;
57 nir_variable
*v_dst_offset
;
58 nir_variable
*v_src_inv_size
;
61 nir_variable
*frag_coord
;
64 nir_variable
*color_out
;
68 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
69 const struct brw_blorp_blit_prog_key
*key
)
71 /* Blended and scaled blits never use pixel discard. */
72 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
74 #define LOAD_INPUT(name, type)\
75 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
77 LOAD_INPUT(discard_rect
, glsl_vec4_type())
78 LOAD_INPUT(rect_grid
, glsl_vec4_type())
79 LOAD_INPUT(coord_transform
, glsl_vec4_type())
80 LOAD_INPUT(src_z
, glsl_uint_type())
81 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
82 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
83 LOAD_INPUT(src_inv_size
, glsl_vector_type(GLSL_TYPE_FLOAT
, 2))
87 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
88 glsl_vec4_type(), "gl_FragCoord");
89 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
90 v
->frag_coord
->data
.origin_upper_left
= true;
92 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
93 glsl_vec4_type(), "gl_FragColor");
94 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
98 blorp_blit_get_frag_coords(nir_builder
*b
,
99 const struct brw_blorp_blit_prog_key
*key
,
100 struct brw_blorp_blit_vars
*v
)
102 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_var(b
, v
->frag_coord
));
104 /* Account for destination surface intratile offset
106 * Transformation parameters giving translation from destination to source
107 * coordinates don't take into account possible intra-tile destination
108 * offset. Therefore it has to be first subtracted from the incoming
109 * coordinates. Vertices are set up based on coordinates containing the
112 if (key
->need_dst_offset
)
113 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
115 if (key
->persample_msaa_dispatch
) {
116 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
117 nir_load_sample_id(b
));
119 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
124 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
128 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
129 struct brw_blorp_blit_vars
*v
)
131 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
133 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
134 nir_channel(b
, coord_transform
, 3));
135 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
136 nir_channel(b
, coord_transform
, 2));
138 return nir_fadd(b
, nir_fmul(b
, src_pos
, mul
), offset
);
142 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
143 struct brw_blorp_blit_vars
*v
)
145 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
146 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
147 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
148 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
149 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
150 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
152 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
153 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
154 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
155 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
157 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
159 nir_intrinsic_instr
*discard
=
160 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
161 discard
->src
[0] = nir_src_for_ssa(oob
);
162 nir_builder_instr_insert(b
, &discard
->instr
);
165 static nir_tex_instr
*
166 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
167 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
168 nir_alu_type dst_type
)
170 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
174 tex
->dest_type
= dst_type
;
175 tex
->is_array
= false;
176 tex
->is_shadow
= false;
178 /* Blorp only has one texture and it's bound at unit 0 */
181 tex
->texture_index
= 0;
182 tex
->sampler_index
= 0;
184 /* To properly handle 3-D and 2-D array textures, we pull the Z component
185 * from an input. TODO: This is a bit magic; we should probably make this
186 * more explicit in the future.
188 assert(pos
->num_components
>= 2);
189 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
190 nir_load_var(b
, v
->v_src_z
));
192 tex
->src
[0].src_type
= nir_tex_src_coord
;
193 tex
->src
[0].src
= nir_src_for_ssa(pos
);
194 tex
->coord_components
= 3;
196 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
202 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
203 const struct brw_blorp_blit_prog_key
*key
, nir_ssa_def
*pos
)
205 if (key
->need_src_offset
)
206 pos
= nir_fadd(b
, pos
, nir_i2f32(b
, nir_load_var(b
, v
->v_src_offset
)));
208 /* If the sampler requires normalized coordinates, we need to compensate. */
209 if (key
->src_coords_normalized
)
210 pos
= nir_fmul(b
, pos
, nir_load_var(b
, v
->v_src_inv_size
));
213 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2,
214 key
->texture_data_type
);
216 assert(pos
->num_components
== 2);
217 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
218 tex
->src
[1].src_type
= nir_tex_src_lod
;
219 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
221 nir_builder_instr_insert(b
, &tex
->instr
);
223 return &tex
->dest
.ssa
;
227 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
228 nir_ssa_def
*pos
, nir_alu_type dst_type
)
231 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
233 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
234 tex
->src
[1].src_type
= nir_tex_src_lod
;
235 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
237 nir_builder_instr_insert(b
, &tex
->instr
);
239 return &tex
->dest
.ssa
;
243 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
244 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
247 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
248 mcs
!= NULL
? 3 : 2, dst_type
);
250 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
252 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
253 if (pos
->num_components
== 2) {
254 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
256 assert(pos
->num_components
== 3);
257 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
261 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
262 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
265 nir_builder_instr_insert(b
, &tex
->instr
);
267 return &tex
->dest
.ssa
;
271 blorp_nir_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
, nir_ssa_def
*pos
)
274 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
275 pos
, 1, nir_type_int
);
277 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
279 nir_builder_instr_insert(b
, &tex
->instr
);
281 return &tex
->dest
.ssa
;
285 nir_mask_shift_or(struct nir_builder
*b
, nir_ssa_def
*dst
, nir_ssa_def
*src
,
286 uint32_t src_mask
, int src_left_shift
)
288 nir_ssa_def
*masked
= nir_iand(b
, src
, nir_imm_int(b
, src_mask
));
290 nir_ssa_def
*shifted
;
291 if (src_left_shift
> 0) {
292 shifted
= nir_ishl(b
, masked
, nir_imm_int(b
, src_left_shift
));
293 } else if (src_left_shift
< 0) {
294 shifted
= nir_ushr(b
, masked
, nir_imm_int(b
, -src_left_shift
));
296 assert(src_left_shift
== 0);
300 return nir_ior(b
, dst
, shifted
);
304 * Emit code to compensate for the difference between Y and W tiling.
306 * This code modifies the X and Y coordinates according to the formula:
308 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
310 * (See brw_blorp_build_nir_shader).
312 static inline nir_ssa_def
*
313 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
315 assert(pos
->num_components
== 2);
316 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
317 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
319 /* Given X and Y coordinates that describe an address using Y tiling,
320 * translate to the X and Y coordinates that describe the same address
323 * If we break down the low order bits of X and Y, using a
324 * single letter to represent each low-order bit:
326 * X = A << 7 | 0bBCDEFGH
327 * Y = J << 5 | 0bKLMNP (1)
329 * Then we can apply the Y tiling formula to see the memory offset being
332 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
334 * If we apply the W detiling formula to this memory location, that the
335 * corresponding X' and Y' coordinates are:
337 * X' = A << 6 | 0bBCDPFH (3)
338 * Y' = J << 6 | 0bKLMNEG
340 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
341 * we need to make the following computation:
343 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
344 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
346 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
347 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
348 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
349 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
351 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
352 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
353 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
354 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
356 return nir_vec2(b
, x_W
, y_W
);
360 * Emit code to compensate for the difference between Y and W tiling.
362 * This code modifies the X and Y coordinates according to the formula:
364 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
366 * (See brw_blorp_build_nir_shader).
368 static inline nir_ssa_def
*
369 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
371 assert(pos
->num_components
== 2);
372 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
373 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
375 /* Applying the same logic as above, but in reverse, we obtain the
378 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
379 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
381 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
382 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
383 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
384 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
385 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
387 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
388 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
389 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
391 return nir_vec2(b
, x_Y
, y_Y
);
395 * Emit code to compensate for the difference between MSAA and non-MSAA
398 * This code modifies the X and Y coordinates according to the formula:
400 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
402 * (See brw_blorp_blit_program).
404 static inline nir_ssa_def
*
405 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
406 unsigned num_samples
, enum isl_msaa_layout layout
)
408 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
411 case ISL_MSAA_LAYOUT_NONE
:
412 assert(pos
->num_components
== 2);
414 case ISL_MSAA_LAYOUT_ARRAY
:
415 /* No translation needed */
417 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
418 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
419 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
420 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
421 nir_channel(b
, pos
, 2);
423 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
424 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
425 switch (num_samples
) {
428 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
429 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
432 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
433 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
434 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
436 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
437 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
438 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
439 if (num_samples
== 2) {
442 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
443 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
444 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
449 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
450 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
452 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
454 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
455 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
456 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
457 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
458 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
459 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
460 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
464 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
465 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
467 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
470 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
471 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
472 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
473 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
474 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
475 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
476 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
477 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
481 unreachable("Invalid number of samples for IMS layout");
484 return nir_vec2(b
, x_out
, y_out
);
488 unreachable("Invalid MSAA layout");
493 * Emit code to compensate for the difference between MSAA and non-MSAA
496 * This code modifies the X and Y coordinates according to the formula:
498 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
500 * (See brw_blorp_blit_program).
502 static inline nir_ssa_def
*
503 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
504 unsigned num_samples
, enum isl_msaa_layout layout
)
506 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
509 case ISL_MSAA_LAYOUT_NONE
:
510 /* No translation necessary, and S should already be zero. */
511 assert(pos
->num_components
== 2);
513 case ISL_MSAA_LAYOUT_ARRAY
:
514 /* No translation necessary. */
516 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
517 assert(pos
->num_components
== 2);
519 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
520 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
522 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
523 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
524 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
525 switch (num_samples
) {
528 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
529 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
530 * S = (X & 0b10) >> 1
532 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
533 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
534 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
535 * S = (Y & 0b10) | (X & 0b10) >> 1
537 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
538 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
539 if (num_samples
== 2) {
541 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
543 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
544 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
545 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
546 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
551 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
552 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
553 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
554 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
556 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
557 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
558 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
559 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
560 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
561 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
562 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
566 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
567 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
568 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
569 * S = (Y & 0b100) << 1 | (X & 0b100) |
570 * (Y & 0b10) | (X & 0b10) >> 1
572 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
573 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
574 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
575 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
576 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
577 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
578 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
579 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
583 unreachable("Invalid number of samples for IMS layout");
586 return nir_vec3(b
, x_out
, y_out
, s_out
);
590 unreachable("Invalid MSAA layout");
595 * Count the number of trailing 1 bits in the given value. For example:
597 * count_trailing_one_bits(0) == 0
598 * count_trailing_one_bits(7) == 3
599 * count_trailing_one_bits(11) == 2
601 static inline int count_trailing_one_bits(unsigned value
)
603 #ifdef HAVE___BUILTIN_CTZ
604 return __builtin_ctz(~value
);
606 return _mesa_bitcount(value
& ~(value
+ 1));
611 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
612 nir_ssa_def
*pos
, unsigned tex_samples
,
613 enum isl_aux_usage tex_aux_usage
,
614 nir_alu_type dst_type
)
616 /* If non-null, this is the outer-most if statement */
617 nir_if
*outer_if
= NULL
;
619 nir_variable
*color
=
620 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
622 nir_ssa_def
*mcs
= NULL
;
623 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
624 mcs
= blorp_nir_txf_ms_mcs(b
, v
, pos
);
626 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
628 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
630 * This ensures that when all samples have the same value, no numerical
631 * precision is lost, since each addition operation always adds two equal
632 * values, and summing two equal floating point values does not lose
635 * We perform this computation by treating the texture_data array as a
636 * stack and performing the following operations:
638 * - push sample 0 onto stack
639 * - push sample 1 onto stack
640 * - add top two stack entries
641 * - push sample 2 onto stack
642 * - push sample 3 onto stack
643 * - add top two stack entries
644 * - add top two stack entries
645 * - divide top stack entry by 4
647 * Note that after pushing sample i onto the stack, the number of add
648 * operations we do is equal to the number of trailing 1 bits in i. This
649 * works provided the total number of samples is a power of two, which it
650 * always is for i965.
652 * For integer formats, we replace the add operations with average
653 * operations and skip the final division.
655 nir_ssa_def
*texture_data
[5];
656 unsigned stack_depth
= 0;
657 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
658 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
660 /* Push sample i onto the stack */
661 assert(stack_depth
< ARRAY_SIZE(texture_data
));
663 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
664 nir_channel(b
, pos
, 1),
666 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
668 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
669 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
670 * suggests an optimization:
672 * "A simple optimization with probable large return in
673 * performance is to compare the MCS value to zero (indicating
674 * all samples are on sample slice 0), and sample only from
675 * sample slice 0 using ld2dss if MCS is zero."
677 * Note that in the case where the MCS value is zero, sampling from
678 * sample slice 0 using ld2dss and sampling from sample 0 using
679 * ld2dms are equivalent (since all samples are on sample slice 0).
680 * Since we have already sampled from sample 0, all we need to do is
681 * skip the remaining fetches and averaging if MCS is zero.
683 nir_ssa_def
*mcs_zero
=
684 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
685 if (tex_samples
== 16) {
686 mcs_zero
= nir_iand(b
, mcs_zero
,
687 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
690 nir_if
*if_stmt
= nir_if_create(b
->shader
);
691 if_stmt
->condition
= nir_src_for_ssa(mcs_zero
);
692 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
694 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
695 nir_store_var(b
, color
, texture_data
[0], 0xf);
697 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
701 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
702 assert(stack_depth
>= 2);
705 assert(dst_type
== nir_type_float
);
706 texture_data
[stack_depth
- 1] =
707 nir_fadd(b
, texture_data
[stack_depth
- 1],
708 texture_data
[stack_depth
]);
712 /* We should have just 1 sample on the stack now. */
713 assert(stack_depth
== 1);
715 texture_data
[0] = nir_fmul(b
, texture_data
[0],
716 nir_imm_float(b
, 1.0 / tex_samples
));
718 nir_store_var(b
, color
, texture_data
[0], 0xf);
721 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
723 return nir_load_var(b
, color
);
726 static inline nir_ssa_def
*
727 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
731 memset(&v
, 0, sizeof(v
));
735 return nir_build_imm(build
, 4, 32, v
);
739 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
740 unsigned tex_samples
,
741 const struct brw_blorp_blit_prog_key
*key
,
742 struct brw_blorp_blit_vars
*v
)
744 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
745 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
746 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
748 /* Translate coordinates to lay out the samples in a rectangular grid
749 * roughly corresponding to sample locations.
751 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
752 /* Adjust coordinates so that integers represent pixel centers rather
755 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
756 /* Clamp the X, Y texture coordinates to properly handle the sampling of
757 * texels on texture edges.
759 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
760 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
761 nir_channel(b
, rect_grid
, 1)));
763 /* Store the fractional parts to be used as bilinear interpolation
766 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
767 /* Round the float coordinates down to nearest integer */
768 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
770 nir_ssa_def
*tex_data
[4];
771 for (unsigned i
= 0; i
< 4; ++i
) {
772 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
773 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
774 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
776 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
777 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
779 /* The MCS value we fetch has to match up with the pixel that we're
780 * sampling from. Since we sample from different pixels in each
781 * iteration of this "for" loop, the call to mcs_fetch() should be
782 * here inside the loop after computing the pixel coordinates.
784 nir_ssa_def
*mcs
= NULL
;
785 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
786 mcs
= blorp_nir_txf_ms_mcs(b
, v
, sample_coords_int
);
788 /* Compute sample index and map the sample index to a sample number.
789 * Sample index layout shows the numbering of slots in a rectangular
790 * grid of samples with in a pixel. Sample number layout shows the
791 * rectangular grid of samples roughly corresponding to the real sample
792 * locations with in a pixel.
793 * In case of 4x MSAA, layout of sample indices matches the layout of
801 * In case of 8x MSAA the two layouts don't match.
802 * sample index layout : --------- sample number layout : ---------
803 * | 0 | 1 | | 3 | 7 |
804 * --------- ---------
805 * | 2 | 3 | | 5 | 0 |
806 * --------- ---------
807 * | 4 | 5 | | 1 | 2 |
808 * --------- ---------
809 * | 6 | 7 | | 4 | 6 |
810 * --------- ---------
812 * Fortunately, this can be done fairly easily as:
813 * S' = (0x17306425 >> (S * 4)) & 0xf
815 * In the case of 16x MSAA the two layouts don't match.
816 * Sample index layout: Sample number layout:
817 * --------------------- ---------------------
818 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
819 * --------------------- ---------------------
820 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
821 * --------------------- ---------------------
822 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
823 * --------------------- ---------------------
824 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
825 * --------------------- ---------------------
827 * This is equivalent to
828 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
830 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
831 nir_ssa_def
*sample
=
832 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
833 key
->x_scale
* key
->y_scale
));
834 sample
= nir_f2i32(b
, sample
);
836 if (tex_samples
== 8) {
837 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
838 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
839 nir_imm_int(b
, 0xf));
840 } else if (tex_samples
== 16) {
841 nir_ssa_def
*sample_low
=
842 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
843 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
844 nir_imm_int(b
, 0xf));
845 nir_ssa_def
*sample_high
=
846 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
847 nir_ishl(b
, nir_iadd(b
, sample
,
850 nir_imm_int(b
, 0xf));
852 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
853 sample_low
, sample_high
);
855 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
856 nir_channel(b
, sample_coords_int
, 1),
858 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
861 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
862 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
863 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
864 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
868 /** Perform a color bit-cast operation
870 * For copy operations involving CCS, we may need to use different formats for
871 * the source and destination surfaces. The two formats must both be UINT
872 * formats and must have the same size but may have different bit layouts.
873 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
874 * to R16G16_UINT. This function generates code to shuffle bits around to get
875 * us from one to the other.
878 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
879 const struct brw_blorp_blit_prog_key
*key
)
881 assert(key
->texture_data_type
== nir_type_uint
);
883 if (key
->dst_bpc
> key
->src_bpc
) {
884 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
885 nir_ssa_def
*dst_chan
[2] = { u
, u
};
887 unsigned dst_idx
= 0;
888 for (unsigned i
= 0; i
< 4; i
++) {
889 nir_ssa_def
*shifted
= nir_ishl(b
, nir_channel(b
, color
, i
),
890 nir_imm_int(b
, shift
));
892 dst_chan
[dst_idx
] = shifted
;
894 dst_chan
[dst_idx
] = nir_ior(b
, dst_chan
[dst_idx
], shifted
);
897 shift
+= key
->src_bpc
;
898 if (shift
>= key
->dst_bpc
) {
904 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], u
, u
);
906 assert(key
->dst_bpc
< key
->src_bpc
);
908 nir_ssa_def
*mask
= nir_imm_int(b
, ~0u >> (32 - key
->dst_bpc
));
910 nir_ssa_def
*dst_chan
[4];
911 unsigned src_idx
= 0;
913 for (unsigned i
= 0; i
< 4; i
++) {
914 dst_chan
[i
] = nir_iand(b
, nir_ushr(b
, nir_channel(b
, color
, src_idx
),
915 nir_imm_int(b
, shift
)),
917 shift
+= key
->dst_bpc
;
918 if (shift
>= key
->src_bpc
) {
924 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], dst_chan
[2], dst_chan
[3]);
929 * Generator for WM programs used in BLORP blits.
931 * The bulk of the work done by the WM program is to wrap and unwrap the
932 * coordinate transformations used by the hardware to store surfaces in
933 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
934 * sample index for a multisampled surface) to a memory offset by the
935 * following formulas:
937 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
938 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
940 * For a single-sampled surface, or for a multisampled surface using
941 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
944 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
945 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
946 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
947 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
949 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
950 * embeds the sample number into bit 1 of the X and Y coordinates:
952 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
953 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
954 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
955 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
956 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
957 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
958 * S = (Y & 0b10) | (X & 0b10) >> 1
960 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
961 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
964 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
965 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
966 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
967 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
968 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
969 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
970 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
972 * For X tiling, tile() combines together the low-order bits of the X and Y
973 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
974 * bytes wide and 8 rows high:
976 * tile(x_tiled, X, Y, S) = A
977 * where A = tile_num << 12 | offset
978 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
979 * offset = (Y' & 0b111) << 9
980 * | (X & 0b111111111)
982 * Y' = Y + S * qpitch
983 * detile(x_tiled, A) = (X, Y, S)
987 * Y' = (tile_num / tile_pitch) << 3
988 * | (A & 0b111000000000) >> 9
989 * X' = (tile_num % tile_pitch) << 9
990 * | (A & 0b111111111)
992 * (In all tiling formulas, cpp is the number of bytes occupied by a single
993 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
994 * to fill the width of the surface, and qpitch is the spacing (in rows)
995 * between array slices).
997 * For Y tiling, tile() combines together the low-order bits of the X and Y
998 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
999 * bytes wide and 32 rows high:
1001 * tile(y_tiled, X, Y, S) = A
1002 * where A = tile_num << 12 | offset
1003 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
1004 * offset = (X' & 0b1110000) << 5
1005 * | (Y' & 0b11111) << 4
1008 * Y' = Y + S * qpitch
1009 * detile(y_tiled, A) = (X, Y, S)
1010 * where X = X' / cpp
1013 * Y' = (tile_num / tile_pitch) << 5
1014 * | (A & 0b111110000) >> 4
1015 * X' = (tile_num % tile_pitch) << 7
1016 * | (A & 0b111000000000) >> 5
1019 * For W tiling, tile() combines together the low-order bits of the X and Y
1020 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1021 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1022 * buffers, which always have cpp = 1 and S=0):
1024 * tile(w_tiled, X, Y, S) = A
1025 * where A = tile_num << 12 | offset
1026 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1027 * offset = (X' & 0b111000) << 6
1028 * | (Y' & 0b111100) << 3
1029 * | (X' & 0b100) << 2
1030 * | (Y' & 0b10) << 2
1031 * | (X' & 0b10) << 1
1035 * Y' = Y + S * qpitch
1036 * detile(w_tiled, A) = (X, Y, S)
1037 * where X = X' / cpp = X'
1038 * Y = Y' % qpitch = Y'
1039 * S = Y / qpitch = 0
1040 * Y' = (tile_num / tile_pitch) << 6
1041 * | (A & 0b111100000) >> 3
1042 * | (A & 0b1000) >> 2
1044 * X' = (tile_num % tile_pitch) << 6
1045 * | (A & 0b111000000000) >> 6
1046 * | (A & 0b10000) >> 2
1047 * | (A & 0b100) >> 1
1050 * Finally, for a non-tiled surface, tile() simply combines together the X and
1051 * Y coordinates in the natural way:
1053 * tile(untiled, X, Y, S) = A
1054 * where A = Y * pitch + X'
1056 * Y' = Y + S * qpitch
1057 * detile(untiled, A) = (X, Y, S)
1058 * where X = X' / cpp
1064 * (In these formulas, pitch is the number of bytes occupied by a single row
1068 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1069 const struct brw_blorp_blit_prog_key
*key
)
1071 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1072 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1075 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1076 /* If the destination image is W tiled and multisampled, then the thread
1077 * must be dispatched once per sample, not once per pixel. This is
1078 * necessary because after conversion between W and Y tiling, there's no
1079 * guarantee that all samples corresponding to a single pixel will still
1082 assert(key
->persample_msaa_dispatch
);
1086 /* We are blending, which means we won't have an opportunity to
1087 * translate the tiling and sample count for the texture surface. So
1088 * the surface state for the texture must be configured with the correct
1089 * tiling and sample count.
1091 assert(!key
->src_tiled_w
);
1092 assert(key
->tex_samples
== key
->src_samples
);
1093 assert(key
->tex_layout
== key
->src_layout
);
1094 assert(key
->tex_samples
> 0);
1097 if (key
->persample_msaa_dispatch
) {
1098 /* It only makes sense to do persample dispatch if the render target is
1099 * configured as multisampled.
1101 assert(key
->rt_samples
> 0);
1104 /* Make sure layout is consistent with sample count */
1105 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1106 (key
->tex_samples
<= 1));
1107 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1108 (key
->rt_samples
<= 1));
1109 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1110 (key
->src_samples
<= 1));
1111 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1112 (key
->dst_samples
<= 1));
1115 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1117 struct brw_blorp_blit_vars v
;
1118 brw_blorp_blit_vars_init(&b
, &v
, key
);
1120 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1122 /* Render target and texture hardware don't support W tiling until Gen8. */
1123 const bool rt_tiled_w
= false;
1124 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1126 /* The address that data will be written to is determined by the
1127 * coordinates supplied to the WM thread and the tiling and sample count of
1128 * the render target, according to the formula:
1130 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1132 * If the actual tiling and sample count of the destination surface are not
1133 * the same as the configuration of the render target, then these
1134 * coordinates are wrong and we have to adjust them to compensate for the
1137 if (rt_tiled_w
!= key
->dst_tiled_w
||
1138 key
->rt_samples
!= key
->dst_samples
||
1139 key
->rt_layout
!= key
->dst_layout
) {
1140 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1142 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1143 if (rt_tiled_w
!= key
->dst_tiled_w
)
1144 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1145 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1146 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1150 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1152 * That is: X, Y and S now contain the true coordinates and sample index of
1153 * the data that the WM thread should output.
1155 * If we need to kill pixels that are outside the destination rectangle,
1156 * now is the time to do it.
1158 if (key
->use_kill
) {
1159 assert(!(key
->blend
&& key
->blit_scaled
));
1160 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1163 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1164 if (dst_pos
->num_components
== 3) {
1165 /* The sample coordinate is an integer that we want left alone but
1166 * blorp_blit_apply_transform() blindly applies the transform to all
1167 * three coordinates. Grab the original sample index.
1169 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1170 nir_channel(&b
, src_pos
, 1),
1171 nir_channel(&b
, dst_pos
, 2));
1174 /* If the source image is not multisampled, then we want to fetch sample
1175 * number 0, because that's the only sample there is.
1177 if (key
->src_samples
== 1)
1178 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1180 /* X, Y, and S are now the coordinates of the pixel in the source image
1181 * that we want to texture from. Exception: if we are blending, then S is
1182 * irrelevant, because we are going to fetch all samples.
1184 if (key
->blend
&& !key
->blit_scaled
) {
1185 /* Resolves (effecively) use texelFetch, so we need integers and we
1186 * don't care about the sample index if we got one.
1188 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1190 if (devinfo
->gen
== 6) {
1191 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1192 * blending we need with a single linear-interpolated texture lookup
1193 * at the center of the sample. The texture coordinates to be odd
1194 * integers so that they correspond to the center of a 2x2 block
1195 * representing the four samples that maxe up a pixel. So we need
1196 * to multiply our X and Y coordinates each by 2 and then add 1.
1198 assert(key
->src_coords_normalized
);
1199 src_pos
= nir_fadd(&b
,
1200 nir_i2f32(&b
, src_pos
),
1201 nir_imm_float(&b
, 0.5f
));
1202 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1204 /* Gen7+ hardware doesn't automaticaly blend. */
1205 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1207 key
->texture_data_type
);
1209 } else if (key
->blend
&& key
->blit_scaled
) {
1210 assert(!key
->use_kill
);
1211 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1213 if (key
->bilinear_filter
) {
1214 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1216 /* We're going to use texelFetch, so we need integers */
1217 if (src_pos
->num_components
== 2) {
1218 src_pos
= nir_f2i32(&b
, src_pos
);
1220 assert(src_pos
->num_components
== 3);
1221 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1222 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1223 nir_channel(&b
, src_pos
, 2));
1226 /* We aren't blending, which means we just want to fetch a single
1227 * sample from the source surface. The address that we want to fetch
1228 * from is related to the X, Y and S values according to the formula:
1230 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1232 * If the actual tiling and sample count of the source surface are
1233 * not the same as the configuration of the texture, then we need to
1234 * adjust the coordinates to compensate for the difference.
1236 if (tex_tiled_w
!= key
->src_tiled_w
||
1237 key
->tex_samples
!= key
->src_samples
||
1238 key
->tex_layout
!= key
->src_layout
) {
1239 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1241 /* Now (X, Y, S) = detile(src_tiling, offset) */
1242 if (tex_tiled_w
!= key
->src_tiled_w
)
1243 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1244 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1245 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1249 if (key
->need_src_offset
)
1250 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1252 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1254 * In other words: X, Y, and S now contain values which, when passed to
1255 * the texturing unit, will cause data to be read from the correct
1256 * memory location. So we can fetch the texel now.
1258 if (key
->src_samples
== 1) {
1259 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1261 nir_ssa_def
*mcs
= NULL
;
1262 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1263 mcs
= blorp_nir_txf_ms_mcs(&b
, &v
, src_pos
);
1265 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1270 if (key
->dst_bpc
!= key
->src_bpc
)
1271 color
= bit_cast_color(&b
, color
, key
);
1274 /* The destination image is bound as a red texture three times as wide
1275 * as the actual image. Our shader is effectively running one color
1276 * component at a time. We need to pick off the appropriate component
1277 * from the source color and write that to destination red.
1279 assert(dst_pos
->num_components
== 2);
1281 nir_umod(&b
, nir_channel(&b
, dst_pos
, 0), nir_imm_int(&b
, 3));
1283 nir_ssa_def
*color_component
=
1284 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1285 nir_channel(&b
, color
, 0),
1286 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1287 nir_channel(&b
, color
, 1),
1288 nir_channel(&b
, color
, 2)));
1290 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1291 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1294 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1300 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1301 struct blorp_params
*params
,
1302 const struct brw_blorp_blit_prog_key
*prog_key
)
1304 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1305 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1308 void *mem_ctx
= ralloc_context(NULL
);
1310 const unsigned *program
;
1311 unsigned program_size
;
1312 struct brw_wm_prog_data prog_data
;
1314 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1315 nir
->info
.name
= ralloc_strdup(nir
, "BLORP-blit");
1317 struct brw_wm_prog_key wm_key
;
1318 brw_blorp_init_wm_prog_key(&wm_key
);
1319 wm_key
.tex
.compressed_multisample_layout_mask
=
1320 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1321 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1322 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1324 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1325 &prog_data
, &program_size
);
1328 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1329 program
, program_size
,
1330 &prog_data
.base
, sizeof(prog_data
),
1331 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1333 ralloc_free(mem_ctx
);
1338 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1339 GLfloat src0
, GLfloat src1
,
1340 GLfloat dst0
, GLfloat dst1
,
1343 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1345 /* When not mirroring a coordinate (say, X), we need:
1346 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1348 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1350 * blorp program uses "round toward zero" to convert the
1351 * transformed floating point coordinates to integer coordinates,
1352 * whereas the behaviour we actually want is "round to nearest",
1353 * so 0.5 provides the necessary correction.
1355 xform
->multiplier
= scale
;
1356 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1358 /* When mirroring X we need:
1359 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1361 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1363 xform
->multiplier
= -scale
;
1364 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1369 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1370 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1372 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1373 struct isl_extent2d px_size_sa
=
1374 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1375 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1376 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1377 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1378 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1380 *tile_x_px
= info
->tile_x_sa
;
1381 *tile_y_px
= info
->tile_y_sa
;
1386 blorp_surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1387 struct brw_blorp_surface_info
*info
)
1391 /* Just bail if we have nothing to do. */
1392 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1393 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1394 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1397 /* If this gets triggered then we've gotten here twice which. This
1398 * shouldn't happen thanks to the above early return.
1400 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1402 uint32_t layer
= 0, z
= 0;
1403 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1404 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1406 layer
= info
->view
.base_array_layer
;
1408 uint32_t byte_offset
;
1409 isl_surf_get_image_offset_B_tile_sa(&info
->surf
,
1410 info
->view
.base_level
, layer
, z
,
1412 &info
->tile_x_sa
, &info
->tile_y_sa
);
1413 info
->addr
.offset
+= byte_offset
;
1415 const uint32_t slice_width_px
=
1416 minify(info
->surf
.logical_level0_px
.width
, info
->view
.base_level
);
1417 const uint32_t slice_height_px
=
1418 minify(info
->surf
.logical_level0_px
.height
, info
->view
.base_level
);
1420 uint32_t tile_x_px
, tile_y_px
;
1421 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1423 /* Even for cube maps there will be only single face, therefore drop the
1424 * corresponding flag if present.
1426 const isl_surf_usage_flags_t without_cube_map_flag
=
1427 info
->surf
.usage
& (~ISL_SURF_USAGE_CUBE_BIT
);
1429 struct isl_surf_init_info init_info
= {
1430 .dim
= ISL_SURF_DIM_2D
,
1431 .format
= info
->surf
.format
,
1432 .width
= slice_width_px
+ tile_x_px
,
1433 .height
= slice_height_px
+ tile_y_px
,
1437 .samples
= info
->surf
.samples
,
1438 .row_pitch
= info
->surf
.row_pitch
,
1439 .usage
= without_cube_map_flag
,
1440 .tiling_flags
= 1 << info
->surf
.tiling
,
1443 ok
= isl_surf_init_s(isl_dev
, &info
->surf
, &init_info
);
1446 /* The view is also different now. */
1447 info
->view
.base_level
= 0;
1448 info
->view
.levels
= 1;
1449 info
->view
.base_array_layer
= 0;
1450 info
->view
.array_len
= 1;
1455 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1456 struct brw_blorp_surface_info
*info
)
1458 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1460 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1461 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1463 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1464 info
->surf
.samples
= 1;
1465 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1469 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1470 struct brw_blorp_surface_info
*info
)
1472 assert(info
->surf
.tiling
== ISL_TILING_W
);
1474 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1475 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1477 /* On gen7+, we don't have interleaved multisampling for color render
1478 * targets so we have to fake it.
1480 * TODO: Are we sure we don't also need to fake it on gen6?
1482 if (isl_dev
->info
->gen
> 6 &&
1483 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1484 surf_fake_interleaved_msaa(isl_dev
, info
);
1487 if (isl_dev
->info
->gen
== 6) {
1488 /* Gen6 stencil buffers have a very large alignment coming in from the
1489 * miptree. It's out-of-bounds for what the surface state can handle.
1490 * Since we have a single layer and level, it doesn't really matter as
1491 * long as we don't pass a bogus value into isl_surf_fill_state().
1493 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1496 /* Now that we've converted everything to a simple 2-D surface with only
1497 * one miplevel, we can go about retiling it.
1499 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1500 info
->surf
.tiling
= ISL_TILING_Y0
;
1501 info
->surf
.logical_level0_px
.width
=
1502 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1503 info
->surf
.logical_level0_px
.height
=
1504 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1505 info
->tile_x_sa
*= 2;
1506 info
->tile_y_sa
/= 2;
1510 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1512 /* The current code doesn't support offsets into the aux buffers. This
1513 * should be possible, but we need to make sure the offset is page
1514 * aligned for both the surface and the aux buffer surface. Generally
1515 * this mean using the page aligned offset for the aux buffer.
1517 * Currently the cases where we must split the blit are limited to cases
1518 * where we don't have a aux buffer.
1520 if (surf
->aux_addr
.buffer
!= NULL
)
1523 /* We can't support splitting the blit for gen <= 7, because the qpitch
1524 * size is calculated by the hardware based on the surface height for
1525 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1527 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1534 can_shrink_surfaces(const struct blorp_params
*params
)
1537 can_shrink_surface(¶ms
->src
) &&
1538 can_shrink_surface(¶ms
->dst
);
1542 get_max_surface_size(const struct gen_device_info
*devinfo
,
1543 const struct blorp_params
*params
)
1545 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1546 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1547 return max
>> 4; /* A smaller restriction when debug is enabled */
1553 double src0
, src1
, dst0
, dst1
;
1558 struct blt_axis x
, y
;
1562 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1563 struct brw_blorp_surface_info
*info
,
1564 uint32_t *x
, uint32_t *width
)
1566 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1568 info
->surf
.logical_level0_px
.width
*= 3;
1569 info
->surf
.phys_level0_sa
.width
*= 3;
1573 enum isl_format red_format
;
1574 switch (info
->view
.format
) {
1575 case ISL_FORMAT_R8G8B8_UNORM
:
1576 red_format
= ISL_FORMAT_R8_UNORM
;
1578 case ISL_FORMAT_R8G8B8_UINT
:
1579 red_format
= ISL_FORMAT_R8_UINT
;
1581 case ISL_FORMAT_R16G16B16_UNORM
:
1582 red_format
= ISL_FORMAT_R16_UNORM
;
1584 case ISL_FORMAT_R16G16B16_UINT
:
1585 red_format
= ISL_FORMAT_R16_UINT
;
1587 case ISL_FORMAT_R32G32B32_UINT
:
1588 red_format
= ISL_FORMAT_R32_UINT
;
1591 unreachable("Invalid RGB copy destination format");
1593 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1594 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1595 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1596 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1598 info
->surf
.format
= info
->view
.format
= red_format
;
1602 fake_dest_rgb_with_red(const struct isl_device
*dev
,
1603 struct blorp_params
*params
,
1604 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1605 struct blt_coords
*coords
)
1607 /* Handle RGB destinations for blorp_copy */
1608 const struct isl_format_layout
*dst_fmtl
=
1609 isl_format_get_layout(params
->dst
.surf
.format
);
1611 if (dst_fmtl
->bpb
% 3 == 0) {
1612 uint32_t dst_x
= coords
->x
.dst0
;
1613 uint32_t dst_width
= coords
->x
.dst1
- dst_x
;
1614 surf_fake_rgb_with_red(dev
, ¶ms
->dst
,
1615 &dst_x
, &dst_width
);
1616 coords
->x
.dst0
= dst_x
;
1617 coords
->x
.dst1
= dst_x
+ dst_width
;
1618 wm_prog_key
->dst_rgb
= true;
1619 wm_prog_key
->need_dst_offset
= true;
1623 enum blit_shrink_status
{
1625 BLIT_WIDTH_SHRINK
= 1,
1626 BLIT_HEIGHT_SHRINK
= 2,
1629 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1630 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1631 * returned, then the blit was successful.
1633 static enum blit_shrink_status
1634 try_blorp_blit(struct blorp_batch
*batch
,
1635 struct blorp_params
*params
,
1636 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1637 struct blt_coords
*coords
)
1639 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1641 fake_dest_rgb_with_red(batch
->blorp
->isl_dev
, params
, wm_prog_key
, coords
);
1643 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1644 wm_prog_key
->texture_data_type
= nir_type_int
;
1645 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1646 wm_prog_key
->texture_data_type
= nir_type_uint
;
1648 wm_prog_key
->texture_data_type
= nir_type_float
;
1651 /* src_samples and dst_samples are the true sample counts */
1652 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1653 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1655 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1657 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1660 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1661 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1663 /* Round floating point values to nearest integer to avoid "off by one texel"
1664 * kind of errors when blitting.
1666 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1667 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1668 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1669 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1671 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1672 coords
->x
.src0
, coords
->x
.src1
,
1673 coords
->x
.dst0
, coords
->x
.dst1
,
1675 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1676 coords
->y
.src0
, coords
->y
.src1
,
1677 coords
->y
.dst0
, coords
->y
.dst1
,
1681 if (devinfo
->gen
== 4) {
1682 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
1683 * Convert them to a single slice on gen4.
1685 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1686 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1687 wm_prog_key
->need_dst_offset
= true;
1690 if (params
->src
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1691 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->src
);
1692 wm_prog_key
->need_src_offset
= true;
1696 if (devinfo
->gen
> 6 &&
1697 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1698 assert(params
->dst
.surf
.samples
> 1);
1700 /* We must expand the rectangle we send through the rendering pipeline,
1701 * to account for the fact that we are mapping the destination region as
1702 * single-sampled when it is in fact multisampled. We must also align
1703 * it to a multiple of the multisampling pattern, because the
1704 * differences between multisampled and single-sampled surface formats
1705 * will mean that pixels are scrambled within the multisampling pattern.
1706 * TODO: what if this makes the coordinates too large?
1708 * Note: this only works if the destination surface uses the IMS layout.
1709 * If it's UMS, then we have no choice but to set up the rendering
1710 * pipeline as multisampled.
1712 struct isl_extent2d px_size_sa
=
1713 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1714 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1715 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1716 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1717 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1719 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1721 wm_prog_key
->use_kill
= true;
1722 wm_prog_key
->need_dst_offset
= true;
1725 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1726 /* We must modify the rectangle we send through the rendering pipeline
1727 * (and the size and x/y offset of the destination surface), to account
1728 * for the fact that we are mapping it as Y-tiled when it is in fact
1731 * Both Y tiling and W tiling can be understood as organizations of
1732 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1733 * is different, but the layout of the 32-byte sub-tiles within the 4k
1734 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1735 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1736 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1738 * Therefore, to account for the layout differences within the 32-byte
1739 * sub-tiles, we must expand the rectangle so the X coordinates of its
1740 * edges are multiples of 8 (the W sub-tile width), and its Y
1741 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1742 * Then we need to scale the X and Y coordinates of the rectangle to
1743 * account for the differences in aspect ratio between the Y and W
1744 * sub-tiles. We need to modify the layer width and height similarly.
1746 * A correction needs to be applied when MSAA is in use: since
1747 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1748 * we need to align the Y coordinates to multiples of 8, so that when
1749 * they are divided by two they are still multiples of 4.
1751 * Note: Since the x/y offset of the surface will be applied using the
1752 * SURFACE_STATE command packet, it will be invisible to the swizzling
1753 * code in the shader; therefore it needs to be in a multiple of the
1754 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1755 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1756 * buffer), and the miplevel alignment used for stencil buffers is 8
1757 * pixels horizontally and either 4 or 8 pixels vertically (see
1758 * intel_horizontal_texture_alignment_unit() and
1759 * intel_vertical_texture_alignment_unit()).
1761 * Note: Also, since the SURFACE_STATE command packet can only apply
1762 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1763 * vertically, it is important that the offsets will be multiples of
1764 * these sizes after they are converted into Y-tiled coordinates.
1765 * Fortunately they will be, since we know from above that the offsets
1766 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1767 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1769 * TODO: what if this makes the coordinates (or the texture size) too
1772 const unsigned x_align
= 8;
1773 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1774 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1775 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1776 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1777 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1779 /* Retile the surface to Y-tiled */
1780 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1782 wm_prog_key
->dst_tiled_w
= true;
1783 wm_prog_key
->use_kill
= true;
1784 wm_prog_key
->need_dst_offset
= true;
1786 if (params
->dst
.surf
.samples
> 1) {
1787 /* If the destination surface is a W-tiled multisampled stencil
1788 * buffer that we're mapping as Y tiled, then we need to arrange for
1789 * the WM program to run once per sample rather than once per pixel,
1790 * because the memory layout of related samples doesn't match between
1793 wm_prog_key
->persample_msaa_dispatch
= true;
1797 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1798 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1799 * Broadwell adds support for sampling from stencil.
1801 * See the comments above concerning x/y offset alignment for the
1802 * destination surface.
1804 * TODO: what if this makes the texture size too large?
1806 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1808 wm_prog_key
->src_tiled_w
= true;
1809 wm_prog_key
->need_src_offset
= true;
1812 /* tex_samples and rt_samples are the sample counts that are set up in
1815 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1816 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1818 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1819 * use to access the source and destination surfaces.
1821 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1822 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1824 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1825 /* We are blitting from a multisample buffer to a multisample buffer, so
1826 * we must preserve samples within a pixel. This means we have to
1827 * arrange for the WM program to run once per sample rather than once
1830 wm_prog_key
->persample_msaa_dispatch
= true;
1833 params
->num_samples
= params
->dst
.surf
.samples
;
1835 if ((wm_prog_key
->bilinear_filter
||
1836 (wm_prog_key
->blend
&& !wm_prog_key
->blit_scaled
)) &&
1837 batch
->blorp
->isl_dev
->info
->gen
<= 6) {
1838 /* Gen4-5 don't support non-normalized texture coordinates */
1839 wm_prog_key
->src_coords_normalized
= true;
1840 params
->wm_inputs
.src_inv_size
[0] =
1841 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.width
,
1842 params
->src
.view
.base_level
);
1843 params
->wm_inputs
.src_inv_size
[1] =
1844 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.height
,
1845 params
->src
.view
.base_level
);
1848 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
1849 assert(wm_prog_key
->need_src_offset
);
1850 surf_get_intratile_offset_px(¶ms
->src
,
1851 ¶ms
->wm_inputs
.src_offset
.x
,
1852 ¶ms
->wm_inputs
.src_offset
.y
);
1855 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
1856 assert(wm_prog_key
->need_dst_offset
);
1857 surf_get_intratile_offset_px(¶ms
->dst
,
1858 ¶ms
->wm_inputs
.dst_offset
.x
,
1859 ¶ms
->wm_inputs
.dst_offset
.y
);
1860 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
1861 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
1862 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
1863 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
1866 /* For some texture types, we need to pass the layer through the sampler. */
1867 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
1869 if (!brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
))
1872 if (!blorp_ensure_sf_program(batch
->blorp
, params
))
1875 unsigned result
= 0;
1876 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
1877 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
1878 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
1879 result
|= BLIT_WIDTH_SHRINK
;
1880 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
1881 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
1882 result
|= BLIT_HEIGHT_SHRINK
;
1885 batch
->blorp
->exec(batch
, params
);
1891 /* Adjust split blit source coordinates for the current destination
1895 adjust_split_source_coords(const struct blt_axis
*orig
,
1896 struct blt_axis
*split_coords
,
1899 /* When scale is greater than 0, then we are growing from the start, so
1900 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
1901 * source range shrinks from the end. In that case src0 is adjusted by
1902 * delta1, and src1 is adjusted by delta0.
1904 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
1905 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
1906 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
1907 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
1910 static struct isl_extent2d
1911 get_px_size_sa(const struct isl_surf
*surf
)
1913 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
1915 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
1918 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
1922 shrink_surface_params(const struct isl_device
*dev
,
1923 struct brw_blorp_surface_info
*info
,
1924 double *x0
, double *x1
, double *y0
, double *y1
)
1926 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
1927 struct isl_extent2d px_size_sa
;
1930 blorp_surf_convert_to_single_slice(dev
, info
);
1932 px_size_sa
= get_px_size_sa(&info
->surf
);
1934 /* Because this gets called after we lower compressed images, the tile
1935 * offsets may be non-zero and we need to incorporate them in our
1938 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
1939 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
1940 isl_tiling_get_intratile_offset_sa(info
->surf
.tiling
,
1941 info
->surf
.format
, info
->surf
.row_pitch
,
1942 x_offset_sa
, y_offset_sa
,
1944 &info
->tile_x_sa
, &info
->tile_y_sa
);
1946 info
->addr
.offset
+= byte_offset
;
1948 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
1951 info
->tile_x_sa
= 0;
1953 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
1956 info
->tile_y_sa
= 0;
1958 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
1959 info
->surf
.logical_level0_px
.width
= size
;
1960 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
1962 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
1963 info
->surf
.logical_level0_px
.height
= size
;
1964 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
1968 shrink_surfaces(const struct isl_device
*dev
,
1969 struct blorp_params
*params
,
1970 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1971 struct blt_coords
*coords
)
1973 /* Shrink source surface */
1974 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
1975 &coords
->y
.src0
, &coords
->y
.src1
);
1976 wm_prog_key
->need_src_offset
= false;
1978 /* Shrink destination surface */
1979 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
1980 &coords
->y
.dst0
, &coords
->y
.dst1
);
1981 wm_prog_key
->need_dst_offset
= false;
1985 do_blorp_blit(struct blorp_batch
*batch
,
1986 const struct blorp_params
*orig_params
,
1987 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1988 const struct blt_coords
*orig
)
1990 struct blorp_params params
;
1991 struct blt_coords blit_coords
;
1992 struct blt_coords split_coords
= *orig
;
1993 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
1994 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
1995 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
1996 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
2002 bool x_done
, y_done
;
2003 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
2005 params
= *orig_params
;
2006 blit_coords
= split_coords
;
2008 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
2010 enum blit_shrink_status result
=
2011 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
2013 if (result
& BLIT_WIDTH_SHRINK
) {
2016 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2017 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2019 if (result
& BLIT_HEIGHT_SHRINK
) {
2022 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2023 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2027 assert(can_shrink_surfaces(orig_params
));
2032 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
2033 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
2036 } else if (y_done
) {
2037 split_coords
.x
.dst0
+= w
;
2038 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2039 split_coords
.y
.dst0
= orig
->y
.dst0
;
2040 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2041 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2043 split_coords
.y
.dst0
+= h
;
2044 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2045 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2051 blorp_blit(struct blorp_batch
*batch
,
2052 const struct blorp_surf
*src_surf
,
2053 unsigned src_level
, unsigned src_layer
,
2054 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2055 const struct blorp_surf
*dst_surf
,
2056 unsigned dst_level
, unsigned dst_layer
,
2057 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2058 float src_x0
, float src_y0
,
2059 float src_x1
, float src_y1
,
2060 float dst_x0
, float dst_y0
,
2061 float dst_x1
, float dst_y1
,
2062 GLenum filter
, bool mirror_x
, bool mirror_y
)
2064 struct blorp_params params
;
2065 blorp_params_init(¶ms
);
2067 /* We cannot handle combined depth and stencil. */
2068 if (src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2069 assert(src_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2070 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2071 assert(dst_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2073 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
2074 assert(src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
);
2075 /* Prior to Broadwell, we can't render to R8_UINT */
2076 if (batch
->blorp
->isl_dev
->info
->gen
< 8) {
2077 src_format
= ISL_FORMAT_R8_UNORM
;
2078 dst_format
= ISL_FORMAT_R8_UNORM
;
2082 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2083 src_layer
, src_format
, false);
2084 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2085 dst_layer
, dst_format
, true);
2087 params
.src
.view
.swizzle
= src_swizzle
;
2088 params
.dst
.view
.swizzle
= dst_swizzle
;
2090 struct brw_blorp_blit_prog_key wm_prog_key
= {
2091 .shader_type
= BLORP_SHADER_TYPE_BLIT
2094 /* Scaled blitting or not. */
2095 wm_prog_key
.blit_scaled
=
2096 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2097 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2099 /* Scaling factors used for bilinear filtering in multisample scaled
2102 if (params
.src
.surf
.samples
== 16)
2103 wm_prog_key
.x_scale
= 4.0f
;
2105 wm_prog_key
.x_scale
= 2.0f
;
2106 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2108 if (filter
== GL_LINEAR
&&
2109 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1) {
2110 wm_prog_key
.bilinear_filter
= true;
2113 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
2114 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
2115 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
2116 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
2117 /* We are downsampling a non-integer color buffer, so blend.
2119 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
2121 * "If the source formats are integer types or stencil values, a
2122 * single sample's value is selected for each pixel."
2124 * This implies we should not blend in that case.
2126 wm_prog_key
.blend
= true;
2129 params
.wm_inputs
.rect_grid
.x1
=
2130 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2131 wm_prog_key
.x_scale
- 1.0f
;
2132 params
.wm_inputs
.rect_grid
.y1
=
2133 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2134 wm_prog_key
.y_scale
- 1.0f
;
2136 struct blt_coords coords
= {
2153 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2156 static enum isl_format
2157 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2159 /* The choice of UNORM and UINT formats is very intentional here. Most
2160 * of the time, we want to use a UINT format to avoid any rounding error
2161 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2162 * (It's the only format allowed in conjunction with W-tiling.) Also we
2163 * intentionally use the 4-channel formats whenever we can. This is so
2164 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2165 * even though one of them is 3/4 the size of the other. The choice of
2166 * UNORM vs. UINT is also very intentional because we don't have 8 or
2167 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2168 * Fortunately, the only time we should ever use two different formats in
2169 * the table below is for RGB -> RGBA blits and so we will never have any
2170 * UNORM/UINT mismatch.
2172 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2174 case 8: return ISL_FORMAT_R8_UINT
;
2175 case 16: return ISL_FORMAT_R8G8_UINT
;
2176 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2177 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2178 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2179 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2180 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2181 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2183 unreachable("Unknown format bpb");
2187 case 8: return ISL_FORMAT_R8_UINT
;
2188 case 16: return ISL_FORMAT_R8G8_UINT
;
2189 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2190 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2191 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2192 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2193 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2194 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2196 unreachable("Unknown format bpb");
2201 /** Returns a UINT format that is CCS-compatible with the given format
2203 * The PRM's say absolutely nothing about how render compression works. The
2204 * only thing they provide is a list of formats on which it is and is not
2205 * supported. Empirical testing indicates that the compression is only based
2206 * on the bit-layout of the format and the channel encoding doesn't matter.
2207 * So, while texture views don't work in general, you can create a view as
2208 * long as the bit-layout of the formats are the same.
2210 * Fortunately, for every render compression capable format, the UINT format
2211 * with the same bit layout also supports render compression. This means that
2212 * we only need to handle UINT formats for copy operations. In order to do
2213 * copies between formats with different bit layouts, we attach both with a
2214 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2215 * operation between the two bit layouts.
2217 static enum isl_format
2218 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2220 switch (fmtl
->format
) {
2221 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2222 case ISL_FORMAT_R32G32B32A32_SINT
:
2223 case ISL_FORMAT_R32G32B32A32_UINT
:
2224 case ISL_FORMAT_R32G32B32A32_UNORM
:
2225 case ISL_FORMAT_R32G32B32A32_SNORM
:
2226 return ISL_FORMAT_R32G32B32A32_UINT
;
2228 case ISL_FORMAT_R16G16B16A16_UNORM
:
2229 case ISL_FORMAT_R16G16B16A16_SNORM
:
2230 case ISL_FORMAT_R16G16B16A16_SINT
:
2231 case ISL_FORMAT_R16G16B16A16_UINT
:
2232 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2233 case ISL_FORMAT_R16G16B16X16_UNORM
:
2234 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2235 return ISL_FORMAT_R16G16B16A16_UINT
;
2237 case ISL_FORMAT_R32G32_FLOAT
:
2238 case ISL_FORMAT_R32G32_SINT
:
2239 case ISL_FORMAT_R32G32_UINT
:
2240 case ISL_FORMAT_R32G32_UNORM
:
2241 case ISL_FORMAT_R32G32_SNORM
:
2242 return ISL_FORMAT_R32G32_UINT
;
2244 case ISL_FORMAT_B8G8R8A8_UNORM
:
2245 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2246 case ISL_FORMAT_R8G8B8A8_UNORM
:
2247 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2248 case ISL_FORMAT_R8G8B8A8_SNORM
:
2249 case ISL_FORMAT_R8G8B8A8_SINT
:
2250 case ISL_FORMAT_R8G8B8A8_UINT
:
2251 case ISL_FORMAT_B8G8R8X8_UNORM
:
2252 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2253 case ISL_FORMAT_R8G8B8X8_UNORM
:
2254 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2255 return ISL_FORMAT_R8G8B8A8_UINT
;
2257 case ISL_FORMAT_R16G16_UNORM
:
2258 case ISL_FORMAT_R16G16_SNORM
:
2259 case ISL_FORMAT_R16G16_SINT
:
2260 case ISL_FORMAT_R16G16_UINT
:
2261 case ISL_FORMAT_R16G16_FLOAT
:
2262 return ISL_FORMAT_R16G16_UINT
;
2264 case ISL_FORMAT_R32_SINT
:
2265 case ISL_FORMAT_R32_UINT
:
2266 case ISL_FORMAT_R32_FLOAT
:
2267 case ISL_FORMAT_R32_UNORM
:
2268 case ISL_FORMAT_R32_SNORM
:
2269 return ISL_FORMAT_R32_UINT
;
2272 unreachable("Not a compressible format");
2276 /* Takes an isl_color_value and returns a color value that is the original
2277 * color value only bit-casted to a UINT format. This value, together with
2278 * the format from get_ccs_compatible_uint_format, will yield the same bit
2279 * value as the original color and format.
2281 static union isl_color_value
2282 bitcast_color_value_to_uint(union isl_color_value color
,
2283 const struct isl_format_layout
*fmtl
)
2285 /* All CCS formats have the same number of bits in each channel */
2286 const struct isl_channel_layout
*chan
= &fmtl
->channels
.r
;
2288 union isl_color_value bits
;
2289 switch (chan
->type
) {
2292 /* Hardware will ignore the high bits so there's no need to cast */
2297 for (unsigned i
= 0; i
< 4; i
++)
2298 bits
.u32
[i
] = _mesa_float_to_unorm(color
.f32
[i
], chan
->bits
);
2302 for (unsigned i
= 0; i
< 4; i
++)
2303 bits
.i32
[i
] = _mesa_float_to_snorm(color
.f32
[i
], chan
->bits
);
2307 switch (chan
->bits
) {
2309 for (unsigned i
= 0; i
< 4; i
++)
2310 bits
.u32
[i
] = _mesa_float_to_half(color
.f32
[i
]);
2318 unreachable("Invalid float format size");
2323 unreachable("Invalid channel type");
2326 switch (fmtl
->format
) {
2327 case ISL_FORMAT_B8G8R8A8_UNORM
:
2328 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2329 case ISL_FORMAT_B8G8R8X8_UNORM
:
2330 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
: {
2331 /* If it's a BGRA format, we need to swap blue and red */
2332 uint32_t tmp
= bits
.u32
[0];
2333 bits
.u32
[0] = bits
.u32
[2];
2339 break; /* Nothing to do */
2346 surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2347 struct brw_blorp_surface_info
*info
,
2348 uint32_t *x
, uint32_t *y
,
2349 uint32_t *width
, uint32_t *height
)
2351 const struct isl_format_layout
*fmtl
=
2352 isl_format_get_layout(info
->surf
.format
);
2354 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2356 /* This is a compressed surface. We need to convert it to a single
2357 * slice (because compressed layouts don't perfectly match uncompressed
2358 * ones with the same bpb) and divide x, y, width, and height by the
2361 blorp_surf_convert_to_single_slice(isl_dev
, info
);
2363 if (width
|| height
) {
2365 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2366 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2367 assert(*width
% fmtl
->bw
== 0 ||
2368 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2369 assert(*height
% fmtl
->bh
== 0 ||
2370 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2372 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2373 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2376 assert(*x
% fmtl
->bw
== 0);
2377 assert(*y
% fmtl
->bh
== 0);
2381 info
->surf
.logical_level0_px
.width
=
2382 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
2383 info
->surf
.logical_level0_px
.height
=
2384 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
2386 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
2387 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
2388 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2389 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2391 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2392 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2393 info
->tile_x_sa
/= fmtl
->bw
;
2394 info
->tile_y_sa
/= fmtl
->bh
;
2396 /* It's now an uncompressed surface so we need an uncompressed format */
2397 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2401 blorp_copy(struct blorp_batch
*batch
,
2402 const struct blorp_surf
*src_surf
,
2403 unsigned src_level
, unsigned src_layer
,
2404 const struct blorp_surf
*dst_surf
,
2405 unsigned dst_level
, unsigned dst_layer
,
2406 uint32_t src_x
, uint32_t src_y
,
2407 uint32_t dst_x
, uint32_t dst_y
,
2408 uint32_t src_width
, uint32_t src_height
)
2410 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2411 struct blorp_params params
;
2413 if (src_width
== 0 || src_height
== 0)
2416 blorp_params_init(¶ms
);
2417 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2418 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2419 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2420 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2422 struct brw_blorp_blit_prog_key wm_prog_key
= {
2423 .shader_type
= BLORP_SHADER_TYPE_BLIT
2426 const struct isl_format_layout
*src_fmtl
=
2427 isl_format_get_layout(params
.src
.surf
.format
);
2428 const struct isl_format_layout
*dst_fmtl
=
2429 isl_format_get_layout(params
.dst
.surf
.format
);
2431 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2432 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2433 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2434 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2435 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2436 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2438 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2439 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2440 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2441 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2442 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2443 params
.src
.view
.format
= params
.dst
.view
.format
;
2445 params
.src
.view
.format
=
2446 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2448 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2449 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2450 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2451 params
.dst
.view
.format
= params
.src
.view
.format
;
2453 params
.dst
.view
.format
=
2454 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2457 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2458 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2461 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2462 /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
2463 * enabled even though CCS_E doesn't technically do sRGB on SKL because
2464 * we stomp everything to UINT anyway. The one thing we have to be
2465 * careful of is clear colors. Because fast clear colors for sRGB on
2466 * gen9 are encoded as the float values between format conversion and
2467 * sRGB curve application, a given clear color float will convert to the
2468 * same bits regardless of whether the format is UNORM or sRGB.
2469 * Therefore, we can handle sRGB without any special cases.
2471 UNUSED
enum isl_format linear_src_format
=
2472 isl_format_srgb_to_linear(src_surf
->surf
->format
);
2473 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2475 params
.src
.view
.format
));
2476 params
.src
.clear_color
=
2477 bitcast_color_value_to_uint(params
.src
.clear_color
, src_fmtl
);
2480 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2481 /* See above where we handle linear_src_format */
2482 UNUSED
enum isl_format linear_dst_format
=
2483 isl_format_srgb_to_linear(dst_surf
->surf
->format
);
2484 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2486 params
.dst
.view
.format
));
2487 params
.dst
.clear_color
=
2488 bitcast_color_value_to_uint(params
.dst
.clear_color
, dst_fmtl
);
2491 wm_prog_key
.src_bpc
=
2492 isl_format_get_layout(params
.src
.view
.format
)->channels
.r
.bits
;
2493 wm_prog_key
.dst_bpc
=
2494 isl_format_get_layout(params
.dst
.view
.format
)->channels
.r
.bits
;
2496 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2497 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2498 &src_x
, &src_y
, &src_width
, &src_height
);
2499 wm_prog_key
.need_src_offset
= true;
2502 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2503 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2504 &dst_x
, &dst_y
, NULL
, NULL
);
2505 wm_prog_key
.need_dst_offset
= true;
2508 /* Once both surfaces are stompped to uncompressed as needed, the
2509 * destination size is the same as the source size.
2511 uint32_t dst_width
= src_width
;
2512 uint32_t dst_height
= src_height
;
2514 struct blt_coords coords
= {
2517 .src1
= src_x
+ src_width
,
2519 .dst1
= dst_x
+ dst_width
,
2524 .src1
= src_y
+ src_height
,
2526 .dst1
= dst_y
+ dst_height
,
2531 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);