2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "blorp_nir_builder.h"
25 #include "compiler/nir/nir_format_convert.h"
27 #include "blorp_priv.h"
29 #include "util/format_rgb9e5.h"
30 /* header-only include needed for _mesa_unorm_to_float and friends. */
31 #include "mesa/main/format_utils.h"
33 #define FILE_DEBUG_FLAG DEBUG_BLORP
35 static const bool split_blorp_blit_debug
= false;
38 * Enum to specify the order of arguments in a sampler message
40 enum sampler_message_arg
42 SAMPLER_MESSAGE_ARG_U_FLOAT
,
43 SAMPLER_MESSAGE_ARG_V_FLOAT
,
44 SAMPLER_MESSAGE_ARG_U_INT
,
45 SAMPLER_MESSAGE_ARG_V_INT
,
46 SAMPLER_MESSAGE_ARG_R_INT
,
47 SAMPLER_MESSAGE_ARG_SI_INT
,
48 SAMPLER_MESSAGE_ARG_MCS_INT
,
49 SAMPLER_MESSAGE_ARG_ZERO_INT
,
52 struct brw_blorp_blit_vars
{
53 /* Input values from brw_blorp_wm_inputs */
54 nir_variable
*v_discard_rect
;
55 nir_variable
*v_rect_grid
;
56 nir_variable
*v_coord_transform
;
57 nir_variable
*v_src_z
;
58 nir_variable
*v_src_offset
;
59 nir_variable
*v_dst_offset
;
60 nir_variable
*v_src_inv_size
;
63 nir_variable
*frag_coord
;
66 nir_variable
*color_out
;
70 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
71 const struct brw_blorp_blit_prog_key
*key
)
73 #define LOAD_INPUT(name, type)\
74 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
76 LOAD_INPUT(discard_rect
, glsl_vec4_type())
77 LOAD_INPUT(rect_grid
, glsl_vec4_type())
78 LOAD_INPUT(coord_transform
, glsl_vec4_type())
79 LOAD_INPUT(src_z
, glsl_uint_type())
80 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
81 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
82 LOAD_INPUT(src_inv_size
, glsl_vector_type(GLSL_TYPE_FLOAT
, 2))
86 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
87 glsl_vec4_type(), "gl_FragCoord");
88 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
89 v
->frag_coord
->data
.origin_upper_left
= true;
91 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
92 glsl_vec4_type(), "gl_FragColor");
93 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
97 blorp_blit_get_frag_coords(nir_builder
*b
,
98 const struct brw_blorp_blit_prog_key
*key
,
99 struct brw_blorp_blit_vars
*v
)
101 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_var(b
, v
->frag_coord
));
103 /* Account for destination surface intratile offset
105 * Transformation parameters giving translation from destination to source
106 * coordinates don't take into account possible intra-tile destination
107 * offset. Therefore it has to be first subtracted from the incoming
108 * coordinates. Vertices are set up based on coordinates containing the
111 if (key
->need_dst_offset
)
112 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
114 if (key
->persample_msaa_dispatch
) {
115 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
116 nir_load_sample_id(b
));
118 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
123 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
127 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
128 struct brw_blorp_blit_vars
*v
)
130 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
132 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
133 nir_channel(b
, coord_transform
, 3));
134 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
135 nir_channel(b
, coord_transform
, 2));
137 return nir_fadd(b
, nir_fmul(b
, src_pos
, mul
), offset
);
141 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
142 struct brw_blorp_blit_vars
*v
)
144 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
145 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
146 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
147 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
148 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
149 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
151 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
152 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
153 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
154 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
156 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
158 nir_intrinsic_instr
*discard
=
159 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
160 discard
->src
[0] = nir_src_for_ssa(oob
);
161 nir_builder_instr_insert(b
, &discard
->instr
);
164 static nir_tex_instr
*
165 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
166 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
167 nir_alu_type dst_type
)
169 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
173 tex
->dest_type
= dst_type
;
174 tex
->is_array
= false;
175 tex
->is_shadow
= false;
177 /* Blorp only has one texture and it's bound at unit 0 */
178 tex
->texture_index
= 0;
179 tex
->sampler_index
= 0;
181 /* To properly handle 3-D and 2-D array textures, we pull the Z component
182 * from an input. TODO: This is a bit magic; we should probably make this
183 * more explicit in the future.
185 assert(pos
->num_components
>= 2);
186 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
187 nir_load_var(b
, v
->v_src_z
));
189 tex
->src
[0].src_type
= nir_tex_src_coord
;
190 tex
->src
[0].src
= nir_src_for_ssa(pos
);
191 tex
->coord_components
= 3;
193 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
199 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
200 const struct brw_blorp_blit_prog_key
*key
, nir_ssa_def
*pos
)
202 if (key
->need_src_offset
)
203 pos
= nir_fadd(b
, pos
, nir_i2f32(b
, nir_load_var(b
, v
->v_src_offset
)));
205 /* If the sampler requires normalized coordinates, we need to compensate. */
206 if (key
->src_coords_normalized
)
207 pos
= nir_fmul(b
, pos
, nir_load_var(b
, v
->v_src_inv_size
));
210 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2,
211 key
->texture_data_type
);
213 assert(pos
->num_components
== 2);
214 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
215 tex
->src
[1].src_type
= nir_tex_src_lod
;
216 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
218 nir_builder_instr_insert(b
, &tex
->instr
);
220 return &tex
->dest
.ssa
;
224 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
225 nir_ssa_def
*pos
, nir_alu_type dst_type
)
228 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
230 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
231 tex
->src
[1].src_type
= nir_tex_src_lod
;
232 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
234 nir_builder_instr_insert(b
, &tex
->instr
);
236 return &tex
->dest
.ssa
;
240 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
241 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
244 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
245 mcs
!= NULL
? 3 : 2, dst_type
);
247 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
249 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
250 if (pos
->num_components
== 2) {
251 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
253 assert(pos
->num_components
== 3);
254 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
258 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
259 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
262 nir_builder_instr_insert(b
, &tex
->instr
);
264 return &tex
->dest
.ssa
;
268 blorp_blit_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
272 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
273 pos
, 1, nir_type_int
);
275 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
277 nir_builder_instr_insert(b
, &tex
->instr
);
279 return &tex
->dest
.ssa
;
283 * Emit code to compensate for the difference between Y and W tiling.
285 * This code modifies the X and Y coordinates according to the formula:
287 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
289 * (See brw_blorp_build_nir_shader).
291 static inline nir_ssa_def
*
292 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
294 assert(pos
->num_components
== 2);
295 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
296 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
298 /* Given X and Y coordinates that describe an address using Y tiling,
299 * translate to the X and Y coordinates that describe the same address
302 * If we break down the low order bits of X and Y, using a
303 * single letter to represent each low-order bit:
305 * X = A << 7 | 0bBCDEFGH
306 * Y = J << 5 | 0bKLMNP (1)
308 * Then we can apply the Y tiling formula to see the memory offset being
311 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
313 * If we apply the W detiling formula to this memory location, that the
314 * corresponding X' and Y' coordinates are:
316 * X' = A << 6 | 0bBCDPFH (3)
317 * Y' = J << 6 | 0bKLMNEG
319 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
320 * we need to make the following computation:
322 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
323 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
325 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
326 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
327 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
328 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
330 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
331 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
332 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
333 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
335 return nir_vec2(b
, x_W
, y_W
);
339 * Emit code to compensate for the difference between Y and W tiling.
341 * This code modifies the X and Y coordinates according to the formula:
343 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
345 * (See brw_blorp_build_nir_shader).
347 static inline nir_ssa_def
*
348 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
350 assert(pos
->num_components
== 2);
351 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
352 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
354 /* Applying the same logic as above, but in reverse, we obtain the
357 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
358 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
360 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
361 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
362 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
363 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
364 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
366 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
367 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
368 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
370 return nir_vec2(b
, x_Y
, y_Y
);
374 * Emit code to compensate for the difference between MSAA and non-MSAA
377 * This code modifies the X and Y coordinates according to the formula:
379 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
381 * (See brw_blorp_blit_program).
383 static inline nir_ssa_def
*
384 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
385 unsigned num_samples
, enum isl_msaa_layout layout
)
387 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
390 case ISL_MSAA_LAYOUT_NONE
:
391 assert(pos
->num_components
== 2);
393 case ISL_MSAA_LAYOUT_ARRAY
:
394 /* No translation needed */
396 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
397 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
398 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
399 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
400 nir_channel(b
, pos
, 2);
402 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
403 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
404 switch (num_samples
) {
407 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
408 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
411 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
412 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
413 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
415 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
416 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
417 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
418 if (num_samples
== 2) {
421 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
422 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
423 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
428 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
429 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
431 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
433 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
434 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
435 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
436 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
437 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
438 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
439 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
443 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
444 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
446 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
449 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
450 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
451 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
452 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
453 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
454 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
455 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
456 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
460 unreachable("Invalid number of samples for IMS layout");
463 return nir_vec2(b
, x_out
, y_out
);
467 unreachable("Invalid MSAA layout");
472 * Emit code to compensate for the difference between MSAA and non-MSAA
475 * This code modifies the X and Y coordinates according to the formula:
477 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
479 * (See brw_blorp_blit_program).
481 static inline nir_ssa_def
*
482 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
483 unsigned num_samples
, enum isl_msaa_layout layout
)
485 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
488 case ISL_MSAA_LAYOUT_NONE
:
489 /* No translation necessary, and S should already be zero. */
490 assert(pos
->num_components
== 2);
492 case ISL_MSAA_LAYOUT_ARRAY
:
493 /* No translation necessary. */
495 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
496 assert(pos
->num_components
== 2);
498 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
499 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
501 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
502 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
503 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
504 switch (num_samples
) {
507 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
508 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
509 * S = (X & 0b10) >> 1
511 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
512 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
513 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
514 * S = (Y & 0b10) | (X & 0b10) >> 1
516 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
517 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
518 if (num_samples
== 2) {
520 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
522 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
523 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
524 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
525 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
530 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
531 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
532 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
533 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
535 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
536 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
537 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
538 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
539 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
540 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
541 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
545 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
546 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
547 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
548 * S = (Y & 0b100) << 1 | (X & 0b100) |
549 * (Y & 0b10) | (X & 0b10) >> 1
551 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
552 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
553 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
554 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
555 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
556 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
557 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
558 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
562 unreachable("Invalid number of samples for IMS layout");
565 return nir_vec3(b
, x_out
, y_out
, s_out
);
569 unreachable("Invalid MSAA layout");
574 * Count the number of trailing 1 bits in the given value. For example:
576 * count_trailing_one_bits(0) == 0
577 * count_trailing_one_bits(7) == 3
578 * count_trailing_one_bits(11) == 2
580 static inline int count_trailing_one_bits(unsigned value
)
582 #ifdef HAVE___BUILTIN_CTZ
583 return __builtin_ctz(~value
);
585 return _mesa_bitcount(value
& ~(value
+ 1));
590 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
591 nir_ssa_def
*pos
, unsigned tex_samples
,
592 enum isl_aux_usage tex_aux_usage
,
593 nir_alu_type dst_type
)
595 /* If non-null, this is the outer-most if statement */
596 nir_if
*outer_if
= NULL
;
598 nir_variable
*color
=
599 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
601 nir_ssa_def
*mcs
= NULL
;
602 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
603 mcs
= blorp_blit_txf_ms_mcs(b
, v
, pos
);
605 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
607 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
609 * This ensures that when all samples have the same value, no numerical
610 * precision is lost, since each addition operation always adds two equal
611 * values, and summing two equal floating point values does not lose
614 * We perform this computation by treating the texture_data array as a
615 * stack and performing the following operations:
617 * - push sample 0 onto stack
618 * - push sample 1 onto stack
619 * - add top two stack entries
620 * - push sample 2 onto stack
621 * - push sample 3 onto stack
622 * - add top two stack entries
623 * - add top two stack entries
624 * - divide top stack entry by 4
626 * Note that after pushing sample i onto the stack, the number of add
627 * operations we do is equal to the number of trailing 1 bits in i. This
628 * works provided the total number of samples is a power of two, which it
629 * always is for i965.
631 * For integer formats, we replace the add operations with average
632 * operations and skip the final division.
634 nir_ssa_def
*texture_data
[5];
635 unsigned stack_depth
= 0;
636 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
637 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
639 /* Push sample i onto the stack */
640 assert(stack_depth
< ARRAY_SIZE(texture_data
));
642 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
643 nir_channel(b
, pos
, 1),
645 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
647 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
648 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
649 * suggests an optimization:
651 * "A simple optimization with probable large return in
652 * performance is to compare the MCS value to zero (indicating
653 * all samples are on sample slice 0), and sample only from
654 * sample slice 0 using ld2dss if MCS is zero."
656 * Note that in the case where the MCS value is zero, sampling from
657 * sample slice 0 using ld2dss and sampling from sample 0 using
658 * ld2dms are equivalent (since all samples are on sample slice 0).
659 * Since we have already sampled from sample 0, all we need to do is
660 * skip the remaining fetches and averaging if MCS is zero.
662 * It's also trivial to detect when the MCS has the magic clear color
663 * value. In this case, the txf we did on sample 0 will return the
664 * clear color and we can skip the remaining fetches just like we do
667 nir_ssa_def
*mcs_zero
=
668 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
669 if (tex_samples
== 16) {
670 mcs_zero
= nir_iand(b
, mcs_zero
,
671 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
673 nir_ssa_def
*mcs_clear
=
674 blorp_nir_mcs_is_clear_color(b
, mcs
, tex_samples
);
676 nir_if
*if_stmt
= nir_if_create(b
->shader
);
677 if_stmt
->condition
= nir_src_for_ssa(nir_ior(b
, mcs_zero
, mcs_clear
));
678 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
680 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
681 nir_store_var(b
, color
, texture_data
[0], 0xf);
683 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
687 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
688 assert(stack_depth
>= 2);
691 assert(dst_type
== nir_type_float
);
692 texture_data
[stack_depth
- 1] =
693 nir_fadd(b
, texture_data
[stack_depth
- 1],
694 texture_data
[stack_depth
]);
698 /* We should have just 1 sample on the stack now. */
699 assert(stack_depth
== 1);
701 texture_data
[0] = nir_fmul(b
, texture_data
[0],
702 nir_imm_float(b
, 1.0 / tex_samples
));
704 nir_store_var(b
, color
, texture_data
[0], 0xf);
707 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
709 return nir_load_var(b
, color
);
712 static inline nir_ssa_def
*
713 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
717 memset(&v
, 0, sizeof(v
));
721 return nir_build_imm(build
, 4, 32, v
);
725 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
726 unsigned tex_samples
,
727 const struct brw_blorp_blit_prog_key
*key
,
728 struct brw_blorp_blit_vars
*v
)
730 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
731 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
732 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
734 /* Translate coordinates to lay out the samples in a rectangular grid
735 * roughly corresponding to sample locations.
737 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
738 /* Adjust coordinates so that integers represent pixel centers rather
741 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
742 /* Clamp the X, Y texture coordinates to properly handle the sampling of
743 * texels on texture edges.
745 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
746 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
747 nir_channel(b
, rect_grid
, 1)));
749 /* Store the fractional parts to be used as bilinear interpolation
752 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
753 /* Round the float coordinates down to nearest integer */
754 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
756 nir_ssa_def
*tex_data
[4];
757 for (unsigned i
= 0; i
< 4; ++i
) {
758 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
759 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
760 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
762 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
763 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
765 /* The MCS value we fetch has to match up with the pixel that we're
766 * sampling from. Since we sample from different pixels in each
767 * iteration of this "for" loop, the call to mcs_fetch() should be
768 * here inside the loop after computing the pixel coordinates.
770 nir_ssa_def
*mcs
= NULL
;
771 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
772 mcs
= blorp_blit_txf_ms_mcs(b
, v
, sample_coords_int
);
774 /* Compute sample index and map the sample index to a sample number.
775 * Sample index layout shows the numbering of slots in a rectangular
776 * grid of samples with in a pixel. Sample number layout shows the
777 * rectangular grid of samples roughly corresponding to the real sample
778 * locations with in a pixel.
779 * In case of 4x MSAA, layout of sample indices matches the layout of
787 * In case of 8x MSAA the two layouts don't match.
788 * sample index layout : --------- sample number layout : ---------
789 * | 0 | 1 | | 3 | 7 |
790 * --------- ---------
791 * | 2 | 3 | | 5 | 0 |
792 * --------- ---------
793 * | 4 | 5 | | 1 | 2 |
794 * --------- ---------
795 * | 6 | 7 | | 4 | 6 |
796 * --------- ---------
798 * Fortunately, this can be done fairly easily as:
799 * S' = (0x17306425 >> (S * 4)) & 0xf
801 * In the case of 16x MSAA the two layouts don't match.
802 * Sample index layout: Sample number layout:
803 * --------------------- ---------------------
804 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
805 * --------------------- ---------------------
806 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
807 * --------------------- ---------------------
808 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
809 * --------------------- ---------------------
810 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
811 * --------------------- ---------------------
813 * This is equivalent to
814 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
816 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
817 nir_ssa_def
*sample
=
818 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
819 key
->x_scale
* key
->y_scale
));
820 sample
= nir_f2i32(b
, sample
);
822 if (tex_samples
== 8) {
823 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
824 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
825 nir_imm_int(b
, 0xf));
826 } else if (tex_samples
== 16) {
827 nir_ssa_def
*sample_low
=
828 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
829 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
830 nir_imm_int(b
, 0xf));
831 nir_ssa_def
*sample_high
=
832 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
833 nir_ishl(b
, nir_iadd(b
, sample
,
836 nir_imm_int(b
, 0xf));
838 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
839 sample_low
, sample_high
);
841 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
842 nir_channel(b
, sample_coords_int
, 1),
844 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
847 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
848 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
849 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
850 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
854 /** Perform a color bit-cast operation
856 * For copy operations involving CCS, we may need to use different formats for
857 * the source and destination surfaces. The two formats must both be UINT
858 * formats and must have the same size but may have different bit layouts.
859 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
860 * to R16G16_UINT. This function generates code to shuffle bits around to get
861 * us from one to the other.
864 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
865 const struct brw_blorp_blit_prog_key
*key
)
867 assert(key
->texture_data_type
== nir_type_uint
);
869 if (key
->src_format
== key
->dst_format
)
872 const struct isl_format_layout
*src_fmtl
=
873 isl_format_get_layout(key
->src_format
);
874 const struct isl_format_layout
*dst_fmtl
=
875 isl_format_get_layout(key
->dst_format
);
877 /* They must be uint formats with the same bit size */
878 assert(src_fmtl
->bpb
== dst_fmtl
->bpb
);
879 assert(src_fmtl
->channels
.r
.type
== ISL_UINT
);
880 assert(dst_fmtl
->channels
.r
.type
== ISL_UINT
);
882 /* They must be in regular color formats (no luminance or alpha) */
883 assert(src_fmtl
->channels
.r
.bits
> 0);
884 assert(dst_fmtl
->channels
.r
.bits
> 0);
886 /* They must be in RGBA order (possibly with channels missing) */
887 assert(src_fmtl
->channels
.r
.start_bit
== 0);
888 assert(dst_fmtl
->channels
.r
.start_bit
== 0);
890 if (src_fmtl
->bpb
<= 32) {
891 const unsigned src_channels
=
892 isl_format_get_num_channels(key
->src_format
);
893 const unsigned src_bits
[4] = {
894 src_fmtl
->channels
.r
.bits
,
895 src_fmtl
->channels
.g
.bits
,
896 src_fmtl
->channels
.b
.bits
,
897 src_fmtl
->channels
.a
.bits
,
899 const unsigned dst_channels
=
900 isl_format_get_num_channels(key
->dst_format
);
901 const unsigned dst_bits
[4] = {
902 dst_fmtl
->channels
.r
.bits
,
903 dst_fmtl
->channels
.g
.bits
,
904 dst_fmtl
->channels
.b
.bits
,
905 dst_fmtl
->channels
.a
.bits
,
907 nir_ssa_def
*packed
=
908 nir_format_pack_uint_unmasked(b
, color
, src_bits
, src_channels
);
909 color
= nir_format_unpack_uint(b
, packed
, dst_bits
, dst_channels
);
911 const unsigned src_bpc
= src_fmtl
->channels
.r
.bits
;
912 const unsigned dst_bpc
= dst_fmtl
->channels
.r
.bits
;
914 assert(src_fmtl
->channels
.g
.bits
== 0 ||
915 src_fmtl
->channels
.g
.bits
== src_fmtl
->channels
.r
.bits
);
916 assert(src_fmtl
->channels
.b
.bits
== 0 ||
917 src_fmtl
->channels
.b
.bits
== src_fmtl
->channels
.r
.bits
);
918 assert(src_fmtl
->channels
.a
.bits
== 0 ||
919 src_fmtl
->channels
.a
.bits
== src_fmtl
->channels
.r
.bits
);
920 assert(dst_fmtl
->channels
.g
.bits
== 0 ||
921 dst_fmtl
->channels
.g
.bits
== dst_fmtl
->channels
.r
.bits
);
922 assert(dst_fmtl
->channels
.b
.bits
== 0 ||
923 dst_fmtl
->channels
.b
.bits
== dst_fmtl
->channels
.r
.bits
);
924 assert(dst_fmtl
->channels
.a
.bits
== 0 ||
925 dst_fmtl
->channels
.a
.bits
== dst_fmtl
->channels
.r
.bits
);
927 /* Restrict to only the channels we actually have */
928 const unsigned src_channels
=
929 isl_format_get_num_channels(key
->src_format
);
930 color
= nir_channels(b
, color
, (1 << src_channels
) - 1);
932 color
= nir_format_bitcast_uint_vec_unmasked(b
, color
, src_bpc
, dst_bpc
);
935 /* Blorp likes to assume that colors are vec4s */
936 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
937 nir_ssa_def
*chans
[4] = { u
, u
, u
, u
};
938 for (unsigned i
= 0; i
< color
->num_components
; i
++)
939 chans
[i
] = nir_channel(b
, color
, i
);
940 return nir_vec4(b
, chans
[0], chans
[1], chans
[2], chans
[3]);
944 select_color_channel(struct nir_builder
*b
, nir_ssa_def
*color
,
945 nir_alu_type data_type
,
946 enum isl_channel_select chan
)
948 if (chan
== ISL_CHANNEL_SELECT_ZERO
) {
949 return nir_imm_int(b
, 0);
950 } else if (chan
== ISL_CHANNEL_SELECT_ONE
) {
954 return nir_imm_int(b
, 1);
956 return nir_imm_float(b
, 1);
958 unreachable("Invalid data type");
961 assert((unsigned)(chan
- ISL_CHANNEL_SELECT_RED
) < 4);
962 return nir_channel(b
, color
, chan
- ISL_CHANNEL_SELECT_RED
);
967 swizzle_color(struct nir_builder
*b
, nir_ssa_def
*color
,
968 struct isl_swizzle swizzle
, nir_alu_type data_type
)
971 select_color_channel(b
, color
, data_type
, swizzle
.r
),
972 select_color_channel(b
, color
, data_type
, swizzle
.g
),
973 select_color_channel(b
, color
, data_type
, swizzle
.b
),
974 select_color_channel(b
, color
, data_type
, swizzle
.a
));
978 convert_color(struct nir_builder
*b
, nir_ssa_def
*color
,
979 const struct brw_blorp_blit_prog_key
*key
)
981 /* All of our color conversions end up generating a single-channel color
982 * value that we need to write out.
986 if (key
->dst_format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
987 /* The destination image is bound as R32_UNORM but the data needs to be
988 * in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and the
989 * top 8 need to be zero. We can accomplish this by simply multiplying
990 * by a factor to scale things down.
992 float factor
= (float)((1 << 24) - 1) / (float)UINT32_MAX
;
993 value
= nir_fmul(b
, nir_fsat(b
, nir_channel(b
, color
, 0)),
994 nir_imm_float(b
, factor
));
995 } else if (key
->dst_format
== ISL_FORMAT_L8_UNORM_SRGB
) {
996 value
= nir_format_linear_to_srgb(b
, nir_channel(b
, color
, 0));
997 } else if (key
->dst_format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
) {
998 value
= nir_format_linear_to_srgb(b
, color
);
999 } else if (key
->dst_format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
1000 value
= nir_format_pack_r9g9b9e5(b
, color
);
1002 unreachable("Unsupported format conversion");
1005 nir_ssa_def
*out_comps
[4];
1006 for (unsigned i
= 0; i
< 4; i
++) {
1007 if (i
< value
->num_components
)
1008 out_comps
[i
] = nir_channel(b
, value
, i
);
1010 out_comps
[i
] = nir_ssa_undef(b
, 1, 32);
1012 return nir_vec(b
, out_comps
, 4);
1016 * Generator for WM programs used in BLORP blits.
1018 * The bulk of the work done by the WM program is to wrap and unwrap the
1019 * coordinate transformations used by the hardware to store surfaces in
1020 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
1021 * sample index for a multisampled surface) to a memory offset by the
1022 * following formulas:
1024 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
1025 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
1027 * For a single-sampled surface, or for a multisampled surface using
1028 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
1031 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1032 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1033 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1034 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1036 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1037 * embeds the sample number into bit 1 of the X and Y coordinates:
1039 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1040 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1041 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
1042 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1043 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1044 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1045 * S = (Y & 0b10) | (X & 0b10) >> 1
1047 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1048 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
1051 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1052 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
1053 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1054 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1055 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1056 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1057 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1059 * For X tiling, tile() combines together the low-order bits of the X and Y
1060 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
1061 * bytes wide and 8 rows high:
1063 * tile(x_tiled, X, Y, S) = A
1064 * where A = tile_num << 12 | offset
1065 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
1066 * offset = (Y' & 0b111) << 9
1067 * | (X & 0b111111111)
1069 * Y' = Y + S * qpitch
1070 * detile(x_tiled, A) = (X, Y, S)
1071 * where X = X' / cpp
1074 * Y' = (tile_num / tile_pitch) << 3
1075 * | (A & 0b111000000000) >> 9
1076 * X' = (tile_num % tile_pitch) << 9
1077 * | (A & 0b111111111)
1079 * (In all tiling formulas, cpp is the number of bytes occupied by a single
1080 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
1081 * to fill the width of the surface, and qpitch is the spacing (in rows)
1082 * between array slices).
1084 * For Y tiling, tile() combines together the low-order bits of the X and Y
1085 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
1086 * bytes wide and 32 rows high:
1088 * tile(y_tiled, X, Y, S) = A
1089 * where A = tile_num << 12 | offset
1090 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
1091 * offset = (X' & 0b1110000) << 5
1092 * | (Y' & 0b11111) << 4
1095 * Y' = Y + S * qpitch
1096 * detile(y_tiled, A) = (X, Y, S)
1097 * where X = X' / cpp
1100 * Y' = (tile_num / tile_pitch) << 5
1101 * | (A & 0b111110000) >> 4
1102 * X' = (tile_num % tile_pitch) << 7
1103 * | (A & 0b111000000000) >> 5
1106 * For W tiling, tile() combines together the low-order bits of the X and Y
1107 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1108 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1109 * buffers, which always have cpp = 1 and S=0):
1111 * tile(w_tiled, X, Y, S) = A
1112 * where A = tile_num << 12 | offset
1113 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1114 * offset = (X' & 0b111000) << 6
1115 * | (Y' & 0b111100) << 3
1116 * | (X' & 0b100) << 2
1117 * | (Y' & 0b10) << 2
1118 * | (X' & 0b10) << 1
1122 * Y' = Y + S * qpitch
1123 * detile(w_tiled, A) = (X, Y, S)
1124 * where X = X' / cpp = X'
1125 * Y = Y' % qpitch = Y'
1126 * S = Y / qpitch = 0
1127 * Y' = (tile_num / tile_pitch) << 6
1128 * | (A & 0b111100000) >> 3
1129 * | (A & 0b1000) >> 2
1131 * X' = (tile_num % tile_pitch) << 6
1132 * | (A & 0b111000000000) >> 6
1133 * | (A & 0b10000) >> 2
1134 * | (A & 0b100) >> 1
1137 * Finally, for a non-tiled surface, tile() simply combines together the X and
1138 * Y coordinates in the natural way:
1140 * tile(untiled, X, Y, S) = A
1141 * where A = Y * pitch + X'
1143 * Y' = Y + S * qpitch
1144 * detile(untiled, A) = (X, Y, S)
1145 * where X = X' / cpp
1151 * (In these formulas, pitch is the number of bytes occupied by a single row
1155 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1156 const struct brw_blorp_blit_prog_key
*key
)
1158 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1159 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1162 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1163 /* If the destination image is W tiled and multisampled, then the thread
1164 * must be dispatched once per sample, not once per pixel. This is
1165 * necessary because after conversion between W and Y tiling, there's no
1166 * guarantee that all samples corresponding to a single pixel will still
1169 assert(key
->persample_msaa_dispatch
);
1172 if (key
->persample_msaa_dispatch
) {
1173 /* It only makes sense to do persample dispatch if the render target is
1174 * configured as multisampled.
1176 assert(key
->rt_samples
> 0);
1179 /* Make sure layout is consistent with sample count */
1180 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1181 (key
->tex_samples
<= 1));
1182 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1183 (key
->rt_samples
<= 1));
1184 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1185 (key
->src_samples
<= 1));
1186 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1187 (key
->dst_samples
<= 1));
1190 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1192 struct brw_blorp_blit_vars v
;
1193 brw_blorp_blit_vars_init(&b
, &v
, key
);
1195 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1197 /* Render target and texture hardware don't support W tiling until Gen8. */
1198 const bool rt_tiled_w
= false;
1199 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1201 /* The address that data will be written to is determined by the
1202 * coordinates supplied to the WM thread and the tiling and sample count of
1203 * the render target, according to the formula:
1205 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1207 * If the actual tiling and sample count of the destination surface are not
1208 * the same as the configuration of the render target, then these
1209 * coordinates are wrong and we have to adjust them to compensate for the
1212 if (rt_tiled_w
!= key
->dst_tiled_w
||
1213 key
->rt_samples
!= key
->dst_samples
||
1214 key
->rt_layout
!= key
->dst_layout
) {
1215 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1217 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1218 if (rt_tiled_w
!= key
->dst_tiled_w
)
1219 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1220 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1221 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1225 nir_ssa_def
*comp
= NULL
;
1227 /* The destination image is bound as a red texture three times as wide
1228 * as the actual image. Our shader is effectively running one color
1229 * component at a time. We need to save off the component and adjust
1230 * the destination position.
1232 assert(dst_pos
->num_components
== 2);
1233 nir_ssa_def
*dst_x
= nir_channel(&b
, dst_pos
, 0);
1234 comp
= nir_umod(&b
, dst_x
, nir_imm_int(&b
, 3));
1235 dst_pos
= nir_vec2(&b
, nir_idiv(&b
, dst_x
, nir_imm_int(&b
, 3)),
1236 nir_channel(&b
, dst_pos
, 1));
1239 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1241 * That is: X, Y and S now contain the true coordinates and sample index of
1242 * the data that the WM thread should output.
1244 * If we need to kill pixels that are outside the destination rectangle,
1245 * now is the time to do it.
1248 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1250 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1251 if (dst_pos
->num_components
== 3) {
1252 /* The sample coordinate is an integer that we want left alone but
1253 * blorp_blit_apply_transform() blindly applies the transform to all
1254 * three coordinates. Grab the original sample index.
1256 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1257 nir_channel(&b
, src_pos
, 1),
1258 nir_channel(&b
, dst_pos
, 2));
1261 /* If the source image is not multisampled, then we want to fetch sample
1262 * number 0, because that's the only sample there is.
1264 if (key
->src_samples
== 1)
1265 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1267 /* X, Y, and S are now the coordinates of the pixel in the source image
1268 * that we want to texture from. Exception: if we are blending, then S is
1269 * irrelevant, because we are going to fetch all samples.
1271 switch (key
->filter
) {
1272 case BLORP_FILTER_NONE
:
1273 case BLORP_FILTER_NEAREST
:
1274 case BLORP_FILTER_SAMPLE_0
:
1275 /* We're going to use texelFetch, so we need integers */
1276 if (src_pos
->num_components
== 2) {
1277 src_pos
= nir_f2i32(&b
, src_pos
);
1279 assert(src_pos
->num_components
== 3);
1280 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1281 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1282 nir_channel(&b
, src_pos
, 2));
1285 /* We aren't blending, which means we just want to fetch a single
1286 * sample from the source surface. The address that we want to fetch
1287 * from is related to the X, Y and S values according to the formula:
1289 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1291 * If the actual tiling and sample count of the source surface are
1292 * not the same as the configuration of the texture, then we need to
1293 * adjust the coordinates to compensate for the difference.
1295 if (tex_tiled_w
!= key
->src_tiled_w
||
1296 key
->tex_samples
!= key
->src_samples
||
1297 key
->tex_layout
!= key
->src_layout
) {
1298 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1300 /* Now (X, Y, S) = detile(src_tiling, offset) */
1301 if (tex_tiled_w
!= key
->src_tiled_w
)
1302 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1303 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1304 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1308 if (key
->need_src_offset
)
1309 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1311 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1313 * In other words: X, Y, and S now contain values which, when passed to
1314 * the texturing unit, will cause data to be read from the correct
1315 * memory location. So we can fetch the texel now.
1317 if (key
->src_samples
== 1) {
1318 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1320 nir_ssa_def
*mcs
= NULL
;
1321 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1322 mcs
= blorp_blit_txf_ms_mcs(&b
, &v
, src_pos
);
1324 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1328 case BLORP_FILTER_BILINEAR
:
1329 assert(!key
->src_tiled_w
);
1330 assert(key
->tex_samples
== key
->src_samples
);
1331 assert(key
->tex_layout
== key
->src_layout
);
1333 if (key
->src_samples
== 1) {
1334 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1336 assert(!key
->use_kill
);
1337 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
,
1342 case BLORP_FILTER_AVERAGE
:
1343 assert(!key
->src_tiled_w
);
1344 assert(key
->tex_samples
== key
->src_samples
);
1345 assert(key
->tex_layout
== key
->src_layout
);
1347 /* Resolves (effecively) use texelFetch, so we need integers and we
1348 * don't care about the sample index if we got one.
1350 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1352 if (devinfo
->gen
== 6) {
1353 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1354 * blending we need with a single linear-interpolated texture lookup
1355 * at the center of the sample. The texture coordinates to be odd
1356 * integers so that they correspond to the center of a 2x2 block
1357 * representing the four samples that maxe up a pixel. So we need
1358 * to multiply our X and Y coordinates each by 2 and then add 1.
1360 assert(key
->src_coords_normalized
);
1361 src_pos
= nir_fadd(&b
,
1362 nir_i2f32(&b
, src_pos
),
1363 nir_imm_float(&b
, 0.5f
));
1364 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1366 /* Gen7+ hardware doesn't automaticaly blend. */
1367 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1369 key
->texture_data_type
);
1374 unreachable("Invalid blorp filter");
1377 if (!isl_swizzle_is_identity(key
->src_swizzle
)) {
1378 color
= swizzle_color(&b
, color
, key
->src_swizzle
,
1379 key
->texture_data_type
);
1382 if (!isl_swizzle_is_identity(key
->dst_swizzle
)) {
1383 color
= swizzle_color(&b
, color
, isl_swizzle_invert(key
->dst_swizzle
),
1387 if (key
->format_bit_cast
) {
1388 assert(isl_swizzle_is_identity(key
->src_swizzle
));
1389 assert(isl_swizzle_is_identity(key
->dst_swizzle
));
1390 color
= bit_cast_color(&b
, color
, key
);
1391 } else if (key
->dst_format
) {
1392 color
= convert_color(&b
, color
, key
);
1396 /* The destination image is bound as a red texture three times as wide
1397 * as the actual image. Our shader is effectively running one color
1398 * component at a time. We need to pick off the appropriate component
1399 * from the source color and write that to destination red.
1401 assert(dst_pos
->num_components
== 2);
1403 nir_ssa_def
*color_component
=
1404 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1405 nir_channel(&b
, color
, 0),
1406 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1407 nir_channel(&b
, color
, 1),
1408 nir_channel(&b
, color
, 2)));
1410 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1411 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1414 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1420 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1421 struct blorp_params
*params
,
1422 const struct brw_blorp_blit_prog_key
*prog_key
)
1424 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1425 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1428 void *mem_ctx
= ralloc_context(NULL
);
1430 const unsigned *program
;
1431 struct brw_wm_prog_data prog_data
;
1433 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1434 nir
->info
.name
= ralloc_strdup(nir
, "BLORP-blit");
1436 struct brw_wm_prog_key wm_key
;
1437 brw_blorp_init_wm_prog_key(&wm_key
);
1438 wm_key
.tex
.compressed_multisample_layout_mask
=
1439 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1440 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1441 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1443 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1447 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1448 program
, prog_data
.base
.program_size
,
1449 &prog_data
.base
, sizeof(prog_data
),
1450 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1452 ralloc_free(mem_ctx
);
1457 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1458 GLfloat src0
, GLfloat src1
,
1459 GLfloat dst0
, GLfloat dst1
,
1462 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1464 /* When not mirroring a coordinate (say, X), we need:
1465 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1467 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1469 * blorp program uses "round toward zero" to convert the
1470 * transformed floating point coordinates to integer coordinates,
1471 * whereas the behaviour we actually want is "round to nearest",
1472 * so 0.5 provides the necessary correction.
1474 xform
->multiplier
= scale
;
1475 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1477 /* When mirroring X we need:
1478 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1480 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1482 xform
->multiplier
= -scale
;
1483 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1488 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1489 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1491 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1492 struct isl_extent2d px_size_sa
=
1493 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1494 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1495 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1496 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1497 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1499 *tile_x_px
= info
->tile_x_sa
;
1500 *tile_y_px
= info
->tile_y_sa
;
1505 blorp_surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1506 struct brw_blorp_surface_info
*info
)
1510 /* Just bail if we have nothing to do. */
1511 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1512 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1513 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1516 /* If this gets triggered then we've gotten here twice which. This
1517 * shouldn't happen thanks to the above early return.
1519 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1521 uint32_t layer
= 0, z
= 0;
1522 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1523 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1525 layer
= info
->view
.base_array_layer
;
1527 uint32_t byte_offset
;
1528 isl_surf_get_image_surf(isl_dev
, &info
->surf
,
1529 info
->view
.base_level
, layer
, z
,
1531 &byte_offset
, &info
->tile_x_sa
, &info
->tile_y_sa
);
1532 info
->addr
.offset
+= byte_offset
;
1534 uint32_t tile_x_px
, tile_y_px
;
1535 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1537 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we place
1538 * the image at the tile boundary and offset our sampling or rendering.
1539 * For this reason, we need to grow the image by the offset to ensure that
1540 * the hardware doesn't think we've gone past the edge.
1542 info
->surf
.logical_level0_px
.w
+= tile_x_px
;
1543 info
->surf
.logical_level0_px
.h
+= tile_y_px
;
1544 info
->surf
.phys_level0_sa
.w
+= info
->tile_x_sa
;
1545 info
->surf
.phys_level0_sa
.h
+= info
->tile_y_sa
;
1547 /* The view is also different now. */
1548 info
->view
.base_level
= 0;
1549 info
->view
.levels
= 1;
1550 info
->view
.base_array_layer
= 0;
1551 info
->view
.array_len
= 1;
1556 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1557 struct brw_blorp_surface_info
*info
)
1559 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1561 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1562 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1564 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1565 info
->surf
.samples
= 1;
1566 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1570 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1571 struct brw_blorp_surface_info
*info
)
1573 assert(info
->surf
.tiling
== ISL_TILING_W
);
1575 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1576 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1578 /* On gen7+, we don't have interleaved multisampling for color render
1579 * targets so we have to fake it.
1581 * TODO: Are we sure we don't also need to fake it on gen6?
1583 if (isl_dev
->info
->gen
> 6 &&
1584 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1585 surf_fake_interleaved_msaa(isl_dev
, info
);
1588 if (isl_dev
->info
->gen
== 6) {
1589 /* Gen6 stencil buffers have a very large alignment coming in from the
1590 * miptree. It's out-of-bounds for what the surface state can handle.
1591 * Since we have a single layer and level, it doesn't really matter as
1592 * long as we don't pass a bogus value into isl_surf_fill_state().
1594 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1597 /* Now that we've converted everything to a simple 2-D surface with only
1598 * one miplevel, we can go about retiling it.
1600 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1601 info
->surf
.tiling
= ISL_TILING_Y0
;
1602 info
->surf
.logical_level0_px
.width
=
1603 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1604 info
->surf
.logical_level0_px
.height
=
1605 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1606 info
->tile_x_sa
*= 2;
1607 info
->tile_y_sa
/= 2;
1611 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1613 /* The current code doesn't support offsets into the aux buffers. This
1614 * should be possible, but we need to make sure the offset is page
1615 * aligned for both the surface and the aux buffer surface. Generally
1616 * this mean using the page aligned offset for the aux buffer.
1618 * Currently the cases where we must split the blit are limited to cases
1619 * where we don't have a aux buffer.
1621 if (surf
->aux_addr
.buffer
!= NULL
)
1624 /* We can't support splitting the blit for gen <= 7, because the qpitch
1625 * size is calculated by the hardware based on the surface height for
1626 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1628 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1635 can_shrink_surfaces(const struct blorp_params
*params
)
1638 can_shrink_surface(¶ms
->src
) &&
1639 can_shrink_surface(¶ms
->dst
);
1643 get_max_surface_size(const struct gen_device_info
*devinfo
,
1644 const struct blorp_params
*params
)
1646 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1647 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1648 return max
>> 4; /* A smaller restriction when debug is enabled */
1654 double src0
, src1
, dst0
, dst1
;
1659 struct blt_axis x
, y
;
1662 static enum isl_format
1663 get_red_format_for_rgb_format(enum isl_format format
)
1665 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1667 switch (fmtl
->channels
.r
.bits
) {
1669 switch (fmtl
->channels
.r
.type
) {
1671 return ISL_FORMAT_R8_UNORM
;
1673 return ISL_FORMAT_R8_SNORM
;
1675 return ISL_FORMAT_R8_UINT
;
1677 return ISL_FORMAT_R8_SINT
;
1679 unreachable("Invalid 8-bit RGB channel type");
1682 switch (fmtl
->channels
.r
.type
) {
1684 return ISL_FORMAT_R16_UNORM
;
1686 return ISL_FORMAT_R16_SNORM
;
1688 return ISL_FORMAT_R16_FLOAT
;
1690 return ISL_FORMAT_R16_UINT
;
1692 return ISL_FORMAT_R16_SINT
;
1694 unreachable("Invalid 8-bit RGB channel type");
1697 switch (fmtl
->channels
.r
.type
) {
1699 return ISL_FORMAT_R32_FLOAT
;
1701 return ISL_FORMAT_R32_UINT
;
1703 return ISL_FORMAT_R32_SINT
;
1705 unreachable("Invalid 8-bit RGB channel type");
1708 unreachable("Invalid number of red channel bits");
1713 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1714 struct brw_blorp_surface_info
*info
)
1716 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1718 info
->surf
.logical_level0_px
.width
*= 3;
1719 info
->surf
.phys_level0_sa
.width
*= 3;
1720 info
->tile_x_sa
*= 3;
1722 enum isl_format red_format
=
1723 get_red_format_for_rgb_format(info
->view
.format
);
1725 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1726 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1727 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1728 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1730 info
->surf
.format
= info
->view
.format
= red_format
;
1733 enum blit_shrink_status
{
1735 BLIT_WIDTH_SHRINK
= 1,
1736 BLIT_HEIGHT_SHRINK
= 2,
1739 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1740 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1741 * returned, then the blit was successful.
1743 static enum blit_shrink_status
1744 try_blorp_blit(struct blorp_batch
*batch
,
1745 struct blorp_params
*params
,
1746 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1747 struct blt_coords
*coords
)
1749 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1751 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1752 wm_prog_key
->texture_data_type
= nir_type_int
;
1753 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1754 wm_prog_key
->texture_data_type
= nir_type_uint
;
1756 wm_prog_key
->texture_data_type
= nir_type_float
;
1759 /* src_samples and dst_samples are the true sample counts */
1760 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1761 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1763 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1765 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1768 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1769 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1771 /* Round floating point values to nearest integer to avoid "off by one texel"
1772 * kind of errors when blitting.
1774 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1775 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1776 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1777 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1779 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1780 coords
->x
.src0
, coords
->x
.src1
,
1781 coords
->x
.dst0
, coords
->x
.dst1
,
1783 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1784 coords
->y
.src0
, coords
->y
.src1
,
1785 coords
->y
.dst0
, coords
->y
.dst1
,
1789 if (devinfo
->gen
== 4) {
1790 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
1791 * Convert them to a single slice on gen4.
1793 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1794 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1795 wm_prog_key
->need_dst_offset
= true;
1798 if (params
->src
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1799 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->src
);
1800 wm_prog_key
->need_src_offset
= true;
1804 if (devinfo
->gen
> 6 &&
1805 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1806 assert(params
->dst
.surf
.samples
> 1);
1808 /* We must expand the rectangle we send through the rendering pipeline,
1809 * to account for the fact that we are mapping the destination region as
1810 * single-sampled when it is in fact multisampled. We must also align
1811 * it to a multiple of the multisampling pattern, because the
1812 * differences between multisampled and single-sampled surface formats
1813 * will mean that pixels are scrambled within the multisampling pattern.
1814 * TODO: what if this makes the coordinates too large?
1816 * Note: this only works if the destination surface uses the IMS layout.
1817 * If it's UMS, then we have no choice but to set up the rendering
1818 * pipeline as multisampled.
1820 struct isl_extent2d px_size_sa
=
1821 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1822 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1823 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1824 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1825 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1827 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1829 wm_prog_key
->use_kill
= true;
1830 wm_prog_key
->need_dst_offset
= true;
1833 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1834 /* We must modify the rectangle we send through the rendering pipeline
1835 * (and the size and x/y offset of the destination surface), to account
1836 * for the fact that we are mapping it as Y-tiled when it is in fact
1839 * Both Y tiling and W tiling can be understood as organizations of
1840 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1841 * is different, but the layout of the 32-byte sub-tiles within the 4k
1842 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1843 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1844 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1846 * Therefore, to account for the layout differences within the 32-byte
1847 * sub-tiles, we must expand the rectangle so the X coordinates of its
1848 * edges are multiples of 8 (the W sub-tile width), and its Y
1849 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1850 * Then we need to scale the X and Y coordinates of the rectangle to
1851 * account for the differences in aspect ratio between the Y and W
1852 * sub-tiles. We need to modify the layer width and height similarly.
1854 * A correction needs to be applied when MSAA is in use: since
1855 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1856 * we need to align the Y coordinates to multiples of 8, so that when
1857 * they are divided by two they are still multiples of 4.
1859 * Note: Since the x/y offset of the surface will be applied using the
1860 * SURFACE_STATE command packet, it will be invisible to the swizzling
1861 * code in the shader; therefore it needs to be in a multiple of the
1862 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1863 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1864 * buffer), and the miplevel alignment used for stencil buffers is 8
1865 * pixels horizontally and either 4 or 8 pixels vertically (see
1866 * intel_horizontal_texture_alignment_unit() and
1867 * intel_vertical_texture_alignment_unit()).
1869 * Note: Also, since the SURFACE_STATE command packet can only apply
1870 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1871 * vertically, it is important that the offsets will be multiples of
1872 * these sizes after they are converted into Y-tiled coordinates.
1873 * Fortunately they will be, since we know from above that the offsets
1874 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1875 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1877 * TODO: what if this makes the coordinates (or the texture size) too
1880 const unsigned x_align
= 8;
1881 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1882 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1883 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1884 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1885 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1887 /* Retile the surface to Y-tiled */
1888 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1890 wm_prog_key
->dst_tiled_w
= true;
1891 wm_prog_key
->use_kill
= true;
1892 wm_prog_key
->need_dst_offset
= true;
1894 if (params
->dst
.surf
.samples
> 1) {
1895 /* If the destination surface is a W-tiled multisampled stencil
1896 * buffer that we're mapping as Y tiled, then we need to arrange for
1897 * the WM program to run once per sample rather than once per pixel,
1898 * because the memory layout of related samples doesn't match between
1901 wm_prog_key
->persample_msaa_dispatch
= true;
1905 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1906 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1907 * Broadwell adds support for sampling from stencil.
1909 * See the comments above concerning x/y offset alignment for the
1910 * destination surface.
1912 * TODO: what if this makes the texture size too large?
1914 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1916 wm_prog_key
->src_tiled_w
= true;
1917 wm_prog_key
->need_src_offset
= true;
1920 /* tex_samples and rt_samples are the sample counts that are set up in
1923 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1924 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1926 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1927 * use to access the source and destination surfaces.
1929 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1930 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1932 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1933 /* We are blitting from a multisample buffer to a multisample buffer, so
1934 * we must preserve samples within a pixel. This means we have to
1935 * arrange for the WM program to run once per sample rather than once
1938 wm_prog_key
->persample_msaa_dispatch
= true;
1941 params
->num_samples
= params
->dst
.surf
.samples
;
1943 if ((wm_prog_key
->filter
== BLORP_FILTER_AVERAGE
||
1944 wm_prog_key
->filter
== BLORP_FILTER_BILINEAR
) &&
1945 batch
->blorp
->isl_dev
->info
->gen
<= 6) {
1946 /* Gen4-5 don't support non-normalized texture coordinates */
1947 wm_prog_key
->src_coords_normalized
= true;
1948 params
->wm_inputs
.src_inv_size
[0] =
1949 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.width
,
1950 params
->src
.view
.base_level
);
1951 params
->wm_inputs
.src_inv_size
[1] =
1952 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.height
,
1953 params
->src
.view
.base_level
);
1956 if (isl_format_get_layout(params
->dst
.view
.format
)->bpb
% 3 == 0) {
1957 /* We can't render to RGB formats natively because they aren't a
1958 * power-of-two size. Instead, we fake them by using a red format
1959 * with the same channel type and size and emitting shader code to
1960 * only write one channel at a time.
1965 /* If it happens to be sRGB, we need to force a conversion */
1966 if (params
->dst
.view
.format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
)
1967 wm_prog_key
->dst_format
= ISL_FORMAT_R8G8B8_UNORM_SRGB
;
1969 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1971 wm_prog_key
->dst_rgb
= true;
1972 wm_prog_key
->need_dst_offset
= true;
1973 } else if (isl_format_is_rgbx(params
->dst
.view
.format
)) {
1974 /* We can handle RGBX formats easily enough by treating them as RGBA */
1975 params
->dst
.view
.format
=
1976 isl_format_rgbx_to_rgba(params
->dst
.view
.format
);
1977 } else if (params
->dst
.view
.format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
1978 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
1979 params
->dst
.view
.format
= ISL_FORMAT_R32_UNORM
;
1980 } else if (params
->dst
.view
.format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
1981 params
->dst
.view
.swizzle
=
1982 isl_swizzle_compose(params
->dst
.view
.swizzle
,
1983 ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
));
1984 params
->dst
.view
.format
= ISL_FORMAT_B4G4R4A4_UNORM
;
1985 } else if (params
->dst
.view
.format
== ISL_FORMAT_L8_UNORM_SRGB
) {
1986 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
1987 params
->dst
.view
.format
= ISL_FORMAT_R8_UNORM
;
1988 } else if (params
->dst
.view
.format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
1989 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
1990 params
->dst
.view
.format
= ISL_FORMAT_R32_UINT
;
1993 if (devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
1994 !isl_swizzle_is_identity(params
->src
.view
.swizzle
)) {
1995 wm_prog_key
->src_swizzle
= params
->src
.view
.swizzle
;
1996 params
->src
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
1998 wm_prog_key
->src_swizzle
= ISL_SWIZZLE_IDENTITY
;
2001 if (!isl_swizzle_supports_rendering(devinfo
, params
->dst
.view
.swizzle
)) {
2002 wm_prog_key
->dst_swizzle
= params
->dst
.view
.swizzle
;
2003 params
->dst
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
2005 wm_prog_key
->dst_swizzle
= ISL_SWIZZLE_IDENTITY
;
2008 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
2009 assert(wm_prog_key
->need_src_offset
);
2010 surf_get_intratile_offset_px(¶ms
->src
,
2011 ¶ms
->wm_inputs
.src_offset
.x
,
2012 ¶ms
->wm_inputs
.src_offset
.y
);
2015 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
2016 assert(wm_prog_key
->need_dst_offset
);
2017 surf_get_intratile_offset_px(¶ms
->dst
,
2018 ¶ms
->wm_inputs
.dst_offset
.x
,
2019 ¶ms
->wm_inputs
.dst_offset
.y
);
2020 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
2021 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
2022 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
2023 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
2026 /* For some texture types, we need to pass the layer through the sampler. */
2027 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
2029 if (!brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
))
2032 if (!blorp_ensure_sf_program(batch
->blorp
, params
))
2035 unsigned result
= 0;
2036 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
2037 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
2038 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
2039 result
|= BLIT_WIDTH_SHRINK
;
2040 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
2041 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
2042 result
|= BLIT_HEIGHT_SHRINK
;
2045 batch
->blorp
->exec(batch
, params
);
2051 /* Adjust split blit source coordinates for the current destination
2055 adjust_split_source_coords(const struct blt_axis
*orig
,
2056 struct blt_axis
*split_coords
,
2059 /* When scale is greater than 0, then we are growing from the start, so
2060 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
2061 * source range shrinks from the end. In that case src0 is adjusted by
2062 * delta1, and src1 is adjusted by delta0.
2064 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
2065 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
2066 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
2067 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
2070 static struct isl_extent2d
2071 get_px_size_sa(const struct isl_surf
*surf
)
2073 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
2075 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
2078 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
2082 shrink_surface_params(const struct isl_device
*dev
,
2083 struct brw_blorp_surface_info
*info
,
2084 double *x0
, double *x1
, double *y0
, double *y1
)
2086 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
2087 struct isl_extent2d px_size_sa
;
2090 blorp_surf_convert_to_single_slice(dev
, info
);
2092 px_size_sa
= get_px_size_sa(&info
->surf
);
2094 /* Because this gets called after we lower compressed images, the tile
2095 * offsets may be non-zero and we need to incorporate them in our
2098 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
2099 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
2100 isl_tiling_get_intratile_offset_sa(info
->surf
.tiling
,
2101 info
->surf
.format
, info
->surf
.row_pitch
,
2102 x_offset_sa
, y_offset_sa
,
2104 &info
->tile_x_sa
, &info
->tile_y_sa
);
2106 info
->addr
.offset
+= byte_offset
;
2108 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
2111 info
->tile_x_sa
= 0;
2113 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
2116 info
->tile_y_sa
= 0;
2118 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
2119 info
->surf
.logical_level0_px
.width
= size
;
2120 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
2122 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
2123 info
->surf
.logical_level0_px
.height
= size
;
2124 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
2128 shrink_surfaces(const struct isl_device
*dev
,
2129 struct blorp_params
*params
,
2130 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2131 struct blt_coords
*coords
)
2133 /* Shrink source surface */
2134 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
2135 &coords
->y
.src0
, &coords
->y
.src1
);
2136 wm_prog_key
->need_src_offset
= false;
2138 /* Shrink destination surface */
2139 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
2140 &coords
->y
.dst0
, &coords
->y
.dst1
);
2141 wm_prog_key
->need_dst_offset
= false;
2145 do_blorp_blit(struct blorp_batch
*batch
,
2146 const struct blorp_params
*orig_params
,
2147 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2148 const struct blt_coords
*orig
)
2150 struct blorp_params params
;
2151 struct blt_coords blit_coords
;
2152 struct blt_coords split_coords
= *orig
;
2153 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
2154 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
2155 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
2156 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
2162 bool x_done
, y_done
;
2163 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
2165 params
= *orig_params
;
2166 blit_coords
= split_coords
;
2168 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
2170 enum blit_shrink_status result
=
2171 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
2173 if (result
& BLIT_WIDTH_SHRINK
) {
2176 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2177 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2179 if (result
& BLIT_HEIGHT_SHRINK
) {
2182 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2183 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2187 assert(can_shrink_surfaces(orig_params
));
2192 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
2193 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
2196 } else if (y_done
) {
2197 split_coords
.x
.dst0
+= w
;
2198 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2199 split_coords
.y
.dst0
= orig
->y
.dst0
;
2200 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2201 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2203 split_coords
.y
.dst0
+= h
;
2204 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2205 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2211 blorp_blit(struct blorp_batch
*batch
,
2212 const struct blorp_surf
*src_surf
,
2213 unsigned src_level
, unsigned src_layer
,
2214 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2215 const struct blorp_surf
*dst_surf
,
2216 unsigned dst_level
, unsigned dst_layer
,
2217 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2218 float src_x0
, float src_y0
,
2219 float src_x1
, float src_y1
,
2220 float dst_x0
, float dst_y0
,
2221 float dst_x1
, float dst_y1
,
2222 enum blorp_filter filter
,
2223 bool mirror_x
, bool mirror_y
)
2225 struct blorp_params params
;
2226 blorp_params_init(¶ms
);
2228 /* We cannot handle combined depth and stencil. */
2229 if (src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2230 assert(src_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2231 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2232 assert(dst_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2234 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
2235 assert(src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
);
2236 /* Prior to Broadwell, we can't render to R8_UINT */
2237 if (batch
->blorp
->isl_dev
->info
->gen
< 8) {
2238 src_format
= ISL_FORMAT_R8_UNORM
;
2239 dst_format
= ISL_FORMAT_R8_UNORM
;
2243 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2244 src_layer
, src_format
, false);
2245 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2246 dst_layer
, dst_format
, true);
2248 params
.src
.view
.swizzle
= src_swizzle
;
2249 params
.dst
.view
.swizzle
= dst_swizzle
;
2251 struct brw_blorp_blit_prog_key wm_prog_key
= {
2252 .shader_type
= BLORP_SHADER_TYPE_BLIT
,
2256 /* Scaling factors used for bilinear filtering in multisample scaled
2259 if (params
.src
.surf
.samples
== 16)
2260 wm_prog_key
.x_scale
= 4.0f
;
2262 wm_prog_key
.x_scale
= 2.0f
;
2263 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2265 params
.wm_inputs
.rect_grid
.x1
=
2266 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2267 wm_prog_key
.x_scale
- 1.0f
;
2268 params
.wm_inputs
.rect_grid
.y1
=
2269 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2270 wm_prog_key
.y_scale
- 1.0f
;
2272 struct blt_coords coords
= {
2289 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2292 static enum isl_format
2293 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2295 /* The choice of UNORM and UINT formats is very intentional here. Most
2296 * of the time, we want to use a UINT format to avoid any rounding error
2297 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2298 * (It's the only format allowed in conjunction with W-tiling.) Also we
2299 * intentionally use the 4-channel formats whenever we can. This is so
2300 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2301 * even though one of them is 3/4 the size of the other. The choice of
2302 * UNORM vs. UINT is also very intentional because we don't have 8 or
2303 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2304 * Fortunately, the only time we should ever use two different formats in
2305 * the table below is for RGB -> RGBA blits and so we will never have any
2306 * UNORM/UINT mismatch.
2308 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2310 case 8: return ISL_FORMAT_R8_UINT
;
2311 case 16: return ISL_FORMAT_R8G8_UINT
;
2312 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2313 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2314 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2315 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2316 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2317 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2319 unreachable("Unknown format bpb");
2323 case 8: return ISL_FORMAT_R8_UINT
;
2324 case 16: return ISL_FORMAT_R8G8_UINT
;
2325 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2326 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2327 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2328 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2329 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2330 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2332 unreachable("Unknown format bpb");
2337 /** Returns a UINT format that is CCS-compatible with the given format
2339 * The PRM's say absolutely nothing about how render compression works. The
2340 * only thing they provide is a list of formats on which it is and is not
2341 * supported. Empirical testing indicates that the compression is only based
2342 * on the bit-layout of the format and the channel encoding doesn't matter.
2343 * So, while texture views don't work in general, you can create a view as
2344 * long as the bit-layout of the formats are the same.
2346 * Fortunately, for every render compression capable format, the UINT format
2347 * with the same bit layout also supports render compression. This means that
2348 * we only need to handle UINT formats for copy operations. In order to do
2349 * copies between formats with different bit layouts, we attach both with a
2350 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2351 * operation between the two bit layouts.
2353 static enum isl_format
2354 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2356 switch (fmtl
->format
) {
2357 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2358 case ISL_FORMAT_R32G32B32A32_SINT
:
2359 case ISL_FORMAT_R32G32B32A32_UINT
:
2360 case ISL_FORMAT_R32G32B32A32_UNORM
:
2361 case ISL_FORMAT_R32G32B32A32_SNORM
:
2362 case ISL_FORMAT_R32G32B32X32_FLOAT
:
2363 return ISL_FORMAT_R32G32B32A32_UINT
;
2365 case ISL_FORMAT_R16G16B16A16_UNORM
:
2366 case ISL_FORMAT_R16G16B16A16_SNORM
:
2367 case ISL_FORMAT_R16G16B16A16_SINT
:
2368 case ISL_FORMAT_R16G16B16A16_UINT
:
2369 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2370 case ISL_FORMAT_R16G16B16X16_UNORM
:
2371 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2372 return ISL_FORMAT_R16G16B16A16_UINT
;
2374 case ISL_FORMAT_R32G32_FLOAT
:
2375 case ISL_FORMAT_R32G32_SINT
:
2376 case ISL_FORMAT_R32G32_UINT
:
2377 case ISL_FORMAT_R32G32_UNORM
:
2378 case ISL_FORMAT_R32G32_SNORM
:
2379 return ISL_FORMAT_R32G32_UINT
;
2381 case ISL_FORMAT_B8G8R8A8_UNORM
:
2382 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2383 case ISL_FORMAT_R8G8B8A8_UNORM
:
2384 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2385 case ISL_FORMAT_R8G8B8A8_SNORM
:
2386 case ISL_FORMAT_R8G8B8A8_SINT
:
2387 case ISL_FORMAT_R8G8B8A8_UINT
:
2388 case ISL_FORMAT_B8G8R8X8_UNORM
:
2389 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2390 case ISL_FORMAT_R8G8B8X8_UNORM
:
2391 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2392 return ISL_FORMAT_R8G8B8A8_UINT
;
2394 case ISL_FORMAT_R16G16_UNORM
:
2395 case ISL_FORMAT_R16G16_SNORM
:
2396 case ISL_FORMAT_R16G16_SINT
:
2397 case ISL_FORMAT_R16G16_UINT
:
2398 case ISL_FORMAT_R16G16_FLOAT
:
2399 return ISL_FORMAT_R16G16_UINT
;
2401 case ISL_FORMAT_R32_SINT
:
2402 case ISL_FORMAT_R32_UINT
:
2403 case ISL_FORMAT_R32_FLOAT
:
2404 case ISL_FORMAT_R32_UNORM
:
2405 case ISL_FORMAT_R32_SNORM
:
2406 return ISL_FORMAT_R32_UINT
;
2408 case ISL_FORMAT_B10G10R10A2_UNORM
:
2409 case ISL_FORMAT_B10G10R10A2_UNORM_SRGB
:
2410 case ISL_FORMAT_R10G10B10A2_UNORM
:
2411 case ISL_FORMAT_R10G10B10A2_UINT
:
2412 return ISL_FORMAT_R10G10B10A2_UINT
;
2415 unreachable("Not a compressible format");
2420 blorp_surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2421 struct brw_blorp_surface_info
*info
,
2422 uint32_t *x
, uint32_t *y
,
2423 uint32_t *width
, uint32_t *height
)
2425 const struct isl_format_layout
*fmtl
=
2426 isl_format_get_layout(info
->surf
.format
);
2428 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2430 /* This is a compressed surface. We need to convert it to a single
2431 * slice (because compressed layouts don't perfectly match uncompressed
2432 * ones with the same bpb) and divide x, y, width, and height by the
2435 blorp_surf_convert_to_single_slice(isl_dev
, info
);
2437 if (width
&& height
) {
2439 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2440 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2441 assert(*width
% fmtl
->bw
== 0 ||
2442 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2443 assert(*height
% fmtl
->bh
== 0 ||
2444 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2446 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2447 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2451 assert(*x
% fmtl
->bw
== 0);
2452 assert(*y
% fmtl
->bh
== 0);
2457 info
->surf
.logical_level0_px
.width
=
2458 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
2459 info
->surf
.logical_level0_px
.height
=
2460 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
2462 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
2463 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
2464 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2465 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2467 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2468 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2469 info
->tile_x_sa
/= fmtl
->bw
;
2470 info
->tile_y_sa
/= fmtl
->bh
;
2472 /* It's now an uncompressed surface so we need an uncompressed format */
2473 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2477 blorp_copy(struct blorp_batch
*batch
,
2478 const struct blorp_surf
*src_surf
,
2479 unsigned src_level
, unsigned src_layer
,
2480 const struct blorp_surf
*dst_surf
,
2481 unsigned dst_level
, unsigned dst_layer
,
2482 uint32_t src_x
, uint32_t src_y
,
2483 uint32_t dst_x
, uint32_t dst_y
,
2484 uint32_t src_width
, uint32_t src_height
)
2486 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2487 struct blorp_params params
;
2489 if (src_width
== 0 || src_height
== 0)
2492 blorp_params_init(¶ms
);
2493 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2494 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2495 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2496 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2498 struct brw_blorp_blit_prog_key wm_prog_key
= {
2499 .shader_type
= BLORP_SHADER_TYPE_BLIT
,
2500 .filter
= BLORP_FILTER_NONE
,
2501 .need_src_offset
= src_surf
->tile_x_sa
|| src_surf
->tile_y_sa
,
2502 .need_dst_offset
= dst_surf
->tile_x_sa
|| dst_surf
->tile_y_sa
,
2505 const struct isl_format_layout
*src_fmtl
=
2506 isl_format_get_layout(params
.src
.surf
.format
);
2507 const struct isl_format_layout
*dst_fmtl
=
2508 isl_format_get_layout(params
.dst
.surf
.format
);
2510 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2511 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2512 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2513 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2514 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2515 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2517 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2518 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2519 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2520 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2521 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2522 params
.src
.view
.format
= params
.dst
.view
.format
;
2524 params
.src
.view
.format
=
2525 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2527 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2528 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2529 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2530 params
.dst
.view
.format
= params
.src
.view
.format
;
2532 params
.dst
.view
.format
=
2533 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2536 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2537 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2540 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2541 /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
2542 * enabled even though CCS_E doesn't technically do sRGB on SKL because
2543 * we stomp everything to UINT anyway. The one thing we have to be
2544 * careful of is clear colors. Because fast clear colors for sRGB on
2545 * gen9 are encoded as the float values between format conversion and
2546 * sRGB curve application, a given clear color float will convert to the
2547 * same bits regardless of whether the format is UNORM or sRGB.
2548 * Therefore, we can handle sRGB without any special cases.
2550 UNUSED
enum isl_format linear_src_format
=
2551 isl_format_srgb_to_linear(src_surf
->surf
->format
);
2552 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2554 params
.src
.view
.format
));
2556 isl_color_value_pack(¶ms
.src
.clear_color
,
2557 linear_src_format
, packed
);
2558 isl_color_value_unpack(¶ms
.src
.clear_color
,
2559 params
.src
.view
.format
, packed
);
2562 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2563 /* See above where we handle linear_src_format */
2564 UNUSED
enum isl_format linear_dst_format
=
2565 isl_format_srgb_to_linear(dst_surf
->surf
->format
);
2566 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2568 params
.dst
.view
.format
));
2570 isl_color_value_pack(¶ms
.dst
.clear_color
,
2571 linear_dst_format
, packed
);
2572 isl_color_value_unpack(¶ms
.dst
.clear_color
,
2573 params
.dst
.view
.format
, packed
);
2576 if (params
.src
.view
.format
!= params
.dst
.view
.format
) {
2577 enum isl_format src_cast_format
= params
.src
.view
.format
;
2578 enum isl_format dst_cast_format
= params
.dst
.view
.format
;
2580 /* The BLORP bitcast code gets confused by RGB formats. Just treat them
2581 * as RGBA and then everything will be happy. This is perfectly safe
2582 * because BLORP likes to treat things as if they have vec4 colors all
2585 if (isl_format_is_rgb(src_cast_format
))
2586 src_cast_format
= isl_format_rgb_to_rgba(src_cast_format
);
2587 if (isl_format_is_rgb(dst_cast_format
))
2588 dst_cast_format
= isl_format_rgb_to_rgba(dst_cast_format
);
2590 if (src_cast_format
!= dst_cast_format
) {
2591 wm_prog_key
.format_bit_cast
= true;
2592 wm_prog_key
.src_format
= src_cast_format
;
2593 wm_prog_key
.dst_format
= dst_cast_format
;
2597 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2598 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2600 &src_width
, &src_height
);
2601 wm_prog_key
.need_src_offset
= true;
2604 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2605 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2606 &dst_x
, &dst_y
, NULL
, NULL
);
2607 wm_prog_key
.need_dst_offset
= true;
2610 /* Once both surfaces are stompped to uncompressed as needed, the
2611 * destination size is the same as the source size.
2613 uint32_t dst_width
= src_width
;
2614 uint32_t dst_height
= src_height
;
2616 struct blt_coords coords
= {
2619 .src1
= src_x
+ src_width
,
2621 .dst1
= dst_x
+ dst_width
,
2626 .src1
= src_y
+ src_height
,
2628 .dst1
= dst_y
+ dst_height
,
2633 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2636 static enum isl_format
2637 isl_format_for_size(unsigned size_B
)
2640 case 1: return ISL_FORMAT_R8_UINT
;
2641 case 2: return ISL_FORMAT_R8G8_UINT
;
2642 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
2643 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
2644 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
2646 unreachable("Not a power-of-two format size");
2651 * Returns the greatest common divisor of a and b that is a power of two.
2654 gcd_pow2_u64(uint64_t a
, uint64_t b
)
2656 assert(a
> 0 || b
> 0);
2658 unsigned a_log2
= ffsll(a
) - 1;
2659 unsigned b_log2
= ffsll(b
) - 1;
2661 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
2662 * case, the MIN2() will take the other one. If both are 0 then we will
2663 * hit the assert above.
2665 return 1 << MIN2(a_log2
, b_log2
);
2669 do_buffer_copy(struct blorp_batch
*batch
,
2670 struct blorp_address
*src
,
2671 struct blorp_address
*dst
,
2672 int width
, int height
, int block_size
)
2674 /* The actual format we pick doesn't matter as blorp will throw it away.
2675 * The only thing that actually matters is the size.
2677 enum isl_format format
= isl_format_for_size(block_size
);
2680 struct isl_surf surf
;
2681 ok
= isl_surf_init(batch
->blorp
->isl_dev
, &surf
,
2682 .dim
= ISL_SURF_DIM_2D
,
2690 .row_pitch
= width
* block_size
,
2691 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
2692 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
2693 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
2696 struct blorp_surf src_blorp_surf
= {
2701 struct blorp_surf dst_blorp_surf
= {
2706 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
2707 0, 0, 0, 0, width
, height
);
2711 blorp_buffer_copy(struct blorp_batch
*batch
,
2712 struct blorp_address src
,
2713 struct blorp_address dst
,
2716 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
2717 uint64_t copy_size
= size
;
2719 /* This is maximum possible width/height our HW can handle */
2720 uint64_t max_surface_dim
= 1 << (devinfo
->gen
>= 7 ? 14 : 13);
2722 /* First, we compute the biggest format that can be used with the
2723 * given offsets and size.
2726 bs
= gcd_pow2_u64(bs
, src
.offset
);
2727 bs
= gcd_pow2_u64(bs
, dst
.offset
);
2728 bs
= gcd_pow2_u64(bs
, size
);
2730 /* First, we make a bunch of max-sized copies */
2731 uint64_t max_copy_size
= max_surface_dim
* max_surface_dim
* bs
;
2732 while (copy_size
>= max_copy_size
) {
2733 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, max_surface_dim
, bs
);
2734 copy_size
-= max_copy_size
;
2735 src
.offset
+= max_copy_size
;
2736 dst
.offset
+= max_copy_size
;
2739 /* Now make a max-width copy */
2740 uint64_t height
= copy_size
/ (max_surface_dim
* bs
);
2741 assert(height
< max_surface_dim
);
2743 uint64_t rect_copy_size
= height
* max_surface_dim
* bs
;
2744 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, height
, bs
);
2745 copy_size
-= rect_copy_size
;
2746 src
.offset
+= rect_copy_size
;
2747 dst
.offset
+= rect_copy_size
;
2750 /* Finally, make a small copy to finish it off */
2751 if (copy_size
!= 0) {
2752 do_buffer_copy(batch
, &src
, &dst
, copy_size
/ bs
, 1, bs
);