2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "blorp_nir_builder.h"
25 #include "compiler/nir/nir_format_convert.h"
27 #include "blorp_priv.h"
29 /* header-only include needed for _mesa_unorm_to_float and friends. */
30 #include "mesa/main/format_utils.h"
32 #define FILE_DEBUG_FLAG DEBUG_BLORP
34 static const bool split_blorp_blit_debug
= false;
37 * Enum to specify the order of arguments in a sampler message
39 enum sampler_message_arg
41 SAMPLER_MESSAGE_ARG_U_FLOAT
,
42 SAMPLER_MESSAGE_ARG_V_FLOAT
,
43 SAMPLER_MESSAGE_ARG_U_INT
,
44 SAMPLER_MESSAGE_ARG_V_INT
,
45 SAMPLER_MESSAGE_ARG_R_INT
,
46 SAMPLER_MESSAGE_ARG_SI_INT
,
47 SAMPLER_MESSAGE_ARG_MCS_INT
,
48 SAMPLER_MESSAGE_ARG_ZERO_INT
,
51 struct brw_blorp_blit_vars
{
52 /* Input values from brw_blorp_wm_inputs */
53 nir_variable
*v_discard_rect
;
54 nir_variable
*v_rect_grid
;
55 nir_variable
*v_coord_transform
;
56 nir_variable
*v_src_z
;
57 nir_variable
*v_src_offset
;
58 nir_variable
*v_dst_offset
;
59 nir_variable
*v_src_inv_size
;
62 nir_variable
*frag_coord
;
65 nir_variable
*color_out
;
69 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
70 const struct brw_blorp_blit_prog_key
*key
)
72 /* Blended and scaled blits never use pixel discard. */
73 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
75 #define LOAD_INPUT(name, type)\
76 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
78 LOAD_INPUT(discard_rect
, glsl_vec4_type())
79 LOAD_INPUT(rect_grid
, glsl_vec4_type())
80 LOAD_INPUT(coord_transform
, glsl_vec4_type())
81 LOAD_INPUT(src_z
, glsl_uint_type())
82 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
83 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
84 LOAD_INPUT(src_inv_size
, glsl_vector_type(GLSL_TYPE_FLOAT
, 2))
88 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
89 glsl_vec4_type(), "gl_FragCoord");
90 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
91 v
->frag_coord
->data
.origin_upper_left
= true;
93 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
94 glsl_vec4_type(), "gl_FragColor");
95 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
99 blorp_blit_get_frag_coords(nir_builder
*b
,
100 const struct brw_blorp_blit_prog_key
*key
,
101 struct brw_blorp_blit_vars
*v
)
103 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_var(b
, v
->frag_coord
));
105 /* Account for destination surface intratile offset
107 * Transformation parameters giving translation from destination to source
108 * coordinates don't take into account possible intra-tile destination
109 * offset. Therefore it has to be first subtracted from the incoming
110 * coordinates. Vertices are set up based on coordinates containing the
113 if (key
->need_dst_offset
)
114 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
116 if (key
->persample_msaa_dispatch
) {
117 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
118 nir_load_sample_id(b
));
120 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
125 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
129 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
130 struct brw_blorp_blit_vars
*v
)
132 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
134 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
135 nir_channel(b
, coord_transform
, 3));
136 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
137 nir_channel(b
, coord_transform
, 2));
139 return nir_fadd(b
, nir_fmul(b
, src_pos
, mul
), offset
);
143 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
144 struct brw_blorp_blit_vars
*v
)
146 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
147 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
148 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
149 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
150 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
151 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
153 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
154 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
155 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
156 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
158 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
160 nir_intrinsic_instr
*discard
=
161 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
162 discard
->src
[0] = nir_src_for_ssa(oob
);
163 nir_builder_instr_insert(b
, &discard
->instr
);
166 static nir_tex_instr
*
167 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
168 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
169 nir_alu_type dst_type
)
171 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
175 tex
->dest_type
= dst_type
;
176 tex
->is_array
= false;
177 tex
->is_shadow
= false;
179 /* Blorp only has one texture and it's bound at unit 0 */
182 tex
->texture_index
= 0;
183 tex
->sampler_index
= 0;
185 /* To properly handle 3-D and 2-D array textures, we pull the Z component
186 * from an input. TODO: This is a bit magic; we should probably make this
187 * more explicit in the future.
189 assert(pos
->num_components
>= 2);
190 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
191 nir_load_var(b
, v
->v_src_z
));
193 tex
->src
[0].src_type
= nir_tex_src_coord
;
194 tex
->src
[0].src
= nir_src_for_ssa(pos
);
195 tex
->coord_components
= 3;
197 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
203 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
204 const struct brw_blorp_blit_prog_key
*key
, nir_ssa_def
*pos
)
206 if (key
->need_src_offset
)
207 pos
= nir_fadd(b
, pos
, nir_i2f32(b
, nir_load_var(b
, v
->v_src_offset
)));
209 /* If the sampler requires normalized coordinates, we need to compensate. */
210 if (key
->src_coords_normalized
)
211 pos
= nir_fmul(b
, pos
, nir_load_var(b
, v
->v_src_inv_size
));
214 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2,
215 key
->texture_data_type
);
217 assert(pos
->num_components
== 2);
218 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
219 tex
->src
[1].src_type
= nir_tex_src_lod
;
220 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
222 nir_builder_instr_insert(b
, &tex
->instr
);
224 return &tex
->dest
.ssa
;
228 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
229 nir_ssa_def
*pos
, nir_alu_type dst_type
)
232 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
234 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
235 tex
->src
[1].src_type
= nir_tex_src_lod
;
236 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
238 nir_builder_instr_insert(b
, &tex
->instr
);
240 return &tex
->dest
.ssa
;
244 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
245 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
248 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
249 mcs
!= NULL
? 3 : 2, dst_type
);
251 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
253 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
254 if (pos
->num_components
== 2) {
255 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
257 assert(pos
->num_components
== 3);
258 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
262 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
263 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
266 nir_builder_instr_insert(b
, &tex
->instr
);
268 return &tex
->dest
.ssa
;
272 blorp_blit_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
276 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
277 pos
, 1, nir_type_int
);
279 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
281 nir_builder_instr_insert(b
, &tex
->instr
);
283 return &tex
->dest
.ssa
;
287 * Emit code to compensate for the difference between Y and W tiling.
289 * This code modifies the X and Y coordinates according to the formula:
291 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
293 * (See brw_blorp_build_nir_shader).
295 static inline nir_ssa_def
*
296 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
298 assert(pos
->num_components
== 2);
299 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
300 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
302 /* Given X and Y coordinates that describe an address using Y tiling,
303 * translate to the X and Y coordinates that describe the same address
306 * If we break down the low order bits of X and Y, using a
307 * single letter to represent each low-order bit:
309 * X = A << 7 | 0bBCDEFGH
310 * Y = J << 5 | 0bKLMNP (1)
312 * Then we can apply the Y tiling formula to see the memory offset being
315 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
317 * If we apply the W detiling formula to this memory location, that the
318 * corresponding X' and Y' coordinates are:
320 * X' = A << 6 | 0bBCDPFH (3)
321 * Y' = J << 6 | 0bKLMNEG
323 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
324 * we need to make the following computation:
326 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
327 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
329 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
330 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
331 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
332 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
334 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
335 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
336 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
337 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
339 return nir_vec2(b
, x_W
, y_W
);
343 * Emit code to compensate for the difference between Y and W tiling.
345 * This code modifies the X and Y coordinates according to the formula:
347 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
349 * (See brw_blorp_build_nir_shader).
351 static inline nir_ssa_def
*
352 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
354 assert(pos
->num_components
== 2);
355 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
356 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
358 /* Applying the same logic as above, but in reverse, we obtain the
361 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
362 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
364 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
365 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
366 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
367 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
368 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
370 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
371 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
372 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
374 return nir_vec2(b
, x_Y
, y_Y
);
378 * Emit code to compensate for the difference between MSAA and non-MSAA
381 * This code modifies the X and Y coordinates according to the formula:
383 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
385 * (See brw_blorp_blit_program).
387 static inline nir_ssa_def
*
388 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
389 unsigned num_samples
, enum isl_msaa_layout layout
)
391 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
394 case ISL_MSAA_LAYOUT_NONE
:
395 assert(pos
->num_components
== 2);
397 case ISL_MSAA_LAYOUT_ARRAY
:
398 /* No translation needed */
400 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
401 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
402 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
403 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
404 nir_channel(b
, pos
, 2);
406 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
407 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
408 switch (num_samples
) {
411 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
412 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
415 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
416 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
417 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
419 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
420 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
421 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
422 if (num_samples
== 2) {
425 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
426 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
427 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
432 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
433 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
435 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
437 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
438 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
439 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
440 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
441 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
442 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
443 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
447 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
448 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
450 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
453 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
454 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
455 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
456 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
457 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
458 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
459 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
460 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
464 unreachable("Invalid number of samples for IMS layout");
467 return nir_vec2(b
, x_out
, y_out
);
471 unreachable("Invalid MSAA layout");
476 * Emit code to compensate for the difference between MSAA and non-MSAA
479 * This code modifies the X and Y coordinates according to the formula:
481 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
483 * (See brw_blorp_blit_program).
485 static inline nir_ssa_def
*
486 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
487 unsigned num_samples
, enum isl_msaa_layout layout
)
489 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
492 case ISL_MSAA_LAYOUT_NONE
:
493 /* No translation necessary, and S should already be zero. */
494 assert(pos
->num_components
== 2);
496 case ISL_MSAA_LAYOUT_ARRAY
:
497 /* No translation necessary. */
499 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
500 assert(pos
->num_components
== 2);
502 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
503 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
505 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
506 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
507 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
508 switch (num_samples
) {
511 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
512 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
513 * S = (X & 0b10) >> 1
515 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
516 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
517 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
518 * S = (Y & 0b10) | (X & 0b10) >> 1
520 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
521 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
522 if (num_samples
== 2) {
524 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
526 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
527 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
528 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
529 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
534 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
535 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
536 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
537 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
539 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
540 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
541 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
542 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
543 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
544 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
545 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
549 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
550 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
551 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
552 * S = (Y & 0b100) << 1 | (X & 0b100) |
553 * (Y & 0b10) | (X & 0b10) >> 1
555 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
556 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
557 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
558 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
559 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
560 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
561 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
562 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
566 unreachable("Invalid number of samples for IMS layout");
569 return nir_vec3(b
, x_out
, y_out
, s_out
);
573 unreachable("Invalid MSAA layout");
578 * Count the number of trailing 1 bits in the given value. For example:
580 * count_trailing_one_bits(0) == 0
581 * count_trailing_one_bits(7) == 3
582 * count_trailing_one_bits(11) == 2
584 static inline int count_trailing_one_bits(unsigned value
)
586 #ifdef HAVE___BUILTIN_CTZ
587 return __builtin_ctz(~value
);
589 return _mesa_bitcount(value
& ~(value
+ 1));
594 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
595 nir_ssa_def
*pos
, unsigned tex_samples
,
596 enum isl_aux_usage tex_aux_usage
,
597 nir_alu_type dst_type
)
599 /* If non-null, this is the outer-most if statement */
600 nir_if
*outer_if
= NULL
;
602 nir_variable
*color
=
603 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
605 nir_ssa_def
*mcs
= NULL
;
606 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
607 mcs
= blorp_blit_txf_ms_mcs(b
, v
, pos
);
609 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
611 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
613 * This ensures that when all samples have the same value, no numerical
614 * precision is lost, since each addition operation always adds two equal
615 * values, and summing two equal floating point values does not lose
618 * We perform this computation by treating the texture_data array as a
619 * stack and performing the following operations:
621 * - push sample 0 onto stack
622 * - push sample 1 onto stack
623 * - add top two stack entries
624 * - push sample 2 onto stack
625 * - push sample 3 onto stack
626 * - add top two stack entries
627 * - add top two stack entries
628 * - divide top stack entry by 4
630 * Note that after pushing sample i onto the stack, the number of add
631 * operations we do is equal to the number of trailing 1 bits in i. This
632 * works provided the total number of samples is a power of two, which it
633 * always is for i965.
635 * For integer formats, we replace the add operations with average
636 * operations and skip the final division.
638 nir_ssa_def
*texture_data
[5];
639 unsigned stack_depth
= 0;
640 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
641 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
643 /* Push sample i onto the stack */
644 assert(stack_depth
< ARRAY_SIZE(texture_data
));
646 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
647 nir_channel(b
, pos
, 1),
649 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
651 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
652 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
653 * suggests an optimization:
655 * "A simple optimization with probable large return in
656 * performance is to compare the MCS value to zero (indicating
657 * all samples are on sample slice 0), and sample only from
658 * sample slice 0 using ld2dss if MCS is zero."
660 * Note that in the case where the MCS value is zero, sampling from
661 * sample slice 0 using ld2dss and sampling from sample 0 using
662 * ld2dms are equivalent (since all samples are on sample slice 0).
663 * Since we have already sampled from sample 0, all we need to do is
664 * skip the remaining fetches and averaging if MCS is zero.
666 * It's also trivial to detect when the MCS has the magic clear color
667 * value. In this case, the txf we did on sample 0 will return the
668 * clear color and we can skip the remaining fetches just like we do
671 nir_ssa_def
*mcs_zero
=
672 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
673 if (tex_samples
== 16) {
674 mcs_zero
= nir_iand(b
, mcs_zero
,
675 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
677 nir_ssa_def
*mcs_clear
=
678 blorp_nir_mcs_is_clear_color(b
, mcs
, tex_samples
);
680 nir_if
*if_stmt
= nir_if_create(b
->shader
);
681 if_stmt
->condition
= nir_src_for_ssa(nir_ior(b
, mcs_zero
, mcs_clear
));
682 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
684 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
685 nir_store_var(b
, color
, texture_data
[0], 0xf);
687 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
691 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
692 assert(stack_depth
>= 2);
695 assert(dst_type
== nir_type_float
);
696 texture_data
[stack_depth
- 1] =
697 nir_fadd(b
, texture_data
[stack_depth
- 1],
698 texture_data
[stack_depth
]);
702 /* We should have just 1 sample on the stack now. */
703 assert(stack_depth
== 1);
705 texture_data
[0] = nir_fmul(b
, texture_data
[0],
706 nir_imm_float(b
, 1.0 / tex_samples
));
708 nir_store_var(b
, color
, texture_data
[0], 0xf);
711 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
713 return nir_load_var(b
, color
);
716 static inline nir_ssa_def
*
717 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
721 memset(&v
, 0, sizeof(v
));
725 return nir_build_imm(build
, 4, 32, v
);
729 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
730 unsigned tex_samples
,
731 const struct brw_blorp_blit_prog_key
*key
,
732 struct brw_blorp_blit_vars
*v
)
734 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
735 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
736 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
738 /* Translate coordinates to lay out the samples in a rectangular grid
739 * roughly corresponding to sample locations.
741 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
742 /* Adjust coordinates so that integers represent pixel centers rather
745 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
746 /* Clamp the X, Y texture coordinates to properly handle the sampling of
747 * texels on texture edges.
749 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
750 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
751 nir_channel(b
, rect_grid
, 1)));
753 /* Store the fractional parts to be used as bilinear interpolation
756 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
757 /* Round the float coordinates down to nearest integer */
758 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
760 nir_ssa_def
*tex_data
[4];
761 for (unsigned i
= 0; i
< 4; ++i
) {
762 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
763 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
764 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
766 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
767 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
769 /* The MCS value we fetch has to match up with the pixel that we're
770 * sampling from. Since we sample from different pixels in each
771 * iteration of this "for" loop, the call to mcs_fetch() should be
772 * here inside the loop after computing the pixel coordinates.
774 nir_ssa_def
*mcs
= NULL
;
775 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
776 mcs
= blorp_blit_txf_ms_mcs(b
, v
, sample_coords_int
);
778 /* Compute sample index and map the sample index to a sample number.
779 * Sample index layout shows the numbering of slots in a rectangular
780 * grid of samples with in a pixel. Sample number layout shows the
781 * rectangular grid of samples roughly corresponding to the real sample
782 * locations with in a pixel.
783 * In case of 4x MSAA, layout of sample indices matches the layout of
791 * In case of 8x MSAA the two layouts don't match.
792 * sample index layout : --------- sample number layout : ---------
793 * | 0 | 1 | | 3 | 7 |
794 * --------- ---------
795 * | 2 | 3 | | 5 | 0 |
796 * --------- ---------
797 * | 4 | 5 | | 1 | 2 |
798 * --------- ---------
799 * | 6 | 7 | | 4 | 6 |
800 * --------- ---------
802 * Fortunately, this can be done fairly easily as:
803 * S' = (0x17306425 >> (S * 4)) & 0xf
805 * In the case of 16x MSAA the two layouts don't match.
806 * Sample index layout: Sample number layout:
807 * --------------------- ---------------------
808 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
809 * --------------------- ---------------------
810 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
811 * --------------------- ---------------------
812 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
813 * --------------------- ---------------------
814 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
815 * --------------------- ---------------------
817 * This is equivalent to
818 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
820 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
821 nir_ssa_def
*sample
=
822 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
823 key
->x_scale
* key
->y_scale
));
824 sample
= nir_f2i32(b
, sample
);
826 if (tex_samples
== 8) {
827 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
828 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
829 nir_imm_int(b
, 0xf));
830 } else if (tex_samples
== 16) {
831 nir_ssa_def
*sample_low
=
832 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
833 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
834 nir_imm_int(b
, 0xf));
835 nir_ssa_def
*sample_high
=
836 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
837 nir_ishl(b
, nir_iadd(b
, sample
,
840 nir_imm_int(b
, 0xf));
842 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
843 sample_low
, sample_high
);
845 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
846 nir_channel(b
, sample_coords_int
, 1),
848 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
851 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
852 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
853 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
854 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
858 /** Perform a color bit-cast operation
860 * For copy operations involving CCS, we may need to use different formats for
861 * the source and destination surfaces. The two formats must both be UINT
862 * formats and must have the same size but may have different bit layouts.
863 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
864 * to R16G16_UINT. This function generates code to shuffle bits around to get
865 * us from one to the other.
868 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
869 const struct brw_blorp_blit_prog_key
*key
)
871 assert(key
->texture_data_type
== nir_type_uint
);
873 if (key
->dst_bpc
> key
->src_bpc
) {
874 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
875 nir_ssa_def
*dst_chan
[2] = { u
, u
};
877 unsigned dst_idx
= 0;
878 for (unsigned i
= 0; i
< 4; i
++) {
879 nir_ssa_def
*shifted
= nir_ishl(b
, nir_channel(b
, color
, i
),
880 nir_imm_int(b
, shift
));
882 dst_chan
[dst_idx
] = shifted
;
884 dst_chan
[dst_idx
] = nir_ior(b
, dst_chan
[dst_idx
], shifted
);
887 shift
+= key
->src_bpc
;
888 if (shift
>= key
->dst_bpc
) {
894 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], u
, u
);
896 assert(key
->dst_bpc
< key
->src_bpc
);
898 nir_ssa_def
*mask
= nir_imm_int(b
, ~0u >> (32 - key
->dst_bpc
));
900 nir_ssa_def
*dst_chan
[4];
901 unsigned src_idx
= 0;
903 for (unsigned i
= 0; i
< 4; i
++) {
904 dst_chan
[i
] = nir_iand(b
, nir_ushr(b
, nir_channel(b
, color
, src_idx
),
905 nir_imm_int(b
, shift
)),
907 shift
+= key
->dst_bpc
;
908 if (shift
>= key
->src_bpc
) {
914 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], dst_chan
[2], dst_chan
[3]);
919 select_color_channel(struct nir_builder
*b
, nir_ssa_def
*color
,
920 nir_alu_type data_type
,
921 enum isl_channel_select chan
)
923 if (chan
== ISL_CHANNEL_SELECT_ZERO
) {
924 return nir_imm_int(b
, 0);
925 } else if (chan
== ISL_CHANNEL_SELECT_ONE
) {
929 return nir_imm_int(b
, 1);
931 return nir_imm_float(b
, 1);
933 unreachable("Invalid data type");
936 assert((unsigned)(chan
- ISL_CHANNEL_SELECT_RED
) < 4);
937 return nir_channel(b
, color
, chan
- ISL_CHANNEL_SELECT_RED
);
942 swizzle_color(struct nir_builder
*b
, nir_ssa_def
*color
,
943 struct isl_swizzle swizzle
, nir_alu_type data_type
)
946 select_color_channel(b
, color
, data_type
, swizzle
.r
),
947 select_color_channel(b
, color
, data_type
, swizzle
.g
),
948 select_color_channel(b
, color
, data_type
, swizzle
.b
),
949 select_color_channel(b
, color
, data_type
, swizzle
.a
));
953 * Generator for WM programs used in BLORP blits.
955 * The bulk of the work done by the WM program is to wrap and unwrap the
956 * coordinate transformations used by the hardware to store surfaces in
957 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
958 * sample index for a multisampled surface) to a memory offset by the
959 * following formulas:
961 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
962 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
964 * For a single-sampled surface, or for a multisampled surface using
965 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
968 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
969 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
970 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
971 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
973 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
974 * embeds the sample number into bit 1 of the X and Y coordinates:
976 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
977 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
978 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
979 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
980 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
981 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
982 * S = (Y & 0b10) | (X & 0b10) >> 1
984 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
985 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
988 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
989 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
990 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
991 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
992 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
993 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
994 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
996 * For X tiling, tile() combines together the low-order bits of the X and Y
997 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
998 * bytes wide and 8 rows high:
1000 * tile(x_tiled, X, Y, S) = A
1001 * where A = tile_num << 12 | offset
1002 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
1003 * offset = (Y' & 0b111) << 9
1004 * | (X & 0b111111111)
1006 * Y' = Y + S * qpitch
1007 * detile(x_tiled, A) = (X, Y, S)
1008 * where X = X' / cpp
1011 * Y' = (tile_num / tile_pitch) << 3
1012 * | (A & 0b111000000000) >> 9
1013 * X' = (tile_num % tile_pitch) << 9
1014 * | (A & 0b111111111)
1016 * (In all tiling formulas, cpp is the number of bytes occupied by a single
1017 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
1018 * to fill the width of the surface, and qpitch is the spacing (in rows)
1019 * between array slices).
1021 * For Y tiling, tile() combines together the low-order bits of the X and Y
1022 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
1023 * bytes wide and 32 rows high:
1025 * tile(y_tiled, X, Y, S) = A
1026 * where A = tile_num << 12 | offset
1027 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
1028 * offset = (X' & 0b1110000) << 5
1029 * | (Y' & 0b11111) << 4
1032 * Y' = Y + S * qpitch
1033 * detile(y_tiled, A) = (X, Y, S)
1034 * where X = X' / cpp
1037 * Y' = (tile_num / tile_pitch) << 5
1038 * | (A & 0b111110000) >> 4
1039 * X' = (tile_num % tile_pitch) << 7
1040 * | (A & 0b111000000000) >> 5
1043 * For W tiling, tile() combines together the low-order bits of the X and Y
1044 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1045 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1046 * buffers, which always have cpp = 1 and S=0):
1048 * tile(w_tiled, X, Y, S) = A
1049 * where A = tile_num << 12 | offset
1050 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1051 * offset = (X' & 0b111000) << 6
1052 * | (Y' & 0b111100) << 3
1053 * | (X' & 0b100) << 2
1054 * | (Y' & 0b10) << 2
1055 * | (X' & 0b10) << 1
1059 * Y' = Y + S * qpitch
1060 * detile(w_tiled, A) = (X, Y, S)
1061 * where X = X' / cpp = X'
1062 * Y = Y' % qpitch = Y'
1063 * S = Y / qpitch = 0
1064 * Y' = (tile_num / tile_pitch) << 6
1065 * | (A & 0b111100000) >> 3
1066 * | (A & 0b1000) >> 2
1068 * X' = (tile_num % tile_pitch) << 6
1069 * | (A & 0b111000000000) >> 6
1070 * | (A & 0b10000) >> 2
1071 * | (A & 0b100) >> 1
1074 * Finally, for a non-tiled surface, tile() simply combines together the X and
1075 * Y coordinates in the natural way:
1077 * tile(untiled, X, Y, S) = A
1078 * where A = Y * pitch + X'
1080 * Y' = Y + S * qpitch
1081 * detile(untiled, A) = (X, Y, S)
1082 * where X = X' / cpp
1088 * (In these formulas, pitch is the number of bytes occupied by a single row
1092 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1093 const struct brw_blorp_blit_prog_key
*key
)
1095 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1096 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1099 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1100 /* If the destination image is W tiled and multisampled, then the thread
1101 * must be dispatched once per sample, not once per pixel. This is
1102 * necessary because after conversion between W and Y tiling, there's no
1103 * guarantee that all samples corresponding to a single pixel will still
1106 assert(key
->persample_msaa_dispatch
);
1110 /* We are blending, which means we won't have an opportunity to
1111 * translate the tiling and sample count for the texture surface. So
1112 * the surface state for the texture must be configured with the correct
1113 * tiling and sample count.
1115 assert(!key
->src_tiled_w
);
1116 assert(key
->tex_samples
== key
->src_samples
);
1117 assert(key
->tex_layout
== key
->src_layout
);
1118 assert(key
->tex_samples
> 0);
1121 if (key
->persample_msaa_dispatch
) {
1122 /* It only makes sense to do persample dispatch if the render target is
1123 * configured as multisampled.
1125 assert(key
->rt_samples
> 0);
1128 /* Make sure layout is consistent with sample count */
1129 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1130 (key
->tex_samples
<= 1));
1131 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1132 (key
->rt_samples
<= 1));
1133 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1134 (key
->src_samples
<= 1));
1135 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1136 (key
->dst_samples
<= 1));
1139 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1141 struct brw_blorp_blit_vars v
;
1142 brw_blorp_blit_vars_init(&b
, &v
, key
);
1144 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1146 /* Render target and texture hardware don't support W tiling until Gen8. */
1147 const bool rt_tiled_w
= false;
1148 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1150 /* The address that data will be written to is determined by the
1151 * coordinates supplied to the WM thread and the tiling and sample count of
1152 * the render target, according to the formula:
1154 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1156 * If the actual tiling and sample count of the destination surface are not
1157 * the same as the configuration of the render target, then these
1158 * coordinates are wrong and we have to adjust them to compensate for the
1161 if (rt_tiled_w
!= key
->dst_tiled_w
||
1162 key
->rt_samples
!= key
->dst_samples
||
1163 key
->rt_layout
!= key
->dst_layout
) {
1164 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1166 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1167 if (rt_tiled_w
!= key
->dst_tiled_w
)
1168 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1169 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1170 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1174 nir_ssa_def
*comp
= NULL
;
1176 /* The destination image is bound as a red texture three times as wide
1177 * as the actual image. Our shader is effectively running one color
1178 * component at a time. We need to save off the component and adjust
1179 * the destination position.
1181 assert(dst_pos
->num_components
== 2);
1182 nir_ssa_def
*dst_x
= nir_channel(&b
, dst_pos
, 0);
1183 comp
= nir_umod(&b
, dst_x
, nir_imm_int(&b
, 3));
1184 dst_pos
= nir_vec2(&b
, nir_idiv(&b
, dst_x
, nir_imm_int(&b
, 3)),
1185 nir_channel(&b
, dst_pos
, 1));
1188 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1190 * That is: X, Y and S now contain the true coordinates and sample index of
1191 * the data that the WM thread should output.
1193 * If we need to kill pixels that are outside the destination rectangle,
1194 * now is the time to do it.
1196 if (key
->use_kill
) {
1197 assert(!(key
->blend
&& key
->blit_scaled
));
1198 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1201 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1202 if (dst_pos
->num_components
== 3) {
1203 /* The sample coordinate is an integer that we want left alone but
1204 * blorp_blit_apply_transform() blindly applies the transform to all
1205 * three coordinates. Grab the original sample index.
1207 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1208 nir_channel(&b
, src_pos
, 1),
1209 nir_channel(&b
, dst_pos
, 2));
1212 /* If the source image is not multisampled, then we want to fetch sample
1213 * number 0, because that's the only sample there is.
1215 if (key
->src_samples
== 1)
1216 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1218 /* X, Y, and S are now the coordinates of the pixel in the source image
1219 * that we want to texture from. Exception: if we are blending, then S is
1220 * irrelevant, because we are going to fetch all samples.
1222 if (key
->blend
&& !key
->blit_scaled
) {
1223 /* Resolves (effecively) use texelFetch, so we need integers and we
1224 * don't care about the sample index if we got one.
1226 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1228 if (devinfo
->gen
== 6) {
1229 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1230 * blending we need with a single linear-interpolated texture lookup
1231 * at the center of the sample. The texture coordinates to be odd
1232 * integers so that they correspond to the center of a 2x2 block
1233 * representing the four samples that maxe up a pixel. So we need
1234 * to multiply our X and Y coordinates each by 2 and then add 1.
1236 assert(key
->src_coords_normalized
);
1237 src_pos
= nir_fadd(&b
,
1238 nir_i2f32(&b
, src_pos
),
1239 nir_imm_float(&b
, 0.5f
));
1240 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1242 /* Gen7+ hardware doesn't automaticaly blend. */
1243 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1245 key
->texture_data_type
);
1247 } else if (key
->blend
&& key
->blit_scaled
) {
1248 assert(!key
->use_kill
);
1249 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1251 if (key
->bilinear_filter
) {
1252 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1254 /* We're going to use texelFetch, so we need integers */
1255 if (src_pos
->num_components
== 2) {
1256 src_pos
= nir_f2i32(&b
, src_pos
);
1258 assert(src_pos
->num_components
== 3);
1259 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1260 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1261 nir_channel(&b
, src_pos
, 2));
1264 /* We aren't blending, which means we just want to fetch a single
1265 * sample from the source surface. The address that we want to fetch
1266 * from is related to the X, Y and S values according to the formula:
1268 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1270 * If the actual tiling and sample count of the source surface are
1271 * not the same as the configuration of the texture, then we need to
1272 * adjust the coordinates to compensate for the difference.
1274 if (tex_tiled_w
!= key
->src_tiled_w
||
1275 key
->tex_samples
!= key
->src_samples
||
1276 key
->tex_layout
!= key
->src_layout
) {
1277 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1279 /* Now (X, Y, S) = detile(src_tiling, offset) */
1280 if (tex_tiled_w
!= key
->src_tiled_w
)
1281 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1282 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1283 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1287 if (key
->need_src_offset
)
1288 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1290 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1292 * In other words: X, Y, and S now contain values which, when passed to
1293 * the texturing unit, will cause data to be read from the correct
1294 * memory location. So we can fetch the texel now.
1296 if (key
->src_samples
== 1) {
1297 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1299 nir_ssa_def
*mcs
= NULL
;
1300 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1301 mcs
= blorp_blit_txf_ms_mcs(&b
, &v
, src_pos
);
1303 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1308 if (!isl_swizzle_is_identity(key
->src_swizzle
)) {
1309 color
= swizzle_color(&b
, color
, key
->src_swizzle
,
1310 key
->texture_data_type
);
1313 if (!isl_swizzle_is_identity(key
->dst_swizzle
)) {
1314 color
= swizzle_color(&b
, color
, isl_swizzle_invert(key
->dst_swizzle
),
1318 if (key
->dst_bpc
!= key
->src_bpc
) {
1319 assert(isl_swizzle_is_identity(key
->src_swizzle
));
1320 assert(isl_swizzle_is_identity(key
->dst_swizzle
));
1321 color
= bit_cast_color(&b
, color
, key
);
1325 /* The destination image is bound as a red texture three times as wide
1326 * as the actual image. Our shader is effectively running one color
1327 * component at a time. We need to pick off the appropriate component
1328 * from the source color and write that to destination red.
1330 assert(dst_pos
->num_components
== 2);
1332 nir_ssa_def
*color_component
=
1333 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1334 nir_channel(&b
, color
, 0),
1335 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1336 nir_channel(&b
, color
, 1),
1337 nir_channel(&b
, color
, 2)));
1339 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1340 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1343 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1349 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1350 struct blorp_params
*params
,
1351 const struct brw_blorp_blit_prog_key
*prog_key
)
1353 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1354 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1357 void *mem_ctx
= ralloc_context(NULL
);
1359 const unsigned *program
;
1360 struct brw_wm_prog_data prog_data
;
1362 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1363 nir
->info
.name
= ralloc_strdup(nir
, "BLORP-blit");
1365 struct brw_wm_prog_key wm_key
;
1366 brw_blorp_init_wm_prog_key(&wm_key
);
1367 wm_key
.tex
.compressed_multisample_layout_mask
=
1368 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1369 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1370 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1372 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1376 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1377 program
, prog_data
.base
.program_size
,
1378 &prog_data
.base
, sizeof(prog_data
),
1379 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1381 ralloc_free(mem_ctx
);
1386 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1387 GLfloat src0
, GLfloat src1
,
1388 GLfloat dst0
, GLfloat dst1
,
1391 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1393 /* When not mirroring a coordinate (say, X), we need:
1394 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1396 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1398 * blorp program uses "round toward zero" to convert the
1399 * transformed floating point coordinates to integer coordinates,
1400 * whereas the behaviour we actually want is "round to nearest",
1401 * so 0.5 provides the necessary correction.
1403 xform
->multiplier
= scale
;
1404 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1406 /* When mirroring X we need:
1407 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1409 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1411 xform
->multiplier
= -scale
;
1412 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1417 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1418 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1420 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1421 struct isl_extent2d px_size_sa
=
1422 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1423 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1424 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1425 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1426 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1428 *tile_x_px
= info
->tile_x_sa
;
1429 *tile_y_px
= info
->tile_y_sa
;
1434 blorp_surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1435 struct brw_blorp_surface_info
*info
)
1439 /* Just bail if we have nothing to do. */
1440 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1441 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1442 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1445 /* If this gets triggered then we've gotten here twice which. This
1446 * shouldn't happen thanks to the above early return.
1448 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1450 uint32_t layer
= 0, z
= 0;
1451 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1452 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1454 layer
= info
->view
.base_array_layer
;
1456 uint32_t byte_offset
;
1457 isl_surf_get_image_surf(isl_dev
, &info
->surf
,
1458 info
->view
.base_level
, layer
, z
,
1460 &byte_offset
, &info
->tile_x_sa
, &info
->tile_y_sa
);
1461 info
->addr
.offset
+= byte_offset
;
1463 uint32_t tile_x_px
, tile_y_px
;
1464 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1466 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we place
1467 * the image at the tile boundary and offset our sampling or rendering.
1468 * For this reason, we need to grow the image by the offset to ensure that
1469 * the hardware doesn't think we've gone past the edge.
1471 info
->surf
.logical_level0_px
.w
+= tile_x_px
;
1472 info
->surf
.logical_level0_px
.h
+= tile_y_px
;
1473 info
->surf
.phys_level0_sa
.w
+= info
->tile_x_sa
;
1474 info
->surf
.phys_level0_sa
.h
+= info
->tile_y_sa
;
1476 /* The view is also different now. */
1477 info
->view
.base_level
= 0;
1478 info
->view
.levels
= 1;
1479 info
->view
.base_array_layer
= 0;
1480 info
->view
.array_len
= 1;
1485 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1486 struct brw_blorp_surface_info
*info
)
1488 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1490 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1491 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1493 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1494 info
->surf
.samples
= 1;
1495 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1499 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1500 struct brw_blorp_surface_info
*info
)
1502 assert(info
->surf
.tiling
== ISL_TILING_W
);
1504 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1505 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1507 /* On gen7+, we don't have interleaved multisampling for color render
1508 * targets so we have to fake it.
1510 * TODO: Are we sure we don't also need to fake it on gen6?
1512 if (isl_dev
->info
->gen
> 6 &&
1513 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1514 surf_fake_interleaved_msaa(isl_dev
, info
);
1517 if (isl_dev
->info
->gen
== 6) {
1518 /* Gen6 stencil buffers have a very large alignment coming in from the
1519 * miptree. It's out-of-bounds for what the surface state can handle.
1520 * Since we have a single layer and level, it doesn't really matter as
1521 * long as we don't pass a bogus value into isl_surf_fill_state().
1523 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1526 /* Now that we've converted everything to a simple 2-D surface with only
1527 * one miplevel, we can go about retiling it.
1529 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1530 info
->surf
.tiling
= ISL_TILING_Y0
;
1531 info
->surf
.logical_level0_px
.width
=
1532 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1533 info
->surf
.logical_level0_px
.height
=
1534 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1535 info
->tile_x_sa
*= 2;
1536 info
->tile_y_sa
/= 2;
1540 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1542 /* The current code doesn't support offsets into the aux buffers. This
1543 * should be possible, but we need to make sure the offset is page
1544 * aligned for both the surface and the aux buffer surface. Generally
1545 * this mean using the page aligned offset for the aux buffer.
1547 * Currently the cases where we must split the blit are limited to cases
1548 * where we don't have a aux buffer.
1550 if (surf
->aux_addr
.buffer
!= NULL
)
1553 /* We can't support splitting the blit for gen <= 7, because the qpitch
1554 * size is calculated by the hardware based on the surface height for
1555 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1557 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1564 can_shrink_surfaces(const struct blorp_params
*params
)
1567 can_shrink_surface(¶ms
->src
) &&
1568 can_shrink_surface(¶ms
->dst
);
1572 get_max_surface_size(const struct gen_device_info
*devinfo
,
1573 const struct blorp_params
*params
)
1575 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1576 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1577 return max
>> 4; /* A smaller restriction when debug is enabled */
1583 double src0
, src1
, dst0
, dst1
;
1588 struct blt_axis x
, y
;
1592 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1593 struct brw_blorp_surface_info
*info
)
1595 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1597 info
->surf
.logical_level0_px
.width
*= 3;
1598 info
->surf
.phys_level0_sa
.width
*= 3;
1599 info
->tile_x_sa
*= 3;
1601 enum isl_format red_format
;
1602 switch (info
->view
.format
) {
1603 case ISL_FORMAT_R8G8B8_UNORM
:
1604 red_format
= ISL_FORMAT_R8_UNORM
;
1606 case ISL_FORMAT_R8G8B8_UINT
:
1607 red_format
= ISL_FORMAT_R8_UINT
;
1609 case ISL_FORMAT_R16G16B16_UNORM
:
1610 red_format
= ISL_FORMAT_R16_UNORM
;
1612 case ISL_FORMAT_R16G16B16_UINT
:
1613 red_format
= ISL_FORMAT_R16_UINT
;
1615 case ISL_FORMAT_R32G32B32_UINT
:
1616 red_format
= ISL_FORMAT_R32_UINT
;
1619 unreachable("Invalid RGB copy destination format");
1621 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1622 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1623 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1624 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1626 info
->surf
.format
= info
->view
.format
= red_format
;
1629 enum blit_shrink_status
{
1631 BLIT_WIDTH_SHRINK
= 1,
1632 BLIT_HEIGHT_SHRINK
= 2,
1635 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1636 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1637 * returned, then the blit was successful.
1639 static enum blit_shrink_status
1640 try_blorp_blit(struct blorp_batch
*batch
,
1641 struct blorp_params
*params
,
1642 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1643 struct blt_coords
*coords
)
1645 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1647 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1648 wm_prog_key
->texture_data_type
= nir_type_int
;
1649 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1650 wm_prog_key
->texture_data_type
= nir_type_uint
;
1652 wm_prog_key
->texture_data_type
= nir_type_float
;
1655 /* src_samples and dst_samples are the true sample counts */
1656 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1657 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1659 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1661 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1664 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1665 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1667 /* Round floating point values to nearest integer to avoid "off by one texel"
1668 * kind of errors when blitting.
1670 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1671 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1672 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1673 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1675 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1676 coords
->x
.src0
, coords
->x
.src1
,
1677 coords
->x
.dst0
, coords
->x
.dst1
,
1679 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1680 coords
->y
.src0
, coords
->y
.src1
,
1681 coords
->y
.dst0
, coords
->y
.dst1
,
1685 if (devinfo
->gen
== 4) {
1686 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
1687 * Convert them to a single slice on gen4.
1689 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1690 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1691 wm_prog_key
->need_dst_offset
= true;
1694 if (params
->src
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1695 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->src
);
1696 wm_prog_key
->need_src_offset
= true;
1700 if (devinfo
->gen
> 6 &&
1701 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1702 assert(params
->dst
.surf
.samples
> 1);
1704 /* We must expand the rectangle we send through the rendering pipeline,
1705 * to account for the fact that we are mapping the destination region as
1706 * single-sampled when it is in fact multisampled. We must also align
1707 * it to a multiple of the multisampling pattern, because the
1708 * differences between multisampled and single-sampled surface formats
1709 * will mean that pixels are scrambled within the multisampling pattern.
1710 * TODO: what if this makes the coordinates too large?
1712 * Note: this only works if the destination surface uses the IMS layout.
1713 * If it's UMS, then we have no choice but to set up the rendering
1714 * pipeline as multisampled.
1716 struct isl_extent2d px_size_sa
=
1717 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1718 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1719 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1720 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1721 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1723 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1725 wm_prog_key
->use_kill
= true;
1726 wm_prog_key
->need_dst_offset
= true;
1729 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1730 /* We must modify the rectangle we send through the rendering pipeline
1731 * (and the size and x/y offset of the destination surface), to account
1732 * for the fact that we are mapping it as Y-tiled when it is in fact
1735 * Both Y tiling and W tiling can be understood as organizations of
1736 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1737 * is different, but the layout of the 32-byte sub-tiles within the 4k
1738 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1739 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1740 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1742 * Therefore, to account for the layout differences within the 32-byte
1743 * sub-tiles, we must expand the rectangle so the X coordinates of its
1744 * edges are multiples of 8 (the W sub-tile width), and its Y
1745 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1746 * Then we need to scale the X and Y coordinates of the rectangle to
1747 * account for the differences in aspect ratio between the Y and W
1748 * sub-tiles. We need to modify the layer width and height similarly.
1750 * A correction needs to be applied when MSAA is in use: since
1751 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1752 * we need to align the Y coordinates to multiples of 8, so that when
1753 * they are divided by two they are still multiples of 4.
1755 * Note: Since the x/y offset of the surface will be applied using the
1756 * SURFACE_STATE command packet, it will be invisible to the swizzling
1757 * code in the shader; therefore it needs to be in a multiple of the
1758 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1759 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1760 * buffer), and the miplevel alignment used for stencil buffers is 8
1761 * pixels horizontally and either 4 or 8 pixels vertically (see
1762 * intel_horizontal_texture_alignment_unit() and
1763 * intel_vertical_texture_alignment_unit()).
1765 * Note: Also, since the SURFACE_STATE command packet can only apply
1766 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1767 * vertically, it is important that the offsets will be multiples of
1768 * these sizes after they are converted into Y-tiled coordinates.
1769 * Fortunately they will be, since we know from above that the offsets
1770 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1771 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1773 * TODO: what if this makes the coordinates (or the texture size) too
1776 const unsigned x_align
= 8;
1777 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1778 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1779 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1780 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1781 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1783 /* Retile the surface to Y-tiled */
1784 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1786 wm_prog_key
->dst_tiled_w
= true;
1787 wm_prog_key
->use_kill
= true;
1788 wm_prog_key
->need_dst_offset
= true;
1790 if (params
->dst
.surf
.samples
> 1) {
1791 /* If the destination surface is a W-tiled multisampled stencil
1792 * buffer that we're mapping as Y tiled, then we need to arrange for
1793 * the WM program to run once per sample rather than once per pixel,
1794 * because the memory layout of related samples doesn't match between
1797 wm_prog_key
->persample_msaa_dispatch
= true;
1801 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1802 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1803 * Broadwell adds support for sampling from stencil.
1805 * See the comments above concerning x/y offset alignment for the
1806 * destination surface.
1808 * TODO: what if this makes the texture size too large?
1810 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1812 wm_prog_key
->src_tiled_w
= true;
1813 wm_prog_key
->need_src_offset
= true;
1816 /* tex_samples and rt_samples are the sample counts that are set up in
1819 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1820 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1822 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1823 * use to access the source and destination surfaces.
1825 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1826 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1828 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1829 /* We are blitting from a multisample buffer to a multisample buffer, so
1830 * we must preserve samples within a pixel. This means we have to
1831 * arrange for the WM program to run once per sample rather than once
1834 wm_prog_key
->persample_msaa_dispatch
= true;
1837 params
->num_samples
= params
->dst
.surf
.samples
;
1839 if ((wm_prog_key
->bilinear_filter
||
1840 (wm_prog_key
->blend
&& !wm_prog_key
->blit_scaled
)) &&
1841 batch
->blorp
->isl_dev
->info
->gen
<= 6) {
1842 /* Gen4-5 don't support non-normalized texture coordinates */
1843 wm_prog_key
->src_coords_normalized
= true;
1844 params
->wm_inputs
.src_inv_size
[0] =
1845 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.width
,
1846 params
->src
.view
.base_level
);
1847 params
->wm_inputs
.src_inv_size
[1] =
1848 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.height
,
1849 params
->src
.view
.base_level
);
1852 if (isl_format_get_layout(params
->dst
.view
.format
)->bpb
% 3 == 0) {
1853 /* We can't render to RGB formats natively because they aren't a
1854 * power-of-two size. Instead, we fake them by using a red format
1855 * with the same channel type and size and emitting shader code to
1856 * only write one channel at a time.
1861 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1863 wm_prog_key
->dst_rgb
= true;
1864 wm_prog_key
->need_dst_offset
= true;
1867 if (devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
1868 !isl_swizzle_is_identity(params
->src
.view
.swizzle
)) {
1869 wm_prog_key
->src_swizzle
= params
->src
.view
.swizzle
;
1870 params
->src
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
1872 wm_prog_key
->src_swizzle
= ISL_SWIZZLE_IDENTITY
;
1875 if (!isl_swizzle_supports_rendering(devinfo
, params
->dst
.view
.swizzle
)) {
1876 wm_prog_key
->dst_swizzle
= params
->dst
.view
.swizzle
;
1877 params
->dst
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
1879 wm_prog_key
->dst_swizzle
= ISL_SWIZZLE_IDENTITY
;
1882 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
1883 assert(wm_prog_key
->need_src_offset
);
1884 surf_get_intratile_offset_px(¶ms
->src
,
1885 ¶ms
->wm_inputs
.src_offset
.x
,
1886 ¶ms
->wm_inputs
.src_offset
.y
);
1889 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
1890 assert(wm_prog_key
->need_dst_offset
);
1891 surf_get_intratile_offset_px(¶ms
->dst
,
1892 ¶ms
->wm_inputs
.dst_offset
.x
,
1893 ¶ms
->wm_inputs
.dst_offset
.y
);
1894 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
1895 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
1896 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
1897 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
1900 /* For some texture types, we need to pass the layer through the sampler. */
1901 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
1903 if (!brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
))
1906 if (!blorp_ensure_sf_program(batch
->blorp
, params
))
1909 unsigned result
= 0;
1910 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
1911 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
1912 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
1913 result
|= BLIT_WIDTH_SHRINK
;
1914 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
1915 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
1916 result
|= BLIT_HEIGHT_SHRINK
;
1919 batch
->blorp
->exec(batch
, params
);
1925 /* Adjust split blit source coordinates for the current destination
1929 adjust_split_source_coords(const struct blt_axis
*orig
,
1930 struct blt_axis
*split_coords
,
1933 /* When scale is greater than 0, then we are growing from the start, so
1934 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
1935 * source range shrinks from the end. In that case src0 is adjusted by
1936 * delta1, and src1 is adjusted by delta0.
1938 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
1939 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
1940 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
1941 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
1944 static struct isl_extent2d
1945 get_px_size_sa(const struct isl_surf
*surf
)
1947 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
1949 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
1952 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
1956 shrink_surface_params(const struct isl_device
*dev
,
1957 struct brw_blorp_surface_info
*info
,
1958 double *x0
, double *x1
, double *y0
, double *y1
)
1960 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
1961 struct isl_extent2d px_size_sa
;
1964 blorp_surf_convert_to_single_slice(dev
, info
);
1966 px_size_sa
= get_px_size_sa(&info
->surf
);
1968 /* Because this gets called after we lower compressed images, the tile
1969 * offsets may be non-zero and we need to incorporate them in our
1972 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
1973 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
1974 isl_tiling_get_intratile_offset_sa(info
->surf
.tiling
,
1975 info
->surf
.format
, info
->surf
.row_pitch
,
1976 x_offset_sa
, y_offset_sa
,
1978 &info
->tile_x_sa
, &info
->tile_y_sa
);
1980 info
->addr
.offset
+= byte_offset
;
1982 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
1985 info
->tile_x_sa
= 0;
1987 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
1990 info
->tile_y_sa
= 0;
1992 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
1993 info
->surf
.logical_level0_px
.width
= size
;
1994 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
1996 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
1997 info
->surf
.logical_level0_px
.height
= size
;
1998 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
2002 shrink_surfaces(const struct isl_device
*dev
,
2003 struct blorp_params
*params
,
2004 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2005 struct blt_coords
*coords
)
2007 /* Shrink source surface */
2008 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
2009 &coords
->y
.src0
, &coords
->y
.src1
);
2010 wm_prog_key
->need_src_offset
= false;
2012 /* Shrink destination surface */
2013 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
2014 &coords
->y
.dst0
, &coords
->y
.dst1
);
2015 wm_prog_key
->need_dst_offset
= false;
2019 do_blorp_blit(struct blorp_batch
*batch
,
2020 const struct blorp_params
*orig_params
,
2021 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2022 const struct blt_coords
*orig
)
2024 struct blorp_params params
;
2025 struct blt_coords blit_coords
;
2026 struct blt_coords split_coords
= *orig
;
2027 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
2028 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
2029 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
2030 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
2036 bool x_done
, y_done
;
2037 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
2039 params
= *orig_params
;
2040 blit_coords
= split_coords
;
2042 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
2044 enum blit_shrink_status result
=
2045 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
2047 if (result
& BLIT_WIDTH_SHRINK
) {
2050 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2051 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2053 if (result
& BLIT_HEIGHT_SHRINK
) {
2056 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2057 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2061 assert(can_shrink_surfaces(orig_params
));
2066 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
2067 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
2070 } else if (y_done
) {
2071 split_coords
.x
.dst0
+= w
;
2072 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2073 split_coords
.y
.dst0
= orig
->y
.dst0
;
2074 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2075 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2077 split_coords
.y
.dst0
+= h
;
2078 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2079 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2085 blorp_blit(struct blorp_batch
*batch
,
2086 const struct blorp_surf
*src_surf
,
2087 unsigned src_level
, unsigned src_layer
,
2088 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2089 const struct blorp_surf
*dst_surf
,
2090 unsigned dst_level
, unsigned dst_layer
,
2091 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2092 float src_x0
, float src_y0
,
2093 float src_x1
, float src_y1
,
2094 float dst_x0
, float dst_y0
,
2095 float dst_x1
, float dst_y1
,
2096 GLenum filter
, bool mirror_x
, bool mirror_y
)
2098 struct blorp_params params
;
2099 blorp_params_init(¶ms
);
2101 /* We cannot handle combined depth and stencil. */
2102 if (src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2103 assert(src_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2104 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2105 assert(dst_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2107 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
2108 assert(src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
);
2109 /* Prior to Broadwell, we can't render to R8_UINT */
2110 if (batch
->blorp
->isl_dev
->info
->gen
< 8) {
2111 src_format
= ISL_FORMAT_R8_UNORM
;
2112 dst_format
= ISL_FORMAT_R8_UNORM
;
2116 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2117 src_layer
, src_format
, false);
2118 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2119 dst_layer
, dst_format
, true);
2121 params
.src
.view
.swizzle
= src_swizzle
;
2122 params
.dst
.view
.swizzle
= dst_swizzle
;
2124 struct brw_blorp_blit_prog_key wm_prog_key
= {
2125 .shader_type
= BLORP_SHADER_TYPE_BLIT
2128 /* Scaled blitting or not. */
2129 wm_prog_key
.blit_scaled
=
2130 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2131 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2133 /* Scaling factors used for bilinear filtering in multisample scaled
2136 if (params
.src
.surf
.samples
== 16)
2137 wm_prog_key
.x_scale
= 4.0f
;
2139 wm_prog_key
.x_scale
= 2.0f
;
2140 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2142 if (filter
== GL_LINEAR
&&
2143 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1) {
2144 wm_prog_key
.bilinear_filter
= true;
2147 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
2148 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
2149 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
2150 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
2151 /* We are downsampling a non-integer color buffer, so blend.
2153 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
2155 * "If the source formats are integer types or stencil values, a
2156 * single sample's value is selected for each pixel."
2158 * This implies we should not blend in that case.
2160 wm_prog_key
.blend
= true;
2163 params
.wm_inputs
.rect_grid
.x1
=
2164 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2165 wm_prog_key
.x_scale
- 1.0f
;
2166 params
.wm_inputs
.rect_grid
.y1
=
2167 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2168 wm_prog_key
.y_scale
- 1.0f
;
2170 struct blt_coords coords
= {
2187 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2190 static enum isl_format
2191 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2193 /* The choice of UNORM and UINT formats is very intentional here. Most
2194 * of the time, we want to use a UINT format to avoid any rounding error
2195 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2196 * (It's the only format allowed in conjunction with W-tiling.) Also we
2197 * intentionally use the 4-channel formats whenever we can. This is so
2198 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2199 * even though one of them is 3/4 the size of the other. The choice of
2200 * UNORM vs. UINT is also very intentional because we don't have 8 or
2201 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2202 * Fortunately, the only time we should ever use two different formats in
2203 * the table below is for RGB -> RGBA blits and so we will never have any
2204 * UNORM/UINT mismatch.
2206 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2208 case 8: return ISL_FORMAT_R8_UINT
;
2209 case 16: return ISL_FORMAT_R8G8_UINT
;
2210 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2211 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2212 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2213 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2214 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2215 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2217 unreachable("Unknown format bpb");
2221 case 8: return ISL_FORMAT_R8_UINT
;
2222 case 16: return ISL_FORMAT_R8G8_UINT
;
2223 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2224 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2225 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2226 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2227 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2228 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2230 unreachable("Unknown format bpb");
2235 /** Returns a UINT format that is CCS-compatible with the given format
2237 * The PRM's say absolutely nothing about how render compression works. The
2238 * only thing they provide is a list of formats on which it is and is not
2239 * supported. Empirical testing indicates that the compression is only based
2240 * on the bit-layout of the format and the channel encoding doesn't matter.
2241 * So, while texture views don't work in general, you can create a view as
2242 * long as the bit-layout of the formats are the same.
2244 * Fortunately, for every render compression capable format, the UINT format
2245 * with the same bit layout also supports render compression. This means that
2246 * we only need to handle UINT formats for copy operations. In order to do
2247 * copies between formats with different bit layouts, we attach both with a
2248 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2249 * operation between the two bit layouts.
2251 static enum isl_format
2252 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2254 switch (fmtl
->format
) {
2255 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2256 case ISL_FORMAT_R32G32B32A32_SINT
:
2257 case ISL_FORMAT_R32G32B32A32_UINT
:
2258 case ISL_FORMAT_R32G32B32A32_UNORM
:
2259 case ISL_FORMAT_R32G32B32A32_SNORM
:
2260 case ISL_FORMAT_R32G32B32X32_FLOAT
:
2261 return ISL_FORMAT_R32G32B32A32_UINT
;
2263 case ISL_FORMAT_R16G16B16A16_UNORM
:
2264 case ISL_FORMAT_R16G16B16A16_SNORM
:
2265 case ISL_FORMAT_R16G16B16A16_SINT
:
2266 case ISL_FORMAT_R16G16B16A16_UINT
:
2267 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2268 case ISL_FORMAT_R16G16B16X16_UNORM
:
2269 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2270 return ISL_FORMAT_R16G16B16A16_UINT
;
2272 case ISL_FORMAT_R32G32_FLOAT
:
2273 case ISL_FORMAT_R32G32_SINT
:
2274 case ISL_FORMAT_R32G32_UINT
:
2275 case ISL_FORMAT_R32G32_UNORM
:
2276 case ISL_FORMAT_R32G32_SNORM
:
2277 return ISL_FORMAT_R32G32_UINT
;
2279 case ISL_FORMAT_B8G8R8A8_UNORM
:
2280 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2281 case ISL_FORMAT_R8G8B8A8_UNORM
:
2282 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2283 case ISL_FORMAT_R8G8B8A8_SNORM
:
2284 case ISL_FORMAT_R8G8B8A8_SINT
:
2285 case ISL_FORMAT_R8G8B8A8_UINT
:
2286 case ISL_FORMAT_B8G8R8X8_UNORM
:
2287 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2288 case ISL_FORMAT_R8G8B8X8_UNORM
:
2289 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2290 return ISL_FORMAT_R8G8B8A8_UINT
;
2292 case ISL_FORMAT_R16G16_UNORM
:
2293 case ISL_FORMAT_R16G16_SNORM
:
2294 case ISL_FORMAT_R16G16_SINT
:
2295 case ISL_FORMAT_R16G16_UINT
:
2296 case ISL_FORMAT_R16G16_FLOAT
:
2297 return ISL_FORMAT_R16G16_UINT
;
2299 case ISL_FORMAT_R32_SINT
:
2300 case ISL_FORMAT_R32_UINT
:
2301 case ISL_FORMAT_R32_FLOAT
:
2302 case ISL_FORMAT_R32_UNORM
:
2303 case ISL_FORMAT_R32_SNORM
:
2304 return ISL_FORMAT_R32_UINT
;
2307 unreachable("Not a compressible format");
2311 /* Takes an isl_color_value and returns a color value that is the original
2312 * color value only bit-casted to a UINT format. This value, together with
2313 * the format from get_ccs_compatible_uint_format, will yield the same bit
2314 * value as the original color and format.
2316 static union isl_color_value
2317 bitcast_color_value_to_uint(union isl_color_value color
,
2318 const struct isl_format_layout
*fmtl
)
2320 /* All CCS formats have the same number of bits in each channel */
2321 const struct isl_channel_layout
*chan
= &fmtl
->channels
.r
;
2323 union isl_color_value bits
;
2324 switch (chan
->type
) {
2327 /* Hardware will ignore the high bits so there's no need to cast */
2332 for (unsigned i
= 0; i
< 4; i
++)
2333 bits
.u32
[i
] = _mesa_float_to_unorm(color
.f32
[i
], chan
->bits
);
2337 for (unsigned i
= 0; i
< 4; i
++)
2338 bits
.i32
[i
] = _mesa_float_to_snorm(color
.f32
[i
], chan
->bits
);
2342 switch (chan
->bits
) {
2344 for (unsigned i
= 0; i
< 4; i
++)
2345 bits
.u32
[i
] = _mesa_float_to_half(color
.f32
[i
]);
2353 unreachable("Invalid float format size");
2358 unreachable("Invalid channel type");
2361 switch (fmtl
->format
) {
2362 case ISL_FORMAT_B8G8R8A8_UNORM
:
2363 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2364 case ISL_FORMAT_B8G8R8X8_UNORM
:
2365 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
: {
2366 /* If it's a BGRA format, we need to swap blue and red */
2367 uint32_t tmp
= bits
.u32
[0];
2368 bits
.u32
[0] = bits
.u32
[2];
2374 break; /* Nothing to do */
2381 blorp_surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2382 struct brw_blorp_surface_info
*info
,
2383 uint32_t *x
, uint32_t *y
,
2384 uint32_t *width
, uint32_t *height
)
2386 const struct isl_format_layout
*fmtl
=
2387 isl_format_get_layout(info
->surf
.format
);
2389 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2391 /* This is a compressed surface. We need to convert it to a single
2392 * slice (because compressed layouts don't perfectly match uncompressed
2393 * ones with the same bpb) and divide x, y, width, and height by the
2396 blorp_surf_convert_to_single_slice(isl_dev
, info
);
2398 if (width
&& height
) {
2400 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2401 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2402 assert(*width
% fmtl
->bw
== 0 ||
2403 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2404 assert(*height
% fmtl
->bh
== 0 ||
2405 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2407 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2408 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2412 assert(*x
% fmtl
->bw
== 0);
2413 assert(*y
% fmtl
->bh
== 0);
2418 info
->surf
.logical_level0_px
.width
=
2419 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
2420 info
->surf
.logical_level0_px
.height
=
2421 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
2423 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
2424 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
2425 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2426 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2428 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2429 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2430 info
->tile_x_sa
/= fmtl
->bw
;
2431 info
->tile_y_sa
/= fmtl
->bh
;
2433 /* It's now an uncompressed surface so we need an uncompressed format */
2434 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2438 blorp_copy(struct blorp_batch
*batch
,
2439 const struct blorp_surf
*src_surf
,
2440 unsigned src_level
, unsigned src_layer
,
2441 const struct blorp_surf
*dst_surf
,
2442 unsigned dst_level
, unsigned dst_layer
,
2443 uint32_t src_x
, uint32_t src_y
,
2444 uint32_t dst_x
, uint32_t dst_y
,
2445 uint32_t src_width
, uint32_t src_height
)
2447 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2448 struct blorp_params params
;
2450 if (src_width
== 0 || src_height
== 0)
2453 blorp_params_init(¶ms
);
2454 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2455 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2456 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2457 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2459 struct brw_blorp_blit_prog_key wm_prog_key
= {
2460 .shader_type
= BLORP_SHADER_TYPE_BLIT
2463 const struct isl_format_layout
*src_fmtl
=
2464 isl_format_get_layout(params
.src
.surf
.format
);
2465 const struct isl_format_layout
*dst_fmtl
=
2466 isl_format_get_layout(params
.dst
.surf
.format
);
2468 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2469 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2470 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2471 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2472 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2473 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2475 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2476 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2477 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2478 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2479 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2480 params
.src
.view
.format
= params
.dst
.view
.format
;
2482 params
.src
.view
.format
=
2483 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2485 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2486 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2487 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2488 params
.dst
.view
.format
= params
.src
.view
.format
;
2490 params
.dst
.view
.format
=
2491 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2494 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2495 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2498 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2499 /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
2500 * enabled even though CCS_E doesn't technically do sRGB on SKL because
2501 * we stomp everything to UINT anyway. The one thing we have to be
2502 * careful of is clear colors. Because fast clear colors for sRGB on
2503 * gen9 are encoded as the float values between format conversion and
2504 * sRGB curve application, a given clear color float will convert to the
2505 * same bits regardless of whether the format is UNORM or sRGB.
2506 * Therefore, we can handle sRGB without any special cases.
2508 UNUSED
enum isl_format linear_src_format
=
2509 isl_format_srgb_to_linear(src_surf
->surf
->format
);
2510 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2512 params
.src
.view
.format
));
2513 params
.src
.clear_color
=
2514 bitcast_color_value_to_uint(params
.src
.clear_color
, src_fmtl
);
2517 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2518 /* See above where we handle linear_src_format */
2519 UNUSED
enum isl_format linear_dst_format
=
2520 isl_format_srgb_to_linear(dst_surf
->surf
->format
);
2521 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2523 params
.dst
.view
.format
));
2524 params
.dst
.clear_color
=
2525 bitcast_color_value_to_uint(params
.dst
.clear_color
, dst_fmtl
);
2528 wm_prog_key
.src_bpc
=
2529 isl_format_get_layout(params
.src
.view
.format
)->channels
.r
.bits
;
2530 wm_prog_key
.dst_bpc
=
2531 isl_format_get_layout(params
.dst
.view
.format
)->channels
.r
.bits
;
2533 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2534 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2536 &src_width
, &src_height
);
2537 wm_prog_key
.need_src_offset
= true;
2540 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2541 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2542 &dst_x
, &dst_y
, NULL
, NULL
);
2543 wm_prog_key
.need_dst_offset
= true;
2546 /* Once both surfaces are stompped to uncompressed as needed, the
2547 * destination size is the same as the source size.
2549 uint32_t dst_width
= src_width
;
2550 uint32_t dst_height
= src_height
;
2552 struct blt_coords coords
= {
2555 .src1
= src_x
+ src_width
,
2557 .dst1
= dst_x
+ dst_width
,
2562 .src1
= src_y
+ src_height
,
2564 .dst1
= dst_y
+ dst_height
,
2569 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2572 static enum isl_format
2573 isl_format_for_size(unsigned size_B
)
2576 case 1: return ISL_FORMAT_R8_UINT
;
2577 case 2: return ISL_FORMAT_R8G8_UINT
;
2578 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
2579 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
2580 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
2582 unreachable("Not a power-of-two format size");
2587 * Returns the greatest common divisor of a and b that is a power of two.
2590 gcd_pow2_u64(uint64_t a
, uint64_t b
)
2592 assert(a
> 0 || b
> 0);
2594 unsigned a_log2
= ffsll(a
) - 1;
2595 unsigned b_log2
= ffsll(b
) - 1;
2597 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
2598 * case, the MIN2() will take the other one. If both are 0 then we will
2599 * hit the assert above.
2601 return 1 << MIN2(a_log2
, b_log2
);
2605 do_buffer_copy(struct blorp_batch
*batch
,
2606 struct blorp_address
*src
,
2607 struct blorp_address
*dst
,
2608 int width
, int height
, int block_size
)
2610 /* The actual format we pick doesn't matter as blorp will throw it away.
2611 * The only thing that actually matters is the size.
2613 enum isl_format format
= isl_format_for_size(block_size
);
2616 struct isl_surf surf
;
2617 ok
= isl_surf_init(batch
->blorp
->isl_dev
, &surf
,
2618 .dim
= ISL_SURF_DIM_2D
,
2626 .row_pitch
= width
* block_size
,
2627 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
2628 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
2629 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
2632 struct blorp_surf src_blorp_surf
= {
2637 struct blorp_surf dst_blorp_surf
= {
2642 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
2643 0, 0, 0, 0, width
, height
);
2647 blorp_buffer_copy(struct blorp_batch
*batch
,
2648 struct blorp_address src
,
2649 struct blorp_address dst
,
2652 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
2653 uint64_t copy_size
= size
;
2655 /* This is maximum possible width/height our HW can handle */
2656 uint64_t max_surface_dim
= 1 << (devinfo
->gen
>= 7 ? 14 : 13);
2658 /* First, we compute the biggest format that can be used with the
2659 * given offsets and size.
2662 bs
= gcd_pow2_u64(bs
, src
.offset
);
2663 bs
= gcd_pow2_u64(bs
, dst
.offset
);
2664 bs
= gcd_pow2_u64(bs
, size
);
2666 /* First, we make a bunch of max-sized copies */
2667 uint64_t max_copy_size
= max_surface_dim
* max_surface_dim
* bs
;
2668 while (copy_size
>= max_copy_size
) {
2669 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, max_surface_dim
, bs
);
2670 copy_size
-= max_copy_size
;
2671 src
.offset
+= max_copy_size
;
2672 dst
.offset
+= max_copy_size
;
2675 /* Now make a max-width copy */
2676 uint64_t height
= copy_size
/ (max_surface_dim
* bs
);
2677 assert(height
< max_surface_dim
);
2679 uint64_t rect_copy_size
= height
* max_surface_dim
* bs
;
2680 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, height
, bs
);
2681 copy_size
-= rect_copy_size
;
2682 src
.offset
+= rect_copy_size
;
2683 dst
.offset
+= rect_copy_size
;
2686 /* Finally, make a small copy to finish it off */
2687 if (copy_size
!= 0) {
2688 do_buffer_copy(batch
, &src
, &dst
, copy_size
/ bs
, 1, bs
);