2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "blorp_nir_builder.h"
25 #include "compiler/nir/nir_format_convert.h"
27 #include "blorp_priv.h"
29 #include "util/format_rgb9e5.h"
30 /* header-only include needed for _mesa_unorm_to_float and friends. */
31 #include "mesa/main/format_utils.h"
32 #include "util/u_math.h"
34 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 static const bool split_blorp_blit_debug
= false;
39 * Enum to specify the order of arguments in a sampler message
41 enum sampler_message_arg
43 SAMPLER_MESSAGE_ARG_U_FLOAT
,
44 SAMPLER_MESSAGE_ARG_V_FLOAT
,
45 SAMPLER_MESSAGE_ARG_U_INT
,
46 SAMPLER_MESSAGE_ARG_V_INT
,
47 SAMPLER_MESSAGE_ARG_R_INT
,
48 SAMPLER_MESSAGE_ARG_SI_INT
,
49 SAMPLER_MESSAGE_ARG_MCS_INT
,
50 SAMPLER_MESSAGE_ARG_ZERO_INT
,
53 struct brw_blorp_blit_vars
{
54 /* Input values from brw_blorp_wm_inputs */
55 nir_variable
*v_discard_rect
;
56 nir_variable
*v_rect_grid
;
57 nir_variable
*v_coord_transform
;
58 nir_variable
*v_src_z
;
59 nir_variable
*v_src_offset
;
60 nir_variable
*v_dst_offset
;
61 nir_variable
*v_src_inv_size
;
64 nir_variable
*frag_coord
;
67 nir_variable
*color_out
;
71 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
72 const struct brw_blorp_blit_prog_key
*key
)
74 #define LOAD_INPUT(name, type)\
75 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
77 LOAD_INPUT(discard_rect
, glsl_vec4_type())
78 LOAD_INPUT(rect_grid
, glsl_vec4_type())
79 LOAD_INPUT(coord_transform
, glsl_vec4_type())
80 LOAD_INPUT(src_z
, glsl_uint_type())
81 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
82 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
83 LOAD_INPUT(src_inv_size
, glsl_vector_type(GLSL_TYPE_FLOAT
, 2))
87 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
88 glsl_vec4_type(), "gl_FragCoord");
89 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
91 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
92 glsl_vec4_type(), "gl_FragColor");
93 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
97 blorp_blit_get_frag_coords(nir_builder
*b
,
98 const struct brw_blorp_blit_prog_key
*key
,
99 struct brw_blorp_blit_vars
*v
)
101 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_var(b
, v
->frag_coord
));
103 /* Account for destination surface intratile offset
105 * Transformation parameters giving translation from destination to source
106 * coordinates don't take into account possible intra-tile destination
107 * offset. Therefore it has to be first subtracted from the incoming
108 * coordinates. Vertices are set up based on coordinates containing the
111 if (key
->need_dst_offset
)
112 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
114 if (key
->persample_msaa_dispatch
) {
115 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
116 nir_load_sample_id(b
));
118 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
123 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
127 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
128 struct brw_blorp_blit_vars
*v
)
130 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
132 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
133 nir_channel(b
, coord_transform
, 3));
134 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
135 nir_channel(b
, coord_transform
, 2));
137 return nir_fadd(b
, nir_fmul(b
, src_pos
, mul
), offset
);
141 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
142 struct brw_blorp_blit_vars
*v
)
144 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
145 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
146 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
147 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
148 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
149 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
151 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
152 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
153 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
154 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
156 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
158 nir_intrinsic_instr
*discard
=
159 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
160 discard
->src
[0] = nir_src_for_ssa(oob
);
161 nir_builder_instr_insert(b
, &discard
->instr
);
164 static nir_tex_instr
*
165 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
166 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
167 nir_alu_type dst_type
)
169 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
173 tex
->dest_type
= dst_type
;
174 tex
->is_array
= false;
175 tex
->is_shadow
= false;
177 /* Blorp only has one texture and it's bound at unit 0 */
178 tex
->texture_index
= 0;
179 tex
->sampler_index
= 0;
181 /* To properly handle 3-D and 2-D array textures, we pull the Z component
182 * from an input. TODO: This is a bit magic; we should probably make this
183 * more explicit in the future.
185 assert(pos
->num_components
>= 2);
186 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
187 nir_load_var(b
, v
->v_src_z
));
189 tex
->src
[0].src_type
= nir_tex_src_coord
;
190 tex
->src
[0].src
= nir_src_for_ssa(pos
);
191 tex
->coord_components
= 3;
193 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
199 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
200 const struct brw_blorp_blit_prog_key
*key
, nir_ssa_def
*pos
)
202 if (key
->need_src_offset
)
203 pos
= nir_fadd(b
, pos
, nir_i2f32(b
, nir_load_var(b
, v
->v_src_offset
)));
205 /* If the sampler requires normalized coordinates, we need to compensate. */
206 if (key
->src_coords_normalized
)
207 pos
= nir_fmul(b
, pos
, nir_load_var(b
, v
->v_src_inv_size
));
210 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2,
211 key
->texture_data_type
);
213 assert(pos
->num_components
== 2);
214 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
215 tex
->src
[1].src_type
= nir_tex_src_lod
;
216 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
218 nir_builder_instr_insert(b
, &tex
->instr
);
220 return &tex
->dest
.ssa
;
224 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
225 nir_ssa_def
*pos
, nir_alu_type dst_type
)
228 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
230 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
231 tex
->src
[1].src_type
= nir_tex_src_lod
;
232 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
234 nir_builder_instr_insert(b
, &tex
->instr
);
236 return &tex
->dest
.ssa
;
240 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
241 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
244 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
245 mcs
!= NULL
? 3 : 2, dst_type
);
247 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
249 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
250 if (pos
->num_components
== 2) {
251 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
253 assert(pos
->num_components
== 3);
254 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
258 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
259 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
262 nir_builder_instr_insert(b
, &tex
->instr
);
264 return &tex
->dest
.ssa
;
268 blorp_blit_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
272 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
273 pos
, 1, nir_type_int
);
275 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
277 nir_builder_instr_insert(b
, &tex
->instr
);
279 return &tex
->dest
.ssa
;
283 * Emit code to compensate for the difference between Y and W tiling.
285 * This code modifies the X and Y coordinates according to the formula:
287 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
289 * (See brw_blorp_build_nir_shader).
291 static inline nir_ssa_def
*
292 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
294 assert(pos
->num_components
== 2);
295 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
296 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
298 /* Given X and Y coordinates that describe an address using Y tiling,
299 * translate to the X and Y coordinates that describe the same address
302 * If we break down the low order bits of X and Y, using a
303 * single letter to represent each low-order bit:
305 * X = A << 7 | 0bBCDEFGH
306 * Y = J << 5 | 0bKLMNP (1)
308 * Then we can apply the Y tiling formula to see the memory offset being
311 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
313 * If we apply the W detiling formula to this memory location, that the
314 * corresponding X' and Y' coordinates are:
316 * X' = A << 6 | 0bBCDPFH (3)
317 * Y' = J << 6 | 0bKLMNEG
319 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
320 * we need to make the following computation:
322 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
323 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
325 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
326 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
327 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
328 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
330 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
331 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
332 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
333 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
335 return nir_vec2(b
, x_W
, y_W
);
339 * Emit code to compensate for the difference between Y and W tiling.
341 * This code modifies the X and Y coordinates according to the formula:
343 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
345 * (See brw_blorp_build_nir_shader).
347 static inline nir_ssa_def
*
348 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
350 assert(pos
->num_components
== 2);
351 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
352 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
354 /* Applying the same logic as above, but in reverse, we obtain the
357 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
358 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
360 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
361 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
362 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
363 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
364 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
366 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
367 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
368 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
370 return nir_vec2(b
, x_Y
, y_Y
);
374 * Emit code to compensate for the difference between MSAA and non-MSAA
377 * This code modifies the X and Y coordinates according to the formula:
379 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
381 * (See brw_blorp_blit_program).
383 static inline nir_ssa_def
*
384 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
385 unsigned num_samples
, enum isl_msaa_layout layout
)
387 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
390 case ISL_MSAA_LAYOUT_NONE
:
391 assert(pos
->num_components
== 2);
393 case ISL_MSAA_LAYOUT_ARRAY
:
394 /* No translation needed */
396 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
397 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
398 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
399 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
400 nir_channel(b
, pos
, 2);
402 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
403 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
404 switch (num_samples
) {
407 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
408 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
411 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
412 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
413 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
415 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
416 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
417 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
418 if (num_samples
== 2) {
421 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
422 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
423 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
428 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
429 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
431 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
433 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
434 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
435 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
436 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
437 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
438 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
439 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
443 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
444 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
446 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
449 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
450 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
451 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
452 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
453 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
454 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
455 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
456 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
460 unreachable("Invalid number of samples for IMS layout");
463 return nir_vec2(b
, x_out
, y_out
);
467 unreachable("Invalid MSAA layout");
472 * Emit code to compensate for the difference between MSAA and non-MSAA
475 * This code modifies the X and Y coordinates according to the formula:
477 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
479 * (See brw_blorp_blit_program).
481 static inline nir_ssa_def
*
482 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
483 unsigned num_samples
, enum isl_msaa_layout layout
)
485 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
488 case ISL_MSAA_LAYOUT_NONE
:
489 /* No translation necessary, and S should already be zero. */
490 assert(pos
->num_components
== 2);
492 case ISL_MSAA_LAYOUT_ARRAY
:
493 /* No translation necessary. */
495 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
496 assert(pos
->num_components
== 2);
498 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
499 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
501 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
502 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
503 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
504 switch (num_samples
) {
507 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
508 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
509 * S = (X & 0b10) >> 1
511 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
512 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
513 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
514 * S = (Y & 0b10) | (X & 0b10) >> 1
516 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
517 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
518 if (num_samples
== 2) {
520 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
522 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
523 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
524 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
525 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
530 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
531 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
532 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
533 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
535 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
536 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
537 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
538 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
539 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
540 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
541 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
545 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
546 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
547 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
548 * S = (Y & 0b100) << 1 | (X & 0b100) |
549 * (Y & 0b10) | (X & 0b10) >> 1
551 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
552 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
553 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
554 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
555 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
556 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
557 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
558 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
562 unreachable("Invalid number of samples for IMS layout");
565 return nir_vec3(b
, x_out
, y_out
, s_out
);
569 unreachable("Invalid MSAA layout");
574 * Count the number of trailing 1 bits in the given value. For example:
576 * count_trailing_one_bits(0) == 0
577 * count_trailing_one_bits(7) == 3
578 * count_trailing_one_bits(11) == 2
580 static inline int count_trailing_one_bits(unsigned value
)
582 #ifdef HAVE___BUILTIN_CTZ
583 return __builtin_ctz(~value
);
585 return util_bitcount(value
& ~(value
+ 1));
590 blorp_nir_combine_samples(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
591 nir_ssa_def
*pos
, unsigned tex_samples
,
592 enum isl_aux_usage tex_aux_usage
,
593 nir_alu_type dst_type
,
594 enum blorp_filter filter
)
596 /* If non-null, this is the outer-most if statement */
597 nir_if
*outer_if
= NULL
;
599 nir_variable
*color
=
600 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
602 nir_ssa_def
*mcs
= NULL
;
603 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
604 mcs
= blorp_blit_txf_ms_mcs(b
, v
, pos
);
608 case BLORP_FILTER_AVERAGE
:
609 assert(dst_type
== nir_type_float
);
610 combine_op
= nir_op_fadd
;
613 case BLORP_FILTER_MIN_SAMPLE
:
615 case nir_type_int
: combine_op
= nir_op_imin
; break;
616 case nir_type_uint
: combine_op
= nir_op_umin
; break;
617 case nir_type_float
: combine_op
= nir_op_fmin
; break;
618 default: unreachable("Invalid dst_type");
622 case BLORP_FILTER_MAX_SAMPLE
:
624 case nir_type_int
: combine_op
= nir_op_imax
; break;
625 case nir_type_uint
: combine_op
= nir_op_umax
; break;
626 case nir_type_float
: combine_op
= nir_op_fmax
; break;
627 default: unreachable("Invalid dst_type");
632 unreachable("Invalid filter");
635 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
637 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
639 * This ensures that when all samples have the same value, no numerical
640 * precision is lost, since each addition operation always adds two equal
641 * values, and summing two equal floating point values does not lose
644 * We perform this computation by treating the texture_data array as a
645 * stack and performing the following operations:
647 * - push sample 0 onto stack
648 * - push sample 1 onto stack
649 * - add top two stack entries
650 * - push sample 2 onto stack
651 * - push sample 3 onto stack
652 * - add top two stack entries
653 * - add top two stack entries
654 * - divide top stack entry by 4
656 * Note that after pushing sample i onto the stack, the number of add
657 * operations we do is equal to the number of trailing 1 bits in i. This
658 * works provided the total number of samples is a power of two, which it
659 * always is for i965.
661 * For integer formats, we replace the add operations with average
662 * operations and skip the final division.
664 nir_ssa_def
*texture_data
[5];
665 unsigned stack_depth
= 0;
666 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
667 assert(stack_depth
== util_bitcount(i
)); /* Loop invariant */
669 /* Push sample i onto the stack */
670 assert(stack_depth
< ARRAY_SIZE(texture_data
));
672 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
673 nir_channel(b
, pos
, 1),
675 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
677 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
678 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
679 * suggests an optimization:
681 * "A simple optimization with probable large return in
682 * performance is to compare the MCS value to zero (indicating
683 * all samples are on sample slice 0), and sample only from
684 * sample slice 0 using ld2dss if MCS is zero."
686 * Note that in the case where the MCS value is zero, sampling from
687 * sample slice 0 using ld2dss and sampling from sample 0 using
688 * ld2dms are equivalent (since all samples are on sample slice 0).
689 * Since we have already sampled from sample 0, all we need to do is
690 * skip the remaining fetches and averaging if MCS is zero.
692 * It's also trivial to detect when the MCS has the magic clear color
693 * value. In this case, the txf we did on sample 0 will return the
694 * clear color and we can skip the remaining fetches just like we do
697 nir_ssa_def
*mcs_zero
=
698 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
699 if (tex_samples
== 16) {
700 mcs_zero
= nir_iand(b
, mcs_zero
,
701 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
703 nir_ssa_def
*mcs_clear
=
704 blorp_nir_mcs_is_clear_color(b
, mcs
, tex_samples
);
706 nir_if
*if_stmt
= nir_if_create(b
->shader
);
707 if_stmt
->condition
= nir_src_for_ssa(nir_ior(b
, mcs_zero
, mcs_clear
));
708 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
710 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
711 nir_store_var(b
, color
, texture_data
[0], 0xf);
713 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
717 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
718 assert(stack_depth
>= 2);
721 texture_data
[stack_depth
- 1] =
722 nir_build_alu(b
, combine_op
,
723 texture_data
[stack_depth
- 1],
724 texture_data
[stack_depth
],
729 /* We should have just 1 sample on the stack now. */
730 assert(stack_depth
== 1);
732 if (filter
== BLORP_FILTER_AVERAGE
) {
733 assert(dst_type
== nir_type_float
);
734 texture_data
[0] = nir_fmul(b
, texture_data
[0],
735 nir_imm_float(b
, 1.0 / tex_samples
));
738 nir_store_var(b
, color
, texture_data
[0], 0xf);
741 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
743 return nir_load_var(b
, color
);
746 static inline nir_ssa_def
*
747 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
751 memset(&v
, 0, sizeof(v
));
755 return nir_build_imm(build
, 4, 32, v
);
759 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
760 unsigned tex_samples
,
761 const struct brw_blorp_blit_prog_key
*key
,
762 struct brw_blorp_blit_vars
*v
)
764 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
765 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
766 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
768 /* Translate coordinates to lay out the samples in a rectangular grid
769 * roughly corresponding to sample locations.
771 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
772 /* Adjust coordinates so that integers represent pixel centers rather
775 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
776 /* Clamp the X, Y texture coordinates to properly handle the sampling of
777 * texels on texture edges.
779 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
780 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
781 nir_channel(b
, rect_grid
, 1)));
783 /* Store the fractional parts to be used as bilinear interpolation
786 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
787 /* Round the float coordinates down to nearest integer */
788 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
790 nir_ssa_def
*tex_data
[4];
791 for (unsigned i
= 0; i
< 4; ++i
) {
792 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
793 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
794 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
796 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
797 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
799 /* The MCS value we fetch has to match up with the pixel that we're
800 * sampling from. Since we sample from different pixels in each
801 * iteration of this "for" loop, the call to mcs_fetch() should be
802 * here inside the loop after computing the pixel coordinates.
804 nir_ssa_def
*mcs
= NULL
;
805 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
806 mcs
= blorp_blit_txf_ms_mcs(b
, v
, sample_coords_int
);
808 /* Compute sample index and map the sample index to a sample number.
809 * Sample index layout shows the numbering of slots in a rectangular
810 * grid of samples with in a pixel. Sample number layout shows the
811 * rectangular grid of samples roughly corresponding to the real sample
812 * locations with in a pixel.
814 * In the case of 2x MSAA, the layout of sample indices is reversed from
815 * the layout of sample numbers:
817 * sample index layout : --------- sample number layout : ---------
818 * | 0 | 1 | | 1 | 0 |
819 * --------- ---------
821 * In case of 4x MSAA, layout of sample indices matches the layout of
829 * In case of 8x MSAA the two layouts don't match.
830 * sample index layout : --------- sample number layout : ---------
831 * | 0 | 1 | | 3 | 7 |
832 * --------- ---------
833 * | 2 | 3 | | 5 | 0 |
834 * --------- ---------
835 * | 4 | 5 | | 1 | 2 |
836 * --------- ---------
837 * | 6 | 7 | | 4 | 6 |
838 * --------- ---------
840 * Fortunately, this can be done fairly easily as:
841 * S' = (0x17306425 >> (S * 4)) & 0xf
843 * In the case of 16x MSAA the two layouts don't match.
844 * Sample index layout: Sample number layout:
845 * --------------------- ---------------------
846 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
847 * --------------------- ---------------------
848 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
849 * --------------------- ---------------------
850 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
851 * --------------------- ---------------------
852 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
853 * --------------------- ---------------------
855 * This is equivalent to
856 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
858 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
859 nir_ssa_def
*sample
=
860 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
861 key
->x_scale
* key
->y_scale
));
862 sample
= nir_f2i32(b
, sample
);
864 if (tex_samples
== 2) {
865 sample
= nir_isub(b
, nir_imm_int(b
, 1), sample
);
866 } else if (tex_samples
== 8) {
867 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
868 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
869 nir_imm_int(b
, 0xf));
870 } else if (tex_samples
== 16) {
871 nir_ssa_def
*sample_low
=
872 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
873 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
874 nir_imm_int(b
, 0xf));
875 nir_ssa_def
*sample_high
=
876 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
877 nir_ishl(b
, nir_iadd(b
, sample
,
880 nir_imm_int(b
, 0xf));
882 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
883 sample_low
, sample_high
);
885 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
886 nir_channel(b
, sample_coords_int
, 1),
888 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
891 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
892 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
893 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
894 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
898 /** Perform a color bit-cast operation
900 * For copy operations involving CCS, we may need to use different formats for
901 * the source and destination surfaces. The two formats must both be UINT
902 * formats and must have the same size but may have different bit layouts.
903 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
904 * to R16G16_UINT. This function generates code to shuffle bits around to get
905 * us from one to the other.
908 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
909 const struct brw_blorp_blit_prog_key
*key
)
911 assert(key
->texture_data_type
== nir_type_uint
);
913 if (key
->src_format
== key
->dst_format
)
916 const struct isl_format_layout
*src_fmtl
=
917 isl_format_get_layout(key
->src_format
);
918 const struct isl_format_layout
*dst_fmtl
=
919 isl_format_get_layout(key
->dst_format
);
921 /* They must be uint formats with the same bit size */
922 assert(src_fmtl
->bpb
== dst_fmtl
->bpb
);
923 assert(src_fmtl
->channels
.r
.type
== ISL_UINT
);
924 assert(dst_fmtl
->channels
.r
.type
== ISL_UINT
);
926 /* They must be in regular color formats (no luminance or alpha) */
927 assert(src_fmtl
->channels
.r
.bits
> 0);
928 assert(dst_fmtl
->channels
.r
.bits
> 0);
930 /* They must be in RGBA order (possibly with channels missing) */
931 assert(src_fmtl
->channels
.r
.start_bit
== 0);
932 assert(dst_fmtl
->channels
.r
.start_bit
== 0);
934 if (src_fmtl
->bpb
<= 32) {
935 const unsigned src_channels
=
936 isl_format_get_num_channels(key
->src_format
);
937 const unsigned src_bits
[4] = {
938 src_fmtl
->channels
.r
.bits
,
939 src_fmtl
->channels
.g
.bits
,
940 src_fmtl
->channels
.b
.bits
,
941 src_fmtl
->channels
.a
.bits
,
943 const unsigned dst_channels
=
944 isl_format_get_num_channels(key
->dst_format
);
945 const unsigned dst_bits
[4] = {
946 dst_fmtl
->channels
.r
.bits
,
947 dst_fmtl
->channels
.g
.bits
,
948 dst_fmtl
->channels
.b
.bits
,
949 dst_fmtl
->channels
.a
.bits
,
951 nir_ssa_def
*packed
=
952 nir_format_pack_uint_unmasked(b
, color
, src_bits
, src_channels
);
953 color
= nir_format_unpack_uint(b
, packed
, dst_bits
, dst_channels
);
955 const unsigned src_bpc
= src_fmtl
->channels
.r
.bits
;
956 const unsigned dst_bpc
= dst_fmtl
->channels
.r
.bits
;
958 assert(src_fmtl
->channels
.g
.bits
== 0 ||
959 src_fmtl
->channels
.g
.bits
== src_fmtl
->channels
.r
.bits
);
960 assert(src_fmtl
->channels
.b
.bits
== 0 ||
961 src_fmtl
->channels
.b
.bits
== src_fmtl
->channels
.r
.bits
);
962 assert(src_fmtl
->channels
.a
.bits
== 0 ||
963 src_fmtl
->channels
.a
.bits
== src_fmtl
->channels
.r
.bits
);
964 assert(dst_fmtl
->channels
.g
.bits
== 0 ||
965 dst_fmtl
->channels
.g
.bits
== dst_fmtl
->channels
.r
.bits
);
966 assert(dst_fmtl
->channels
.b
.bits
== 0 ||
967 dst_fmtl
->channels
.b
.bits
== dst_fmtl
->channels
.r
.bits
);
968 assert(dst_fmtl
->channels
.a
.bits
== 0 ||
969 dst_fmtl
->channels
.a
.bits
== dst_fmtl
->channels
.r
.bits
);
971 /* Restrict to only the channels we actually have */
972 const unsigned src_channels
=
973 isl_format_get_num_channels(key
->src_format
);
974 color
= nir_channels(b
, color
, (1 << src_channels
) - 1);
976 color
= nir_format_bitcast_uvec_unmasked(b
, color
, src_bpc
, dst_bpc
);
979 /* Blorp likes to assume that colors are vec4s */
980 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
981 nir_ssa_def
*chans
[4] = { u
, u
, u
, u
};
982 for (unsigned i
= 0; i
< color
->num_components
; i
++)
983 chans
[i
] = nir_channel(b
, color
, i
);
984 return nir_vec4(b
, chans
[0], chans
[1], chans
[2], chans
[3]);
988 select_color_channel(struct nir_builder
*b
, nir_ssa_def
*color
,
989 nir_alu_type data_type
,
990 enum isl_channel_select chan
)
992 if (chan
== ISL_CHANNEL_SELECT_ZERO
) {
993 return nir_imm_int(b
, 0);
994 } else if (chan
== ISL_CHANNEL_SELECT_ONE
) {
998 return nir_imm_int(b
, 1);
1000 return nir_imm_float(b
, 1);
1002 unreachable("Invalid data type");
1005 assert((unsigned)(chan
- ISL_CHANNEL_SELECT_RED
) < 4);
1006 return nir_channel(b
, color
, chan
- ISL_CHANNEL_SELECT_RED
);
1010 static nir_ssa_def
*
1011 swizzle_color(struct nir_builder
*b
, nir_ssa_def
*color
,
1012 struct isl_swizzle swizzle
, nir_alu_type data_type
)
1015 select_color_channel(b
, color
, data_type
, swizzle
.r
),
1016 select_color_channel(b
, color
, data_type
, swizzle
.g
),
1017 select_color_channel(b
, color
, data_type
, swizzle
.b
),
1018 select_color_channel(b
, color
, data_type
, swizzle
.a
));
1021 static nir_ssa_def
*
1022 convert_color(struct nir_builder
*b
, nir_ssa_def
*color
,
1023 const struct brw_blorp_blit_prog_key
*key
)
1025 /* All of our color conversions end up generating a single-channel color
1026 * value that we need to write out.
1030 if (key
->dst_format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
1031 /* The destination image is bound as R32_UINT but the data needs to be
1032 * in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and the
1033 * top 8 need to be zero. We can accomplish this by simply multiplying
1034 * by a factor to scale things down.
1036 unsigned factor
= (1 << 24) - 1;
1037 value
= nir_fsat(b
, nir_channel(b
, color
, 0));
1038 value
= nir_f2i32(b
, nir_fmul(b
, value
, nir_imm_float(b
, factor
)));
1039 } else if (key
->dst_format
== ISL_FORMAT_L8_UNORM_SRGB
) {
1040 value
= nir_format_linear_to_srgb(b
, nir_channel(b
, color
, 0));
1041 } else if (key
->dst_format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
) {
1042 value
= nir_format_linear_to_srgb(b
, color
);
1043 } else if (key
->dst_format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
1044 value
= nir_format_pack_r9g9b9e5(b
, color
);
1046 unreachable("Unsupported format conversion");
1049 nir_ssa_def
*out_comps
[4];
1050 for (unsigned i
= 0; i
< 4; i
++) {
1051 if (i
< value
->num_components
)
1052 out_comps
[i
] = nir_channel(b
, value
, i
);
1054 out_comps
[i
] = nir_ssa_undef(b
, 1, 32);
1056 return nir_vec(b
, out_comps
, 4);
1060 * Generator for WM programs used in BLORP blits.
1062 * The bulk of the work done by the WM program is to wrap and unwrap the
1063 * coordinate transformations used by the hardware to store surfaces in
1064 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
1065 * sample index for a multisampled surface) to a memory offset by the
1066 * following formulas:
1068 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
1069 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
1071 * For a single-sampled surface, or for a multisampled surface using
1072 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
1075 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1076 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1077 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1078 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1080 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1081 * embeds the sample number into bit 1 of the X and Y coordinates:
1083 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1084 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1085 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
1086 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1087 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1088 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1089 * S = (Y & 0b10) | (X & 0b10) >> 1
1091 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1092 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
1095 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1096 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
1097 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1098 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1099 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1100 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1101 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1103 * For X tiling, tile() combines together the low-order bits of the X and Y
1104 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
1105 * bytes wide and 8 rows high:
1107 * tile(x_tiled, X, Y, S) = A
1108 * where A = tile_num << 12 | offset
1109 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
1110 * offset = (Y' & 0b111) << 9
1111 * | (X & 0b111111111)
1113 * Y' = Y + S * qpitch
1114 * detile(x_tiled, A) = (X, Y, S)
1115 * where X = X' / cpp
1118 * Y' = (tile_num / tile_pitch) << 3
1119 * | (A & 0b111000000000) >> 9
1120 * X' = (tile_num % tile_pitch) << 9
1121 * | (A & 0b111111111)
1123 * (In all tiling formulas, cpp is the number of bytes occupied by a single
1124 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
1125 * to fill the width of the surface, and qpitch is the spacing (in rows)
1126 * between array slices).
1128 * For Y tiling, tile() combines together the low-order bits of the X and Y
1129 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
1130 * bytes wide and 32 rows high:
1132 * tile(y_tiled, X, Y, S) = A
1133 * where A = tile_num << 12 | offset
1134 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
1135 * offset = (X' & 0b1110000) << 5
1136 * | (Y' & 0b11111) << 4
1139 * Y' = Y + S * qpitch
1140 * detile(y_tiled, A) = (X, Y, S)
1141 * where X = X' / cpp
1144 * Y' = (tile_num / tile_pitch) << 5
1145 * | (A & 0b111110000) >> 4
1146 * X' = (tile_num % tile_pitch) << 7
1147 * | (A & 0b111000000000) >> 5
1150 * For W tiling, tile() combines together the low-order bits of the X and Y
1151 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1152 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1153 * buffers, which always have cpp = 1 and S=0):
1155 * tile(w_tiled, X, Y, S) = A
1156 * where A = tile_num << 12 | offset
1157 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1158 * offset = (X' & 0b111000) << 6
1159 * | (Y' & 0b111100) << 3
1160 * | (X' & 0b100) << 2
1161 * | (Y' & 0b10) << 2
1162 * | (X' & 0b10) << 1
1166 * Y' = Y + S * qpitch
1167 * detile(w_tiled, A) = (X, Y, S)
1168 * where X = X' / cpp = X'
1169 * Y = Y' % qpitch = Y'
1170 * S = Y / qpitch = 0
1171 * Y' = (tile_num / tile_pitch) << 6
1172 * | (A & 0b111100000) >> 3
1173 * | (A & 0b1000) >> 2
1175 * X' = (tile_num % tile_pitch) << 6
1176 * | (A & 0b111000000000) >> 6
1177 * | (A & 0b10000) >> 2
1178 * | (A & 0b100) >> 1
1181 * Finally, for a non-tiled surface, tile() simply combines together the X and
1182 * Y coordinates in the natural way:
1184 * tile(untiled, X, Y, S) = A
1185 * where A = Y * pitch + X'
1187 * Y' = Y + S * qpitch
1188 * detile(untiled, A) = (X, Y, S)
1189 * where X = X' / cpp
1195 * (In these formulas, pitch is the number of bytes occupied by a single row
1199 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1200 const struct brw_blorp_blit_prog_key
*key
)
1202 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1203 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1206 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1207 /* If the destination image is W tiled and multisampled, then the thread
1208 * must be dispatched once per sample, not once per pixel. This is
1209 * necessary because after conversion between W and Y tiling, there's no
1210 * guarantee that all samples corresponding to a single pixel will still
1213 assert(key
->persample_msaa_dispatch
);
1216 if (key
->persample_msaa_dispatch
) {
1217 /* It only makes sense to do persample dispatch if the render target is
1218 * configured as multisampled.
1220 assert(key
->rt_samples
> 0);
1223 /* Make sure layout is consistent with sample count */
1224 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1225 (key
->tex_samples
<= 1));
1226 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1227 (key
->rt_samples
<= 1));
1228 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1229 (key
->src_samples
<= 1));
1230 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1231 (key
->dst_samples
<= 1));
1234 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1236 struct brw_blorp_blit_vars v
;
1237 brw_blorp_blit_vars_init(&b
, &v
, key
);
1239 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1241 /* Render target and texture hardware don't support W tiling until Gen8. */
1242 const bool rt_tiled_w
= false;
1243 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1245 /* The address that data will be written to is determined by the
1246 * coordinates supplied to the WM thread and the tiling and sample count of
1247 * the render target, according to the formula:
1249 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1251 * If the actual tiling and sample count of the destination surface are not
1252 * the same as the configuration of the render target, then these
1253 * coordinates are wrong and we have to adjust them to compensate for the
1256 if (rt_tiled_w
!= key
->dst_tiled_w
||
1257 key
->rt_samples
!= key
->dst_samples
||
1258 key
->rt_layout
!= key
->dst_layout
) {
1259 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1261 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1262 if (rt_tiled_w
!= key
->dst_tiled_w
)
1263 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1264 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1265 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1269 nir_ssa_def
*comp
= NULL
;
1271 /* The destination image is bound as a red texture three times as wide
1272 * as the actual image. Our shader is effectively running one color
1273 * component at a time. We need to save off the component and adjust
1274 * the destination position.
1276 assert(dst_pos
->num_components
== 2);
1277 nir_ssa_def
*dst_x
= nir_channel(&b
, dst_pos
, 0);
1278 comp
= nir_umod(&b
, dst_x
, nir_imm_int(&b
, 3));
1279 dst_pos
= nir_vec2(&b
, nir_idiv(&b
, dst_x
, nir_imm_int(&b
, 3)),
1280 nir_channel(&b
, dst_pos
, 1));
1283 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1285 * That is: X, Y and S now contain the true coordinates and sample index of
1286 * the data that the WM thread should output.
1288 * If we need to kill pixels that are outside the destination rectangle,
1289 * now is the time to do it.
1292 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1294 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1295 if (dst_pos
->num_components
== 3) {
1296 /* The sample coordinate is an integer that we want left alone but
1297 * blorp_blit_apply_transform() blindly applies the transform to all
1298 * three coordinates. Grab the original sample index.
1300 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1301 nir_channel(&b
, src_pos
, 1),
1302 nir_channel(&b
, dst_pos
, 2));
1305 /* If the source image is not multisampled, then we want to fetch sample
1306 * number 0, because that's the only sample there is.
1308 if (key
->src_samples
== 1)
1309 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1311 /* X, Y, and S are now the coordinates of the pixel in the source image
1312 * that we want to texture from. Exception: if we are blending, then S is
1313 * irrelevant, because we are going to fetch all samples.
1315 switch (key
->filter
) {
1316 case BLORP_FILTER_NONE
:
1317 case BLORP_FILTER_NEAREST
:
1318 case BLORP_FILTER_SAMPLE_0
:
1319 /* We're going to use texelFetch, so we need integers */
1320 if (src_pos
->num_components
== 2) {
1321 src_pos
= nir_f2i32(&b
, src_pos
);
1323 assert(src_pos
->num_components
== 3);
1324 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1325 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1326 nir_channel(&b
, src_pos
, 2));
1329 /* We aren't blending, which means we just want to fetch a single
1330 * sample from the source surface. The address that we want to fetch
1331 * from is related to the X, Y and S values according to the formula:
1333 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1335 * If the actual tiling and sample count of the source surface are
1336 * not the same as the configuration of the texture, then we need to
1337 * adjust the coordinates to compensate for the difference.
1339 if (tex_tiled_w
!= key
->src_tiled_w
||
1340 key
->tex_samples
!= key
->src_samples
||
1341 key
->tex_layout
!= key
->src_layout
) {
1342 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1344 /* Now (X, Y, S) = detile(src_tiling, offset) */
1345 if (tex_tiled_w
!= key
->src_tiled_w
)
1346 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1347 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1348 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1352 if (key
->need_src_offset
)
1353 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1355 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1357 * In other words: X, Y, and S now contain values which, when passed to
1358 * the texturing unit, will cause data to be read from the correct
1359 * memory location. So we can fetch the texel now.
1361 if (key
->src_samples
== 1) {
1362 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1364 nir_ssa_def
*mcs
= NULL
;
1365 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1366 mcs
= blorp_blit_txf_ms_mcs(&b
, &v
, src_pos
);
1368 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1372 case BLORP_FILTER_BILINEAR
:
1373 assert(!key
->src_tiled_w
);
1374 assert(key
->tex_samples
== key
->src_samples
);
1375 assert(key
->tex_layout
== key
->src_layout
);
1377 if (key
->src_samples
== 1) {
1378 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1380 assert(!key
->use_kill
);
1381 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
,
1386 case BLORP_FILTER_AVERAGE
:
1387 case BLORP_FILTER_MIN_SAMPLE
:
1388 case BLORP_FILTER_MAX_SAMPLE
:
1389 assert(!key
->src_tiled_w
);
1390 assert(key
->tex_samples
== key
->src_samples
);
1391 assert(key
->tex_layout
== key
->src_layout
);
1393 /* Resolves (effecively) use texelFetch, so we need integers and we
1394 * don't care about the sample index if we got one.
1396 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1398 if (devinfo
->gen
== 6) {
1399 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1400 * blending we need with a single linear-interpolated texture lookup
1401 * at the center of the sample. The texture coordinates to be odd
1402 * integers so that they correspond to the center of a 2x2 block
1403 * representing the four samples that maxe up a pixel. So we need
1404 * to multiply our X and Y coordinates each by 2 and then add 1.
1406 assert(key
->src_coords_normalized
);
1407 assert(key
->filter
== BLORP_FILTER_AVERAGE
);
1408 src_pos
= nir_fadd(&b
,
1409 nir_i2f32(&b
, src_pos
),
1410 nir_imm_float(&b
, 0.5f
));
1411 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1413 /* Gen7+ hardware doesn't automaticaly blend. */
1414 color
= blorp_nir_combine_samples(&b
, &v
, src_pos
, key
->src_samples
,
1416 key
->texture_data_type
,
1422 unreachable("Invalid blorp filter");
1425 if (!isl_swizzle_is_identity(key
->src_swizzle
)) {
1426 color
= swizzle_color(&b
, color
, key
->src_swizzle
,
1427 key
->texture_data_type
);
1430 if (!isl_swizzle_is_identity(key
->dst_swizzle
)) {
1431 color
= swizzle_color(&b
, color
, isl_swizzle_invert(key
->dst_swizzle
),
1435 if (key
->format_bit_cast
) {
1436 assert(isl_swizzle_is_identity(key
->src_swizzle
));
1437 assert(isl_swizzle_is_identity(key
->dst_swizzle
));
1438 color
= bit_cast_color(&b
, color
, key
);
1439 } else if (key
->dst_format
) {
1440 color
= convert_color(&b
, color
, key
);
1444 /* The destination image is bound as a red texture three times as wide
1445 * as the actual image. Our shader is effectively running one color
1446 * component at a time. We need to pick off the appropriate component
1447 * from the source color and write that to destination red.
1449 assert(dst_pos
->num_components
== 2);
1451 nir_ssa_def
*color_component
=
1452 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1453 nir_channel(&b
, color
, 0),
1454 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1455 nir_channel(&b
, color
, 1),
1456 nir_channel(&b
, color
, 2)));
1458 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1459 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1462 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1468 brw_blorp_get_blit_kernel(struct blorp_batch
*batch
,
1469 struct blorp_params
*params
,
1470 const struct brw_blorp_blit_prog_key
*prog_key
)
1472 struct blorp_context
*blorp
= batch
->blorp
;
1474 if (blorp
->lookup_shader(batch
, prog_key
, sizeof(*prog_key
),
1475 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1478 void *mem_ctx
= ralloc_context(NULL
);
1480 const unsigned *program
;
1481 struct brw_wm_prog_data prog_data
;
1483 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1484 nir
->info
.name
= ralloc_strdup(nir
, "BLORP-blit");
1486 struct brw_wm_prog_key wm_key
;
1487 brw_blorp_init_wm_prog_key(&wm_key
);
1488 wm_key
.tex
.compressed_multisample_layout_mask
=
1489 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1490 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1491 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1493 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1497 blorp
->upload_shader(batch
, prog_key
, sizeof(*prog_key
),
1498 program
, prog_data
.base
.program_size
,
1499 &prog_data
.base
, sizeof(prog_data
),
1500 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1502 ralloc_free(mem_ctx
);
1507 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1508 GLfloat src0
, GLfloat src1
,
1509 GLfloat dst0
, GLfloat dst1
,
1512 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1514 /* When not mirroring a coordinate (say, X), we need:
1515 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1517 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1519 * blorp program uses "round toward zero" to convert the
1520 * transformed floating point coordinates to integer coordinates,
1521 * whereas the behaviour we actually want is "round to nearest",
1522 * so 0.5 provides the necessary correction.
1524 xform
->multiplier
= scale
;
1525 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1527 /* When mirroring X we need:
1528 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1530 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1532 xform
->multiplier
= -scale
;
1533 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1538 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1539 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1541 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1542 struct isl_extent2d px_size_sa
=
1543 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1544 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1545 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1546 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1547 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1549 *tile_x_px
= info
->tile_x_sa
;
1550 *tile_y_px
= info
->tile_y_sa
;
1555 blorp_surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1556 struct brw_blorp_surface_info
*info
)
1560 /* It would be insane to try and do this on a compressed surface */
1561 assert(info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1563 /* Just bail if we have nothing to do. */
1564 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1565 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1566 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1569 /* If this gets triggered then we've gotten here twice which. This
1570 * shouldn't happen thanks to the above early return.
1572 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1574 uint32_t layer
= 0, z
= 0;
1575 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1576 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1578 layer
= info
->view
.base_array_layer
;
1580 uint32_t byte_offset
;
1581 isl_surf_get_image_surf(isl_dev
, &info
->surf
,
1582 info
->view
.base_level
, layer
, z
,
1584 &byte_offset
, &info
->tile_x_sa
, &info
->tile_y_sa
);
1585 info
->addr
.offset
+= byte_offset
;
1587 uint32_t tile_x_px
, tile_y_px
;
1588 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1590 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we place
1591 * the image at the tile boundary and offset our sampling or rendering.
1592 * For this reason, we need to grow the image by the offset to ensure that
1593 * the hardware doesn't think we've gone past the edge.
1595 info
->surf
.logical_level0_px
.w
+= tile_x_px
;
1596 info
->surf
.logical_level0_px
.h
+= tile_y_px
;
1597 info
->surf
.phys_level0_sa
.w
+= info
->tile_x_sa
;
1598 info
->surf
.phys_level0_sa
.h
+= info
->tile_y_sa
;
1600 /* The view is also different now. */
1601 info
->view
.base_level
= 0;
1602 info
->view
.levels
= 1;
1603 info
->view
.base_array_layer
= 0;
1604 info
->view
.array_len
= 1;
1609 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1610 struct brw_blorp_surface_info
*info
)
1612 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1614 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1615 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1617 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1618 info
->surf
.samples
= 1;
1619 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1623 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1624 struct brw_blorp_surface_info
*info
)
1626 assert(info
->surf
.tiling
== ISL_TILING_W
);
1628 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1629 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1631 /* On gen7+, we don't have interleaved multisampling for color render
1632 * targets so we have to fake it.
1634 * TODO: Are we sure we don't also need to fake it on gen6?
1636 if (isl_dev
->info
->gen
> 6 &&
1637 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1638 surf_fake_interleaved_msaa(isl_dev
, info
);
1641 if (isl_dev
->info
->gen
== 6) {
1642 /* Gen6 stencil buffers have a very large alignment coming in from the
1643 * miptree. It's out-of-bounds for what the surface state can handle.
1644 * Since we have a single layer and level, it doesn't really matter as
1645 * long as we don't pass a bogus value into isl_surf_fill_state().
1647 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1650 /* Now that we've converted everything to a simple 2-D surface with only
1651 * one miplevel, we can go about retiling it.
1653 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1654 info
->surf
.tiling
= ISL_TILING_Y0
;
1655 info
->surf
.logical_level0_px
.width
=
1656 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1657 info
->surf
.logical_level0_px
.height
=
1658 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1659 info
->tile_x_sa
*= 2;
1660 info
->tile_y_sa
/= 2;
1664 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1666 /* The current code doesn't support offsets into the aux buffers. This
1667 * should be possible, but we need to make sure the offset is page
1668 * aligned for both the surface and the aux buffer surface. Generally
1669 * this mean using the page aligned offset for the aux buffer.
1671 * Currently the cases where we must split the blit are limited to cases
1672 * where we don't have a aux buffer.
1674 if (surf
->aux_addr
.buffer
!= NULL
)
1677 /* We can't support splitting the blit for gen <= 7, because the qpitch
1678 * size is calculated by the hardware based on the surface height for
1679 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1681 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1688 can_shrink_surfaces(const struct blorp_params
*params
)
1691 can_shrink_surface(¶ms
->src
) &&
1692 can_shrink_surface(¶ms
->dst
);
1696 get_max_surface_size(const struct gen_device_info
*devinfo
,
1697 const struct blorp_params
*params
)
1699 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1700 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1701 return max
>> 4; /* A smaller restriction when debug is enabled */
1707 double src0
, src1
, dst0
, dst1
;
1712 struct blt_axis x
, y
;
1715 static enum isl_format
1716 get_red_format_for_rgb_format(enum isl_format format
)
1718 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1720 switch (fmtl
->channels
.r
.bits
) {
1722 switch (fmtl
->channels
.r
.type
) {
1724 return ISL_FORMAT_R8_UNORM
;
1726 return ISL_FORMAT_R8_SNORM
;
1728 return ISL_FORMAT_R8_UINT
;
1730 return ISL_FORMAT_R8_SINT
;
1732 unreachable("Invalid 8-bit RGB channel type");
1735 switch (fmtl
->channels
.r
.type
) {
1737 return ISL_FORMAT_R16_UNORM
;
1739 return ISL_FORMAT_R16_SNORM
;
1741 return ISL_FORMAT_R16_FLOAT
;
1743 return ISL_FORMAT_R16_UINT
;
1745 return ISL_FORMAT_R16_SINT
;
1747 unreachable("Invalid 8-bit RGB channel type");
1750 switch (fmtl
->channels
.r
.type
) {
1752 return ISL_FORMAT_R32_FLOAT
;
1754 return ISL_FORMAT_R32_UINT
;
1756 return ISL_FORMAT_R32_SINT
;
1758 unreachable("Invalid 8-bit RGB channel type");
1761 unreachable("Invalid number of red channel bits");
1766 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1767 struct brw_blorp_surface_info
*info
)
1769 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1771 info
->surf
.logical_level0_px
.width
*= 3;
1772 info
->surf
.phys_level0_sa
.width
*= 3;
1773 info
->tile_x_sa
*= 3;
1775 enum isl_format red_format
=
1776 get_red_format_for_rgb_format(info
->view
.format
);
1778 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1779 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1780 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1781 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1783 info
->surf
.format
= info
->view
.format
= red_format
;
1786 enum blit_shrink_status
{
1788 BLIT_WIDTH_SHRINK
= 1,
1789 BLIT_HEIGHT_SHRINK
= 2,
1792 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1793 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1794 * returned, then the blit was successful.
1796 static enum blit_shrink_status
1797 try_blorp_blit(struct blorp_batch
*batch
,
1798 struct blorp_params
*params
,
1799 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1800 struct blt_coords
*coords
)
1802 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1804 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1805 wm_prog_key
->texture_data_type
= nir_type_int
;
1806 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1807 wm_prog_key
->texture_data_type
= nir_type_uint
;
1809 wm_prog_key
->texture_data_type
= nir_type_float
;
1812 /* src_samples and dst_samples are the true sample counts */
1813 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1814 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1816 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1818 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1821 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1822 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1824 /* Round floating point values to nearest integer to avoid "off by one texel"
1825 * kind of errors when blitting.
1827 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1828 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1829 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1830 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1832 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1833 coords
->x
.src0
, coords
->x
.src1
,
1834 coords
->x
.dst0
, coords
->x
.dst1
,
1836 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1837 coords
->y
.src0
, coords
->y
.src1
,
1838 coords
->y
.dst0
, coords
->y
.dst1
,
1842 if (devinfo
->gen
== 4) {
1843 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
1844 * Convert them to a single slice on gen4.
1846 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1847 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1848 wm_prog_key
->need_dst_offset
= true;
1851 if (params
->src
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1852 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->src
);
1853 wm_prog_key
->need_src_offset
= true;
1857 if (devinfo
->gen
> 6 &&
1858 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1859 assert(params
->dst
.surf
.samples
> 1);
1861 /* We must expand the rectangle we send through the rendering pipeline,
1862 * to account for the fact that we are mapping the destination region as
1863 * single-sampled when it is in fact multisampled. We must also align
1864 * it to a multiple of the multisampling pattern, because the
1865 * differences between multisampled and single-sampled surface formats
1866 * will mean that pixels are scrambled within the multisampling pattern.
1867 * TODO: what if this makes the coordinates too large?
1869 * Note: this only works if the destination surface uses the IMS layout.
1870 * If it's UMS, then we have no choice but to set up the rendering
1871 * pipeline as multisampled.
1873 struct isl_extent2d px_size_sa
=
1874 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1875 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1876 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1877 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1878 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1880 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1882 wm_prog_key
->use_kill
= true;
1883 wm_prog_key
->need_dst_offset
= true;
1886 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1887 /* We must modify the rectangle we send through the rendering pipeline
1888 * (and the size and x/y offset of the destination surface), to account
1889 * for the fact that we are mapping it as Y-tiled when it is in fact
1892 * Both Y tiling and W tiling can be understood as organizations of
1893 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1894 * is different, but the layout of the 32-byte sub-tiles within the 4k
1895 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1896 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1897 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1899 * Therefore, to account for the layout differences within the 32-byte
1900 * sub-tiles, we must expand the rectangle so the X coordinates of its
1901 * edges are multiples of 8 (the W sub-tile width), and its Y
1902 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1903 * Then we need to scale the X and Y coordinates of the rectangle to
1904 * account for the differences in aspect ratio between the Y and W
1905 * sub-tiles. We need to modify the layer width and height similarly.
1907 * A correction needs to be applied when MSAA is in use: since
1908 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1909 * we need to align the Y coordinates to multiples of 8, so that when
1910 * they are divided by two they are still multiples of 4.
1912 * Note: Since the x/y offset of the surface will be applied using the
1913 * SURFACE_STATE command packet, it will be invisible to the swizzling
1914 * code in the shader; therefore it needs to be in a multiple of the
1915 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1916 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1917 * buffer), and the miplevel alignment used for stencil buffers is 8
1918 * pixels horizontally and either 4 or 8 pixels vertically (see
1919 * intel_horizontal_texture_alignment_unit() and
1920 * intel_vertical_texture_alignment_unit()).
1922 * Note: Also, since the SURFACE_STATE command packet can only apply
1923 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1924 * vertically, it is important that the offsets will be multiples of
1925 * these sizes after they are converted into Y-tiled coordinates.
1926 * Fortunately they will be, since we know from above that the offsets
1927 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1928 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1930 * TODO: what if this makes the coordinates (or the texture size) too
1933 const unsigned x_align
= 8;
1934 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1935 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1936 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1937 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1938 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1940 /* Retile the surface to Y-tiled */
1941 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1943 wm_prog_key
->dst_tiled_w
= true;
1944 wm_prog_key
->use_kill
= true;
1945 wm_prog_key
->need_dst_offset
= true;
1947 if (params
->dst
.surf
.samples
> 1) {
1948 /* If the destination surface is a W-tiled multisampled stencil
1949 * buffer that we're mapping as Y tiled, then we need to arrange for
1950 * the WM program to run once per sample rather than once per pixel,
1951 * because the memory layout of related samples doesn't match between
1954 wm_prog_key
->persample_msaa_dispatch
= true;
1958 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1959 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1960 * Broadwell adds support for sampling from stencil.
1962 * See the comments above concerning x/y offset alignment for the
1963 * destination surface.
1965 * TODO: what if this makes the texture size too large?
1967 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1969 wm_prog_key
->src_tiled_w
= true;
1970 wm_prog_key
->need_src_offset
= true;
1973 /* tex_samples and rt_samples are the sample counts that are set up in
1976 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1977 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1979 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1980 * use to access the source and destination surfaces.
1982 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1983 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1985 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1986 /* We are blitting from a multisample buffer to a multisample buffer, so
1987 * we must preserve samples within a pixel. This means we have to
1988 * arrange for the WM program to run once per sample rather than once
1991 wm_prog_key
->persample_msaa_dispatch
= true;
1994 params
->num_samples
= params
->dst
.surf
.samples
;
1996 if ((wm_prog_key
->filter
== BLORP_FILTER_AVERAGE
||
1997 wm_prog_key
->filter
== BLORP_FILTER_BILINEAR
) &&
1998 batch
->blorp
->isl_dev
->info
->gen
<= 6) {
1999 /* Gen4-5 don't support non-normalized texture coordinates */
2000 wm_prog_key
->src_coords_normalized
= true;
2001 params
->wm_inputs
.src_inv_size
[0] =
2002 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.width
,
2003 params
->src
.view
.base_level
);
2004 params
->wm_inputs
.src_inv_size
[1] =
2005 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.height
,
2006 params
->src
.view
.base_level
);
2009 if (isl_format_get_layout(params
->dst
.view
.format
)->bpb
% 3 == 0) {
2010 /* We can't render to RGB formats natively because they aren't a
2011 * power-of-two size. Instead, we fake them by using a red format
2012 * with the same channel type and size and emitting shader code to
2013 * only write one channel at a time.
2018 /* If it happens to be sRGB, we need to force a conversion */
2019 if (params
->dst
.view
.format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
)
2020 wm_prog_key
->dst_format
= ISL_FORMAT_R8G8B8_UNORM_SRGB
;
2022 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
->dst
);
2024 wm_prog_key
->dst_rgb
= true;
2025 wm_prog_key
->need_dst_offset
= true;
2026 } else if (isl_format_is_rgbx(params
->dst
.view
.format
)) {
2027 /* We can handle RGBX formats easily enough by treating them as RGBA */
2028 params
->dst
.view
.format
=
2029 isl_format_rgbx_to_rgba(params
->dst
.view
.format
);
2030 } else if (params
->dst
.view
.format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
2031 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2032 params
->dst
.view
.format
= ISL_FORMAT_R32_UINT
;
2033 } else if (params
->dst
.view
.format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
2034 params
->dst
.view
.swizzle
=
2035 isl_swizzle_compose(params
->dst
.view
.swizzle
,
2036 ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
));
2037 params
->dst
.view
.format
= ISL_FORMAT_B4G4R4A4_UNORM
;
2038 } else if (params
->dst
.view
.format
== ISL_FORMAT_L8_UNORM_SRGB
) {
2039 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2040 params
->dst
.view
.format
= ISL_FORMAT_R8_UNORM
;
2041 } else if (params
->dst
.view
.format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
2042 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2043 params
->dst
.view
.format
= ISL_FORMAT_R32_UINT
;
2046 if (devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
2047 !isl_swizzle_is_identity(params
->src
.view
.swizzle
)) {
2048 wm_prog_key
->src_swizzle
= params
->src
.view
.swizzle
;
2049 params
->src
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
2051 wm_prog_key
->src_swizzle
= ISL_SWIZZLE_IDENTITY
;
2054 if (!isl_swizzle_supports_rendering(devinfo
, params
->dst
.view
.swizzle
)) {
2055 wm_prog_key
->dst_swizzle
= params
->dst
.view
.swizzle
;
2056 params
->dst
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
2058 wm_prog_key
->dst_swizzle
= ISL_SWIZZLE_IDENTITY
;
2061 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
2062 assert(wm_prog_key
->need_src_offset
);
2063 surf_get_intratile_offset_px(¶ms
->src
,
2064 ¶ms
->wm_inputs
.src_offset
.x
,
2065 ¶ms
->wm_inputs
.src_offset
.y
);
2068 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
2069 assert(wm_prog_key
->need_dst_offset
);
2070 surf_get_intratile_offset_px(¶ms
->dst
,
2071 ¶ms
->wm_inputs
.dst_offset
.x
,
2072 ¶ms
->wm_inputs
.dst_offset
.y
);
2073 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
2074 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
2075 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
2076 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
2079 /* For some texture types, we need to pass the layer through the sampler. */
2080 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
2082 if (!brw_blorp_get_blit_kernel(batch
, params
, wm_prog_key
))
2085 if (!blorp_ensure_sf_program(batch
, params
))
2088 unsigned result
= 0;
2089 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
2090 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
2091 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
2092 result
|= BLIT_WIDTH_SHRINK
;
2093 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
2094 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
2095 result
|= BLIT_HEIGHT_SHRINK
;
2098 batch
->blorp
->exec(batch
, params
);
2104 /* Adjust split blit source coordinates for the current destination
2108 adjust_split_source_coords(const struct blt_axis
*orig
,
2109 struct blt_axis
*split_coords
,
2112 /* When scale is greater than 0, then we are growing from the start, so
2113 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
2114 * source range shrinks from the end. In that case src0 is adjusted by
2115 * delta1, and src1 is adjusted by delta0.
2117 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
2118 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
2119 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
2120 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
2123 static struct isl_extent2d
2124 get_px_size_sa(const struct isl_surf
*surf
)
2126 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
2128 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
2131 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
2135 shrink_surface_params(const struct isl_device
*dev
,
2136 struct brw_blorp_surface_info
*info
,
2137 double *x0
, double *x1
, double *y0
, double *y1
)
2139 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
2140 struct isl_extent2d px_size_sa
;
2143 blorp_surf_convert_to_single_slice(dev
, info
);
2145 px_size_sa
= get_px_size_sa(&info
->surf
);
2147 /* Because this gets called after we lower compressed images, the tile
2148 * offsets may be non-zero and we need to incorporate them in our
2151 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
2152 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
2153 isl_tiling_get_intratile_offset_sa(info
->surf
.tiling
,
2154 info
->surf
.format
, info
->surf
.row_pitch_B
,
2155 x_offset_sa
, y_offset_sa
,
2157 &info
->tile_x_sa
, &info
->tile_y_sa
);
2159 info
->addr
.offset
+= byte_offset
;
2161 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
2164 info
->tile_x_sa
= 0;
2166 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
2169 info
->tile_y_sa
= 0;
2171 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
2172 info
->surf
.logical_level0_px
.width
= size
;
2173 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
2175 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
2176 info
->surf
.logical_level0_px
.height
= size
;
2177 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
2181 shrink_surfaces(const struct isl_device
*dev
,
2182 struct blorp_params
*params
,
2183 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2184 struct blt_coords
*coords
)
2186 /* Shrink source surface */
2187 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
2188 &coords
->y
.src0
, &coords
->y
.src1
);
2189 wm_prog_key
->need_src_offset
= false;
2191 /* Shrink destination surface */
2192 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
2193 &coords
->y
.dst0
, &coords
->y
.dst1
);
2194 wm_prog_key
->need_dst_offset
= false;
2198 do_blorp_blit(struct blorp_batch
*batch
,
2199 const struct blorp_params
*orig_params
,
2200 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2201 const struct blt_coords
*orig
)
2203 struct blorp_params params
;
2204 struct blt_coords blit_coords
;
2205 struct blt_coords split_coords
= *orig
;
2206 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
2207 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
2208 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
2209 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
2215 bool x_done
, y_done
;
2216 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
2218 params
= *orig_params
;
2219 blit_coords
= split_coords
;
2221 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
2223 enum blit_shrink_status result
=
2224 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
2226 if (result
& BLIT_WIDTH_SHRINK
) {
2229 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2230 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2232 if (result
& BLIT_HEIGHT_SHRINK
) {
2235 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2236 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2240 assert(can_shrink_surfaces(orig_params
));
2245 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
2246 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
2249 } else if (y_done
) {
2250 split_coords
.x
.dst0
+= w
;
2251 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2252 split_coords
.y
.dst0
= orig
->y
.dst0
;
2253 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2254 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2256 split_coords
.y
.dst0
+= h
;
2257 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2258 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2264 blorp_blit(struct blorp_batch
*batch
,
2265 const struct blorp_surf
*src_surf
,
2266 unsigned src_level
, unsigned src_layer
,
2267 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2268 const struct blorp_surf
*dst_surf
,
2269 unsigned dst_level
, unsigned dst_layer
,
2270 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2271 float src_x0
, float src_y0
,
2272 float src_x1
, float src_y1
,
2273 float dst_x0
, float dst_y0
,
2274 float dst_x1
, float dst_y1
,
2275 enum blorp_filter filter
,
2276 bool mirror_x
, bool mirror_y
)
2278 struct blorp_params params
;
2279 blorp_params_init(¶ms
);
2281 /* We cannot handle combined depth and stencil. */
2282 if (src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2283 assert(src_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2284 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2285 assert(dst_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2287 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
2288 assert(src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
);
2289 /* Prior to Broadwell, we can't render to R8_UINT */
2290 if (batch
->blorp
->isl_dev
->info
->gen
< 8) {
2291 src_format
= ISL_FORMAT_R8_UNORM
;
2292 dst_format
= ISL_FORMAT_R8_UNORM
;
2296 /* ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as a render target,
2297 * which requires shader math to render to it. Blitting Z24X8 to Z24X8
2298 * is fairly common though, so we'd like to avoid it. Since we don't need
2299 * to blend depth values, we can simply pick a renderable format with the
2300 * right number of bits-per-pixel, like 8-bit BGRA.
2302 if (dst_surf
->surf
->format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
&&
2303 src_surf
->surf
->format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
2304 src_format
= dst_format
= ISL_FORMAT_B8G8R8A8_UNORM
;
2307 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2308 src_layer
, src_format
, false);
2309 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2310 dst_layer
, dst_format
, true);
2312 params
.src
.view
.swizzle
= src_swizzle
;
2313 params
.dst
.view
.swizzle
= dst_swizzle
;
2315 struct brw_blorp_blit_prog_key wm_prog_key
= {
2316 .shader_type
= BLORP_SHADER_TYPE_BLIT
,
2320 /* Scaling factors used for bilinear filtering in multisample scaled
2323 if (params
.src
.surf
.samples
== 16)
2324 wm_prog_key
.x_scale
= 4.0f
;
2326 wm_prog_key
.x_scale
= 2.0f
;
2327 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2329 params
.wm_inputs
.rect_grid
.x1
=
2330 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2331 wm_prog_key
.x_scale
- 1.0f
;
2332 params
.wm_inputs
.rect_grid
.y1
=
2333 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2334 wm_prog_key
.y_scale
- 1.0f
;
2336 struct blt_coords coords
= {
2353 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2356 static enum isl_format
2357 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2359 /* The choice of UNORM and UINT formats is very intentional here. Most
2360 * of the time, we want to use a UINT format to avoid any rounding error
2361 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2362 * (It's the only format allowed in conjunction with W-tiling.) Also we
2363 * intentionally use the 4-channel formats whenever we can. This is so
2364 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2365 * even though one of them is 3/4 the size of the other. The choice of
2366 * UNORM vs. UINT is also very intentional because we don't have 8 or
2367 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2368 * Fortunately, the only time we should ever use two different formats in
2369 * the table below is for RGB -> RGBA blits and so we will never have any
2370 * UNORM/UINT mismatch.
2372 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2374 case 8: return ISL_FORMAT_R8_UINT
;
2375 case 16: return ISL_FORMAT_R8G8_UINT
;
2376 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2377 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2378 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2379 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2380 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2381 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2383 unreachable("Unknown format bpb");
2387 case 8: return ISL_FORMAT_R8_UINT
;
2388 case 16: return ISL_FORMAT_R8G8_UINT
;
2389 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2390 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2391 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2392 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2393 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2394 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2396 unreachable("Unknown format bpb");
2401 /** Returns a UINT format that is CCS-compatible with the given format
2403 * The PRM's say absolutely nothing about how render compression works. The
2404 * only thing they provide is a list of formats on which it is and is not
2405 * supported. Empirical testing indicates that the compression is only based
2406 * on the bit-layout of the format and the channel encoding doesn't matter.
2407 * So, while texture views don't work in general, you can create a view as
2408 * long as the bit-layout of the formats are the same.
2410 * Fortunately, for every render compression capable format, the UINT format
2411 * with the same bit layout also supports render compression. This means that
2412 * we only need to handle UINT formats for copy operations. In order to do
2413 * copies between formats with different bit layouts, we attach both with a
2414 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2415 * operation between the two bit layouts.
2417 static enum isl_format
2418 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2420 switch (fmtl
->format
) {
2421 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2422 case ISL_FORMAT_R32G32B32A32_SINT
:
2423 case ISL_FORMAT_R32G32B32A32_UINT
:
2424 case ISL_FORMAT_R32G32B32A32_UNORM
:
2425 case ISL_FORMAT_R32G32B32A32_SNORM
:
2426 case ISL_FORMAT_R32G32B32X32_FLOAT
:
2427 return ISL_FORMAT_R32G32B32A32_UINT
;
2429 case ISL_FORMAT_R16G16B16A16_UNORM
:
2430 case ISL_FORMAT_R16G16B16A16_SNORM
:
2431 case ISL_FORMAT_R16G16B16A16_SINT
:
2432 case ISL_FORMAT_R16G16B16A16_UINT
:
2433 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2434 case ISL_FORMAT_R16G16B16X16_UNORM
:
2435 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2436 return ISL_FORMAT_R16G16B16A16_UINT
;
2438 case ISL_FORMAT_R32G32_FLOAT
:
2439 case ISL_FORMAT_R32G32_SINT
:
2440 case ISL_FORMAT_R32G32_UINT
:
2441 case ISL_FORMAT_R32G32_UNORM
:
2442 case ISL_FORMAT_R32G32_SNORM
:
2443 return ISL_FORMAT_R32G32_UINT
;
2445 case ISL_FORMAT_B8G8R8A8_UNORM
:
2446 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2447 case ISL_FORMAT_R8G8B8A8_UNORM
:
2448 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2449 case ISL_FORMAT_R8G8B8A8_SNORM
:
2450 case ISL_FORMAT_R8G8B8A8_SINT
:
2451 case ISL_FORMAT_R8G8B8A8_UINT
:
2452 case ISL_FORMAT_B8G8R8X8_UNORM
:
2453 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2454 case ISL_FORMAT_R8G8B8X8_UNORM
:
2455 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2456 return ISL_FORMAT_R8G8B8A8_UINT
;
2458 case ISL_FORMAT_R16G16_UNORM
:
2459 case ISL_FORMAT_R16G16_SNORM
:
2460 case ISL_FORMAT_R16G16_SINT
:
2461 case ISL_FORMAT_R16G16_UINT
:
2462 case ISL_FORMAT_R16G16_FLOAT
:
2463 return ISL_FORMAT_R16G16_UINT
;
2465 case ISL_FORMAT_R32_SINT
:
2466 case ISL_FORMAT_R32_UINT
:
2467 case ISL_FORMAT_R32_FLOAT
:
2468 case ISL_FORMAT_R32_UNORM
:
2469 case ISL_FORMAT_R32_SNORM
:
2470 return ISL_FORMAT_R32_UINT
;
2472 case ISL_FORMAT_B10G10R10A2_UNORM
:
2473 case ISL_FORMAT_B10G10R10A2_UNORM_SRGB
:
2474 case ISL_FORMAT_R10G10B10A2_UNORM
:
2475 case ISL_FORMAT_R10G10B10A2_UINT
:
2476 return ISL_FORMAT_R10G10B10A2_UINT
;
2479 unreachable("Not a compressible format");
2484 blorp_surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2485 struct brw_blorp_surface_info
*info
,
2486 uint32_t *x
, uint32_t *y
,
2487 uint32_t *width
, uint32_t *height
)
2489 const struct isl_format_layout
*fmtl
=
2490 isl_format_get_layout(info
->surf
.format
);
2492 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2494 /* This is a compressed surface. We need to convert it to a single
2495 * slice (because compressed layouts don't perfectly match uncompressed
2496 * ones with the same bpb) and divide x, y, width, and height by the
2499 blorp_surf_convert_to_single_slice(isl_dev
, info
);
2501 if (width
&& height
) {
2503 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2504 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2505 assert(*width
% fmtl
->bw
== 0 ||
2506 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2507 assert(*height
% fmtl
->bh
== 0 ||
2508 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2510 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2511 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2515 assert(*x
% fmtl
->bw
== 0);
2516 assert(*y
% fmtl
->bh
== 0);
2521 info
->surf
.logical_level0_px
.width
=
2522 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
2523 info
->surf
.logical_level0_px
.height
=
2524 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
2526 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
2527 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
2528 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2529 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2531 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2532 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2533 info
->tile_x_sa
/= fmtl
->bw
;
2534 info
->tile_y_sa
/= fmtl
->bh
;
2536 /* It's now an uncompressed surface so we need an uncompressed format */
2537 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2541 blorp_copy(struct blorp_batch
*batch
,
2542 const struct blorp_surf
*src_surf
,
2543 unsigned src_level
, unsigned src_layer
,
2544 const struct blorp_surf
*dst_surf
,
2545 unsigned dst_level
, unsigned dst_layer
,
2546 uint32_t src_x
, uint32_t src_y
,
2547 uint32_t dst_x
, uint32_t dst_y
,
2548 uint32_t src_width
, uint32_t src_height
)
2550 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2551 struct blorp_params params
;
2553 if (src_width
== 0 || src_height
== 0)
2556 blorp_params_init(¶ms
);
2557 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2558 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2559 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2560 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2562 struct brw_blorp_blit_prog_key wm_prog_key
= {
2563 .shader_type
= BLORP_SHADER_TYPE_BLIT
,
2564 .filter
= BLORP_FILTER_NONE
,
2565 .need_src_offset
= src_surf
->tile_x_sa
|| src_surf
->tile_y_sa
,
2566 .need_dst_offset
= dst_surf
->tile_x_sa
|| dst_surf
->tile_y_sa
,
2569 const struct isl_format_layout
*src_fmtl
=
2570 isl_format_get_layout(params
.src
.surf
.format
);
2571 const struct isl_format_layout
*dst_fmtl
=
2572 isl_format_get_layout(params
.dst
.surf
.format
);
2574 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2575 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2576 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2577 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2578 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2579 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2581 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2582 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2583 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2584 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2585 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2586 params
.src
.view
.format
= params
.dst
.view
.format
;
2588 params
.src
.view
.format
=
2589 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2591 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2592 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2593 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2594 params
.dst
.view
.format
= params
.src
.view
.format
;
2596 params
.dst
.view
.format
=
2597 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2600 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2601 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2604 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2605 /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
2606 * enabled even though CCS_E doesn't technically do sRGB on SKL because
2607 * we stomp everything to UINT anyway. The one thing we have to be
2608 * careful of is clear colors. Because fast clear colors for sRGB on
2609 * gen9 are encoded as the float values between format conversion and
2610 * sRGB curve application, a given clear color float will convert to the
2611 * same bits regardless of whether the format is UNORM or sRGB.
2612 * Therefore, we can handle sRGB without any special cases.
2614 UNUSED
enum isl_format linear_src_format
=
2615 isl_format_srgb_to_linear(src_surf
->surf
->format
);
2616 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2618 params
.src
.view
.format
));
2620 isl_color_value_pack(¶ms
.src
.clear_color
,
2621 linear_src_format
, packed
);
2622 isl_color_value_unpack(¶ms
.src
.clear_color
,
2623 params
.src
.view
.format
, packed
);
2626 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2627 /* See above where we handle linear_src_format */
2628 UNUSED
enum isl_format linear_dst_format
=
2629 isl_format_srgb_to_linear(dst_surf
->surf
->format
);
2630 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2632 params
.dst
.view
.format
));
2634 isl_color_value_pack(¶ms
.dst
.clear_color
,
2635 linear_dst_format
, packed
);
2636 isl_color_value_unpack(¶ms
.dst
.clear_color
,
2637 params
.dst
.view
.format
, packed
);
2640 if (params
.src
.view
.format
!= params
.dst
.view
.format
) {
2641 enum isl_format src_cast_format
= params
.src
.view
.format
;
2642 enum isl_format dst_cast_format
= params
.dst
.view
.format
;
2644 /* The BLORP bitcast code gets confused by RGB formats. Just treat them
2645 * as RGBA and then everything will be happy. This is perfectly safe
2646 * because BLORP likes to treat things as if they have vec4 colors all
2649 if (isl_format_is_rgb(src_cast_format
))
2650 src_cast_format
= isl_format_rgb_to_rgba(src_cast_format
);
2651 if (isl_format_is_rgb(dst_cast_format
))
2652 dst_cast_format
= isl_format_rgb_to_rgba(dst_cast_format
);
2654 if (src_cast_format
!= dst_cast_format
) {
2655 wm_prog_key
.format_bit_cast
= true;
2656 wm_prog_key
.src_format
= src_cast_format
;
2657 wm_prog_key
.dst_format
= dst_cast_format
;
2661 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2662 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2664 &src_width
, &src_height
);
2665 wm_prog_key
.need_src_offset
= true;
2668 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2669 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2670 &dst_x
, &dst_y
, NULL
, NULL
);
2671 wm_prog_key
.need_dst_offset
= true;
2674 /* Once both surfaces are stompped to uncompressed as needed, the
2675 * destination size is the same as the source size.
2677 uint32_t dst_width
= src_width
;
2678 uint32_t dst_height
= src_height
;
2680 struct blt_coords coords
= {
2683 .src1
= src_x
+ src_width
,
2685 .dst1
= dst_x
+ dst_width
,
2690 .src1
= src_y
+ src_height
,
2692 .dst1
= dst_y
+ dst_height
,
2697 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2700 static enum isl_format
2701 isl_format_for_size(unsigned size_B
)
2704 case 1: return ISL_FORMAT_R8_UINT
;
2705 case 2: return ISL_FORMAT_R8G8_UINT
;
2706 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
2707 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
2708 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
2710 unreachable("Not a power-of-two format size");
2715 * Returns the greatest common divisor of a and b that is a power of two.
2718 gcd_pow2_u64(uint64_t a
, uint64_t b
)
2720 assert(a
> 0 || b
> 0);
2722 unsigned a_log2
= ffsll(a
) - 1;
2723 unsigned b_log2
= ffsll(b
) - 1;
2725 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
2726 * case, the MIN2() will take the other one. If both are 0 then we will
2727 * hit the assert above.
2729 return 1 << MIN2(a_log2
, b_log2
);
2733 do_buffer_copy(struct blorp_batch
*batch
,
2734 struct blorp_address
*src
,
2735 struct blorp_address
*dst
,
2736 int width
, int height
, int block_size
)
2738 /* The actual format we pick doesn't matter as blorp will throw it away.
2739 * The only thing that actually matters is the size.
2741 enum isl_format format
= isl_format_for_size(block_size
);
2744 struct isl_surf surf
;
2745 ok
= isl_surf_init(batch
->blorp
->isl_dev
, &surf
,
2746 .dim
= ISL_SURF_DIM_2D
,
2754 .row_pitch_B
= width
* block_size
,
2755 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
2756 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
2757 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
2760 struct blorp_surf src_blorp_surf
= {
2765 struct blorp_surf dst_blorp_surf
= {
2770 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
2771 0, 0, 0, 0, width
, height
);
2775 blorp_buffer_copy(struct blorp_batch
*batch
,
2776 struct blorp_address src
,
2777 struct blorp_address dst
,
2780 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
2781 uint64_t copy_size
= size
;
2783 /* This is maximum possible width/height our HW can handle */
2784 uint64_t max_surface_dim
= 1 << (devinfo
->gen
>= 7 ? 14 : 13);
2786 /* First, we compute the biggest format that can be used with the
2787 * given offsets and size.
2790 bs
= gcd_pow2_u64(bs
, src
.offset
);
2791 bs
= gcd_pow2_u64(bs
, dst
.offset
);
2792 bs
= gcd_pow2_u64(bs
, size
);
2794 /* First, we make a bunch of max-sized copies */
2795 uint64_t max_copy_size
= max_surface_dim
* max_surface_dim
* bs
;
2796 while (copy_size
>= max_copy_size
) {
2797 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, max_surface_dim
, bs
);
2798 copy_size
-= max_copy_size
;
2799 src
.offset
+= max_copy_size
;
2800 dst
.offset
+= max_copy_size
;
2803 /* Now make a max-width copy */
2804 uint64_t height
= copy_size
/ (max_surface_dim
* bs
);
2805 assert(height
< max_surface_dim
);
2807 uint64_t rect_copy_size
= height
* max_surface_dim
* bs
;
2808 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, height
, bs
);
2809 copy_size
-= rect_copy_size
;
2810 src
.offset
+= rect_copy_size
;
2811 dst
.offset
+= rect_copy_size
;
2814 /* Finally, make a small copy to finish it off */
2815 if (copy_size
!= 0) {
2816 do_buffer_copy(batch
, &src
, &dst
, copy_size
/ bs
, 1, bs
);