2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/nir/nir_builder.h"
26 #include "blorp_priv.h"
27 #include "brw_meta_util.h"
29 #define FILE_DEBUG_FLAG DEBUG_BLORP
32 * Enum to specify the order of arguments in a sampler message
34 enum sampler_message_arg
36 SAMPLER_MESSAGE_ARG_U_FLOAT
,
37 SAMPLER_MESSAGE_ARG_V_FLOAT
,
38 SAMPLER_MESSAGE_ARG_U_INT
,
39 SAMPLER_MESSAGE_ARG_V_INT
,
40 SAMPLER_MESSAGE_ARG_R_INT
,
41 SAMPLER_MESSAGE_ARG_SI_INT
,
42 SAMPLER_MESSAGE_ARG_MCS_INT
,
43 SAMPLER_MESSAGE_ARG_ZERO_INT
,
46 struct brw_blorp_blit_vars
{
47 /* Input values from brw_blorp_wm_inputs */
48 nir_variable
*v_discard_rect
;
49 nir_variable
*v_rect_grid
;
50 nir_variable
*v_coord_transform
;
51 nir_variable
*v_src_z
;
52 nir_variable
*v_src_offset
;
53 nir_variable
*v_dst_offset
;
56 nir_variable
*frag_coord
;
59 nir_variable
*color_out
;
63 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
64 const struct brw_blorp_blit_prog_key
*key
)
66 /* Blended and scaled blits never use pixel discard. */
67 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
69 #define LOAD_INPUT(name, type)\
70 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
72 LOAD_INPUT(discard_rect
, glsl_vec4_type())
73 LOAD_INPUT(rect_grid
, glsl_vec4_type())
74 LOAD_INPUT(coord_transform
, glsl_vec4_type())
75 LOAD_INPUT(src_z
, glsl_uint_type())
76 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
77 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
81 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
82 glsl_vec4_type(), "gl_FragCoord");
83 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
84 v
->frag_coord
->data
.origin_upper_left
= true;
86 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
87 glsl_vec4_type(), "gl_FragColor");
88 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
92 blorp_blit_get_frag_coords(nir_builder
*b
,
93 const struct brw_blorp_blit_prog_key
*key
,
94 struct brw_blorp_blit_vars
*v
)
96 nir_ssa_def
*coord
= nir_f2i(b
, nir_load_var(b
, v
->frag_coord
));
98 /* Account for destination surface intratile offset
100 * Transformation parameters giving translation from destination to source
101 * coordinates don't take into account possible intra-tile destination
102 * offset. Therefore it has to be first subtracted from the incoming
103 * coordinates. Vertices are set up based on coordinates containing the
106 if (key
->need_dst_offset
)
107 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
109 if (key
->persample_msaa_dispatch
) {
110 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
111 nir_load_sample_id(b
));
113 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
118 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
122 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
123 struct brw_blorp_blit_vars
*v
)
125 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
127 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
128 nir_channel(b
, coord_transform
, 3));
129 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
130 nir_channel(b
, coord_transform
, 2));
132 return nir_ffma(b
, src_pos
, mul
, offset
);
136 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
137 struct brw_blorp_blit_vars
*v
)
139 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
140 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
141 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
142 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
143 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
144 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
146 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
147 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
148 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
149 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
151 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
153 nir_intrinsic_instr
*discard
=
154 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
155 discard
->src
[0] = nir_src_for_ssa(oob
);
156 nir_builder_instr_insert(b
, &discard
->instr
);
159 static nir_tex_instr
*
160 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
161 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
162 nir_alu_type dst_type
)
164 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
168 tex
->dest_type
= dst_type
;
169 tex
->is_array
= false;
170 tex
->is_shadow
= false;
172 /* Blorp only has one texture and it's bound at unit 0 */
175 tex
->texture_index
= 0;
176 tex
->sampler_index
= 0;
178 /* To properly handle 3-D and 2-D array textures, we pull the Z component
179 * from an input. TODO: This is a bit magic; we should probably make this
180 * more explicit in the future.
182 assert(pos
->num_components
>= 2);
183 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
184 nir_load_var(b
, v
->v_src_z
));
186 tex
->src
[0].src_type
= nir_tex_src_coord
;
187 tex
->src
[0].src
= nir_src_for_ssa(pos
);
188 tex
->coord_components
= 3;
190 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
196 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
197 nir_ssa_def
*pos
, nir_alu_type dst_type
)
200 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2, dst_type
);
202 assert(pos
->num_components
== 2);
203 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
204 tex
->src
[1].src_type
= nir_tex_src_lod
;
205 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
207 nir_builder_instr_insert(b
, &tex
->instr
);
209 return &tex
->dest
.ssa
;
213 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
214 nir_ssa_def
*pos
, nir_alu_type dst_type
)
217 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
219 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
220 tex
->src
[1].src_type
= nir_tex_src_lod
;
221 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
223 nir_builder_instr_insert(b
, &tex
->instr
);
225 return &tex
->dest
.ssa
;
229 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
230 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
233 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
234 mcs
!= NULL
? 3 : 2, dst_type
);
236 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
238 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
239 if (pos
->num_components
== 2) {
240 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
242 assert(pos
->num_components
== 3);
243 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
247 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
248 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
251 nir_builder_instr_insert(b
, &tex
->instr
);
253 return &tex
->dest
.ssa
;
257 blorp_nir_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
, nir_ssa_def
*pos
)
260 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
261 pos
, 1, nir_type_int
);
263 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
265 nir_builder_instr_insert(b
, &tex
->instr
);
267 return &tex
->dest
.ssa
;
271 nir_mask_shift_or(struct nir_builder
*b
, nir_ssa_def
*dst
, nir_ssa_def
*src
,
272 uint32_t src_mask
, int src_left_shift
)
274 nir_ssa_def
*masked
= nir_iand(b
, src
, nir_imm_int(b
, src_mask
));
276 nir_ssa_def
*shifted
;
277 if (src_left_shift
> 0) {
278 shifted
= nir_ishl(b
, masked
, nir_imm_int(b
, src_left_shift
));
279 } else if (src_left_shift
< 0) {
280 shifted
= nir_ushr(b
, masked
, nir_imm_int(b
, -src_left_shift
));
282 assert(src_left_shift
== 0);
286 return nir_ior(b
, dst
, shifted
);
290 * Emit code to compensate for the difference between Y and W tiling.
292 * This code modifies the X and Y coordinates according to the formula:
294 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
296 * (See brw_blorp_build_nir_shader).
298 static inline nir_ssa_def
*
299 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
301 assert(pos
->num_components
== 2);
302 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
303 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
305 /* Given X and Y coordinates that describe an address using Y tiling,
306 * translate to the X and Y coordinates that describe the same address
309 * If we break down the low order bits of X and Y, using a
310 * single letter to represent each low-order bit:
312 * X = A << 7 | 0bBCDEFGH
313 * Y = J << 5 | 0bKLMNP (1)
315 * Then we can apply the Y tiling formula to see the memory offset being
318 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
320 * If we apply the W detiling formula to this memory location, that the
321 * corresponding X' and Y' coordinates are:
323 * X' = A << 6 | 0bBCDPFH (3)
324 * Y' = J << 6 | 0bKLMNEG
326 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
327 * we need to make the following computation:
329 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
330 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
332 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
333 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
334 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
335 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
337 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
338 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
339 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
340 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
342 return nir_vec2(b
, x_W
, y_W
);
346 * Emit code to compensate for the difference between Y and W tiling.
348 * This code modifies the X and Y coordinates according to the formula:
350 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
352 * (See brw_blorp_build_nir_shader).
354 static inline nir_ssa_def
*
355 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
357 assert(pos
->num_components
== 2);
358 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
359 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
361 /* Applying the same logic as above, but in reverse, we obtain the
364 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
365 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
367 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
368 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
369 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
370 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
371 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
373 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
374 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
375 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
377 return nir_vec2(b
, x_Y
, y_Y
);
381 * Emit code to compensate for the difference between MSAA and non-MSAA
384 * This code modifies the X and Y coordinates according to the formula:
386 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
388 * (See brw_blorp_blit_program).
390 static inline nir_ssa_def
*
391 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
392 unsigned num_samples
, enum isl_msaa_layout layout
)
394 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
397 case ISL_MSAA_LAYOUT_NONE
:
398 assert(pos
->num_components
== 2);
400 case ISL_MSAA_LAYOUT_ARRAY
:
401 /* No translation needed */
403 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
404 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
405 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
406 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
407 nir_channel(b
, pos
, 2);
409 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
410 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
411 switch (num_samples
) {
414 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
415 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
418 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
419 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
420 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
422 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
423 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
424 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
425 if (num_samples
== 2) {
428 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
429 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
430 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
435 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
436 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
438 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
440 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
441 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
442 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
443 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
444 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
445 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
446 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
450 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
451 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
453 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
456 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
457 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
458 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
459 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
460 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
461 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
462 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
463 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
467 unreachable("Invalid number of samples for IMS layout");
470 return nir_vec2(b
, x_out
, y_out
);
474 unreachable("Invalid MSAA layout");
479 * Emit code to compensate for the difference between MSAA and non-MSAA
482 * This code modifies the X and Y coordinates according to the formula:
484 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
486 * (See brw_blorp_blit_program).
488 static inline nir_ssa_def
*
489 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
490 unsigned num_samples
, enum isl_msaa_layout layout
)
492 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
495 case ISL_MSAA_LAYOUT_NONE
:
496 /* No translation necessary, and S should already be zero. */
497 assert(pos
->num_components
== 2);
499 case ISL_MSAA_LAYOUT_ARRAY
:
500 /* No translation necessary. */
502 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
503 assert(pos
->num_components
== 2);
505 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
506 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
508 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
509 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
510 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
511 switch (num_samples
) {
514 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
515 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
516 * S = (X & 0b10) >> 1
518 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
519 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
520 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
521 * S = (Y & 0b10) | (X & 0b10) >> 1
523 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
524 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
525 if (num_samples
== 2) {
527 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
529 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
530 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
531 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
532 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
537 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
538 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
539 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
540 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
542 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
543 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
544 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
545 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
546 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
547 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
548 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
552 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
553 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
554 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
555 * S = (Y & 0b100) << 1 | (X & 0b100) |
556 * (Y & 0b10) | (X & 0b10) >> 1
558 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
559 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
560 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
561 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
562 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
563 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
564 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
565 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
569 unreachable("Invalid number of samples for IMS layout");
572 return nir_vec3(b
, x_out
, y_out
, s_out
);
576 unreachable("Invalid MSAA layout");
581 * Count the number of trailing 1 bits in the given value. For example:
583 * count_trailing_one_bits(0) == 0
584 * count_trailing_one_bits(7) == 3
585 * count_trailing_one_bits(11) == 2
587 static inline int count_trailing_one_bits(unsigned value
)
589 #ifdef HAVE___BUILTIN_CTZ
590 return __builtin_ctz(~value
);
592 return _mesa_bitcount(value
& ~(value
+ 1));
597 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
598 nir_ssa_def
*pos
, unsigned tex_samples
,
599 enum isl_aux_usage tex_aux_usage
,
600 nir_alu_type dst_type
)
602 /* If non-null, this is the outer-most if statement */
603 nir_if
*outer_if
= NULL
;
605 nir_variable
*color
=
606 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
608 nir_ssa_def
*mcs
= NULL
;
609 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
610 mcs
= blorp_nir_txf_ms_mcs(b
, v
, pos
);
612 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
614 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
616 * This ensures that when all samples have the same value, no numerical
617 * precision is lost, since each addition operation always adds two equal
618 * values, and summing two equal floating point values does not lose
621 * We perform this computation by treating the texture_data array as a
622 * stack and performing the following operations:
624 * - push sample 0 onto stack
625 * - push sample 1 onto stack
626 * - add top two stack entries
627 * - push sample 2 onto stack
628 * - push sample 3 onto stack
629 * - add top two stack entries
630 * - add top two stack entries
631 * - divide top stack entry by 4
633 * Note that after pushing sample i onto the stack, the number of add
634 * operations we do is equal to the number of trailing 1 bits in i. This
635 * works provided the total number of samples is a power of two, which it
636 * always is for i965.
638 * For integer formats, we replace the add operations with average
639 * operations and skip the final division.
641 nir_ssa_def
*texture_data
[5];
642 unsigned stack_depth
= 0;
643 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
644 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
646 /* Push sample i onto the stack */
647 assert(stack_depth
< ARRAY_SIZE(texture_data
));
649 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
650 nir_channel(b
, pos
, 1),
652 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
654 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
655 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
656 * suggests an optimization:
658 * "A simple optimization with probable large return in
659 * performance is to compare the MCS value to zero (indicating
660 * all samples are on sample slice 0), and sample only from
661 * sample slice 0 using ld2dss if MCS is zero."
663 * Note that in the case where the MCS value is zero, sampling from
664 * sample slice 0 using ld2dss and sampling from sample 0 using
665 * ld2dms are equivalent (since all samples are on sample slice 0).
666 * Since we have already sampled from sample 0, all we need to do is
667 * skip the remaining fetches and averaging if MCS is zero.
669 nir_ssa_def
*mcs_zero
=
670 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
671 if (tex_samples
== 16) {
672 mcs_zero
= nir_iand(b
, mcs_zero
,
673 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
676 nir_if
*if_stmt
= nir_if_create(b
->shader
);
677 if_stmt
->condition
= nir_src_for_ssa(mcs_zero
);
678 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
680 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
681 nir_store_var(b
, color
, texture_data
[0], 0xf);
683 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
687 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
688 assert(stack_depth
>= 2);
691 assert(dst_type
== nir_type_float
);
692 texture_data
[stack_depth
- 1] =
693 nir_fadd(b
, texture_data
[stack_depth
- 1],
694 texture_data
[stack_depth
]);
698 /* We should have just 1 sample on the stack now. */
699 assert(stack_depth
== 1);
701 texture_data
[0] = nir_fmul(b
, texture_data
[0],
702 nir_imm_float(b
, 1.0 / tex_samples
));
704 nir_store_var(b
, color
, texture_data
[0], 0xf);
707 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
709 return nir_load_var(b
, color
);
712 static inline nir_ssa_def
*
713 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
717 memset(&v
, 0, sizeof(v
));
721 return nir_build_imm(build
, 4, 32, v
);
725 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
726 unsigned tex_samples
,
727 const struct brw_blorp_blit_prog_key
*key
,
728 struct brw_blorp_blit_vars
*v
)
730 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
731 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
732 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
734 /* Translate coordinates to lay out the samples in a rectangular grid
735 * roughly corresponding to sample locations.
737 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
738 /* Adjust coordinates so that integers represent pixel centers rather
741 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
742 /* Clamp the X, Y texture coordinates to properly handle the sampling of
743 * texels on texture edges.
745 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
746 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
747 nir_channel(b
, rect_grid
, 1)));
749 /* Store the fractional parts to be used as bilinear interpolation
752 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
753 /* Round the float coordinates down to nearest integer */
754 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
756 nir_ssa_def
*tex_data
[4];
757 for (unsigned i
= 0; i
< 4; ++i
) {
758 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
759 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
760 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
762 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
763 nir_ssa_def
*sample_coords_int
= nir_f2i(b
, sample_coords
);
765 /* The MCS value we fetch has to match up with the pixel that we're
766 * sampling from. Since we sample from different pixels in each
767 * iteration of this "for" loop, the call to mcs_fetch() should be
768 * here inside the loop after computing the pixel coordinates.
770 nir_ssa_def
*mcs
= NULL
;
771 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
772 mcs
= blorp_nir_txf_ms_mcs(b
, v
, sample_coords_int
);
774 /* Compute sample index and map the sample index to a sample number.
775 * Sample index layout shows the numbering of slots in a rectangular
776 * grid of samples with in a pixel. Sample number layout shows the
777 * rectangular grid of samples roughly corresponding to the real sample
778 * locations with in a pixel.
779 * In case of 4x MSAA, layout of sample indices matches the layout of
787 * In case of 8x MSAA the two layouts don't match.
788 * sample index layout : --------- sample number layout : ---------
789 * | 0 | 1 | | 3 | 7 |
790 * --------- ---------
791 * | 2 | 3 | | 5 | 0 |
792 * --------- ---------
793 * | 4 | 5 | | 1 | 2 |
794 * --------- ---------
795 * | 6 | 7 | | 4 | 6 |
796 * --------- ---------
798 * Fortunately, this can be done fairly easily as:
799 * S' = (0x17306425 >> (S * 4)) & 0xf
801 * In the case of 16x MSAA the two layouts don't match.
802 * Sample index layout: Sample number layout:
803 * --------------------- ---------------------
804 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
805 * --------------------- ---------------------
806 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
807 * --------------------- ---------------------
808 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
809 * --------------------- ---------------------
810 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
811 * --------------------- ---------------------
813 * This is equivalent to
814 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
816 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
817 nir_ssa_def
*sample
=
818 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
819 key
->x_scale
* key
->y_scale
));
820 sample
= nir_f2i(b
, sample
);
822 if (tex_samples
== 8) {
823 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
824 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
825 nir_imm_int(b
, 0xf));
826 } else if (tex_samples
== 16) {
827 nir_ssa_def
*sample_low
=
828 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
829 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
830 nir_imm_int(b
, 0xf));
831 nir_ssa_def
*sample_high
=
832 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
833 nir_ishl(b
, nir_iadd(b
, sample
,
836 nir_imm_int(b
, 0xf));
838 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
839 sample_low
, sample_high
);
841 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
842 nir_channel(b
, sample_coords_int
, 1),
844 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
847 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
848 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
849 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
850 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
854 /** Perform a color bit-cast operation
856 * For copy operations involving CCS, we may need to use different formats for
857 * the source and destination surfaces. The two formats must both be UINT
858 * formats and must have the same size but may have different bit layouts.
859 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
860 * to R16G16_UINT. This function generates code to shuffle bits around to get
861 * us from one to the other.
864 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
865 const struct brw_blorp_blit_prog_key
*key
)
867 assert(key
->texture_data_type
== nir_type_uint
);
869 if (key
->dst_bpc
> key
->src_bpc
) {
870 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
871 nir_ssa_def
*dst_chan
[2] = { u
, u
};
873 unsigned dst_idx
= 0;
874 for (unsigned i
= 0; i
< 4; i
++) {
875 nir_ssa_def
*shifted
= nir_ishl(b
, nir_channel(b
, color
, i
),
876 nir_imm_int(b
, shift
));
878 dst_chan
[dst_idx
] = shifted
;
880 dst_chan
[dst_idx
] = nir_ior(b
, dst_chan
[dst_idx
], shifted
);
883 shift
+= key
->src_bpc
;
884 if (shift
>= key
->dst_bpc
) {
890 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], u
, u
);
892 assert(key
->dst_bpc
< key
->src_bpc
);
894 nir_ssa_def
*mask
= nir_imm_int(b
, ~0u >> (32 - key
->dst_bpc
));
896 nir_ssa_def
*dst_chan
[4];
897 unsigned src_idx
= 0;
899 for (unsigned i
= 0; i
< 4; i
++) {
900 dst_chan
[i
] = nir_iand(b
, nir_ushr(b
, nir_channel(b
, color
, src_idx
),
901 nir_imm_int(b
, shift
)),
903 shift
+= key
->dst_bpc
;
904 if (shift
>= key
->src_bpc
) {
910 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], dst_chan
[2], dst_chan
[3]);
915 * Generator for WM programs used in BLORP blits.
917 * The bulk of the work done by the WM program is to wrap and unwrap the
918 * coordinate transformations used by the hardware to store surfaces in
919 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
920 * sample index for a multisampled surface) to a memory offset by the
921 * following formulas:
923 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
924 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
926 * For a single-sampled surface, or for a multisampled surface using
927 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
930 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
931 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
932 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
933 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
935 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
936 * embeds the sample number into bit 1 of the X and Y coordinates:
938 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
939 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
940 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
941 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
942 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
943 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
944 * S = (Y & 0b10) | (X & 0b10) >> 1
946 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
947 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
950 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
951 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
952 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
953 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
954 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
955 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
956 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
958 * For X tiling, tile() combines together the low-order bits of the X and Y
959 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
960 * bytes wide and 8 rows high:
962 * tile(x_tiled, X, Y, S) = A
963 * where A = tile_num << 12 | offset
964 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
965 * offset = (Y' & 0b111) << 9
966 * | (X & 0b111111111)
968 * Y' = Y + S * qpitch
969 * detile(x_tiled, A) = (X, Y, S)
973 * Y' = (tile_num / tile_pitch) << 3
974 * | (A & 0b111000000000) >> 9
975 * X' = (tile_num % tile_pitch) << 9
976 * | (A & 0b111111111)
978 * (In all tiling formulas, cpp is the number of bytes occupied by a single
979 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
980 * to fill the width of the surface, and qpitch is the spacing (in rows)
981 * between array slices).
983 * For Y tiling, tile() combines together the low-order bits of the X and Y
984 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
985 * bytes wide and 32 rows high:
987 * tile(y_tiled, X, Y, S) = A
988 * where A = tile_num << 12 | offset
989 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
990 * offset = (X' & 0b1110000) << 5
991 * | (Y' & 0b11111) << 4
994 * Y' = Y + S * qpitch
995 * detile(y_tiled, A) = (X, Y, S)
999 * Y' = (tile_num / tile_pitch) << 5
1000 * | (A & 0b111110000) >> 4
1001 * X' = (tile_num % tile_pitch) << 7
1002 * | (A & 0b111000000000) >> 5
1005 * For W tiling, tile() combines together the low-order bits of the X and Y
1006 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1007 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1008 * buffers, which always have cpp = 1 and S=0):
1010 * tile(w_tiled, X, Y, S) = A
1011 * where A = tile_num << 12 | offset
1012 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1013 * offset = (X' & 0b111000) << 6
1014 * | (Y' & 0b111100) << 3
1015 * | (X' & 0b100) << 2
1016 * | (Y' & 0b10) << 2
1017 * | (X' & 0b10) << 1
1021 * Y' = Y + S * qpitch
1022 * detile(w_tiled, A) = (X, Y, S)
1023 * where X = X' / cpp = X'
1024 * Y = Y' % qpitch = Y'
1025 * S = Y / qpitch = 0
1026 * Y' = (tile_num / tile_pitch) << 6
1027 * | (A & 0b111100000) >> 3
1028 * | (A & 0b1000) >> 2
1030 * X' = (tile_num % tile_pitch) << 6
1031 * | (A & 0b111000000000) >> 6
1032 * | (A & 0b10000) >> 2
1033 * | (A & 0b100) >> 1
1036 * Finally, for a non-tiled surface, tile() simply combines together the X and
1037 * Y coordinates in the natural way:
1039 * tile(untiled, X, Y, S) = A
1040 * where A = Y * pitch + X'
1042 * Y' = Y + S * qpitch
1043 * detile(untiled, A) = (X, Y, S)
1044 * where X = X' / cpp
1050 * (In these formulas, pitch is the number of bytes occupied by a single row
1054 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1055 const struct brw_blorp_blit_prog_key
*key
)
1057 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1058 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1061 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1062 /* If the destination image is W tiled and multisampled, then the thread
1063 * must be dispatched once per sample, not once per pixel. This is
1064 * necessary because after conversion between W and Y tiling, there's no
1065 * guarantee that all samples corresponding to a single pixel will still
1068 assert(key
->persample_msaa_dispatch
);
1072 /* We are blending, which means we won't have an opportunity to
1073 * translate the tiling and sample count for the texture surface. So
1074 * the surface state for the texture must be configured with the correct
1075 * tiling and sample count.
1077 assert(!key
->src_tiled_w
);
1078 assert(key
->tex_samples
== key
->src_samples
);
1079 assert(key
->tex_layout
== key
->src_layout
);
1080 assert(key
->tex_samples
> 0);
1083 if (key
->persample_msaa_dispatch
) {
1084 /* It only makes sense to do persample dispatch if the render target is
1085 * configured as multisampled.
1087 assert(key
->rt_samples
> 0);
1090 /* Make sure layout is consistent with sample count */
1091 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1092 (key
->tex_samples
<= 1));
1093 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1094 (key
->rt_samples
<= 1));
1095 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1096 (key
->src_samples
<= 1));
1097 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1098 (key
->dst_samples
<= 1));
1101 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1103 struct brw_blorp_blit_vars v
;
1104 brw_blorp_blit_vars_init(&b
, &v
, key
);
1106 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1108 /* Render target and texture hardware don't support W tiling until Gen8. */
1109 const bool rt_tiled_w
= false;
1110 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1112 /* The address that data will be written to is determined by the
1113 * coordinates supplied to the WM thread and the tiling and sample count of
1114 * the render target, according to the formula:
1116 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1118 * If the actual tiling and sample count of the destination surface are not
1119 * the same as the configuration of the render target, then these
1120 * coordinates are wrong and we have to adjust them to compensate for the
1123 if (rt_tiled_w
!= key
->dst_tiled_w
||
1124 key
->rt_samples
!= key
->dst_samples
||
1125 key
->rt_layout
!= key
->dst_layout
) {
1126 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1128 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1129 if (rt_tiled_w
!= key
->dst_tiled_w
)
1130 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1131 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1132 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1136 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1138 * That is: X, Y and S now contain the true coordinates and sample index of
1139 * the data that the WM thread should output.
1141 * If we need to kill pixels that are outside the destination rectangle,
1142 * now is the time to do it.
1144 if (key
->use_kill
) {
1145 assert(!(key
->blend
&& key
->blit_scaled
));
1146 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1149 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f(&b
, dst_pos
), &v
);
1150 if (dst_pos
->num_components
== 3) {
1151 /* The sample coordinate is an integer that we want left alone but
1152 * blorp_blit_apply_transform() blindly applies the transform to all
1153 * three coordinates. Grab the original sample index.
1155 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1156 nir_channel(&b
, src_pos
, 1),
1157 nir_channel(&b
, dst_pos
, 2));
1160 /* If the source image is not multisampled, then we want to fetch sample
1161 * number 0, because that's the only sample there is.
1163 if (key
->src_samples
== 1)
1164 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1166 /* X, Y, and S are now the coordinates of the pixel in the source image
1167 * that we want to texture from. Exception: if we are blending, then S is
1168 * irrelevant, because we are going to fetch all samples.
1170 if (key
->blend
&& !key
->blit_scaled
) {
1171 /* Resolves (effecively) use texelFetch, so we need integers and we
1172 * don't care about the sample index if we got one.
1174 src_pos
= nir_f2i(&b
, nir_channels(&b
, src_pos
, 0x3));
1176 if (devinfo
->gen
== 6) {
1177 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1178 * blending we need with a single linear-interpolated texture lookup
1179 * at the center of the sample. The texture coordinates to be odd
1180 * integers so that they correspond to the center of a 2x2 block
1181 * representing the four samples that maxe up a pixel. So we need
1182 * to multiply our X and Y coordinates each by 2 and then add 1.
1184 src_pos
= nir_ishl(&b
, src_pos
, nir_imm_int(&b
, 1));
1185 src_pos
= nir_iadd(&b
, src_pos
, nir_imm_int(&b
, 1));
1186 src_pos
= nir_i2f(&b
, src_pos
);
1187 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1189 /* Gen7+ hardware doesn't automaticaly blend. */
1190 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1192 key
->texture_data_type
);
1194 } else if (key
->blend
&& key
->blit_scaled
) {
1195 assert(!key
->use_kill
);
1196 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1198 if (key
->bilinear_filter
) {
1199 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1201 /* We're going to use texelFetch, so we need integers */
1202 if (src_pos
->num_components
== 2) {
1203 src_pos
= nir_f2i(&b
, src_pos
);
1205 assert(src_pos
->num_components
== 3);
1206 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i(&b
, src_pos
), 0),
1207 nir_channel(&b
, nir_f2i(&b
, src_pos
), 1),
1208 nir_channel(&b
, src_pos
, 2));
1211 /* We aren't blending, which means we just want to fetch a single
1212 * sample from the source surface. The address that we want to fetch
1213 * from is related to the X, Y and S values according to the formula:
1215 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1217 * If the actual tiling and sample count of the source surface are
1218 * not the same as the configuration of the texture, then we need to
1219 * adjust the coordinates to compensate for the difference.
1221 if (tex_tiled_w
!= key
->src_tiled_w
||
1222 key
->tex_samples
!= key
->src_samples
||
1223 key
->tex_layout
!= key
->src_layout
) {
1224 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1226 /* Now (X, Y, S) = detile(src_tiling, offset) */
1227 if (tex_tiled_w
!= key
->src_tiled_w
)
1228 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1229 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1230 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1234 if (key
->need_src_offset
)
1235 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1237 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1239 * In other words: X, Y, and S now contain values which, when passed to
1240 * the texturing unit, will cause data to be read from the correct
1241 * memory location. So we can fetch the texel now.
1243 if (key
->src_samples
== 1) {
1244 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1246 nir_ssa_def
*mcs
= NULL
;
1247 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1248 mcs
= blorp_nir_txf_ms_mcs(&b
, &v
, src_pos
);
1250 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1255 if (key
->dst_bpc
!= key
->src_bpc
)
1256 color
= bit_cast_color(&b
, color
, key
);
1259 /* The destination image is bound as a red texture three times as wide
1260 * as the actual image. Our shader is effectively running one color
1261 * component at a time. We need to pick off the appropriate component
1262 * from the source color and write that to destination red.
1264 assert(dst_pos
->num_components
== 2);
1266 nir_umod(&b
, nir_channel(&b
, dst_pos
, 0), nir_imm_int(&b
, 3));
1268 nir_ssa_def
*color_component
=
1269 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1270 nir_channel(&b
, color
, 0),
1271 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1272 nir_channel(&b
, color
, 1),
1273 nir_channel(&b
, color
, 2)));
1275 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1276 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1279 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1285 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1286 struct blorp_params
*params
,
1287 const struct brw_blorp_blit_prog_key
*prog_key
)
1289 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1290 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1293 void *mem_ctx
= ralloc_context(NULL
);
1295 const unsigned *program
;
1296 unsigned program_size
;
1297 struct brw_wm_prog_data prog_data
;
1299 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1300 struct brw_wm_prog_key wm_key
;
1301 brw_blorp_init_wm_prog_key(&wm_key
);
1302 wm_key
.tex
.compressed_multisample_layout_mask
=
1303 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1304 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1305 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1307 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1308 &prog_data
, &program_size
);
1310 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1311 program
, program_size
,
1312 &prog_data
.base
, sizeof(prog_data
),
1313 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1315 ralloc_free(mem_ctx
);
1319 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1320 GLfloat src0
, GLfloat src1
,
1321 GLfloat dst0
, GLfloat dst1
,
1324 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1326 /* When not mirroring a coordinate (say, X), we need:
1327 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1329 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1331 * blorp program uses "round toward zero" to convert the
1332 * transformed floating point coordinates to integer coordinates,
1333 * whereas the behaviour we actually want is "round to nearest",
1334 * so 0.5 provides the necessary correction.
1336 xform
->multiplier
= scale
;
1337 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1339 /* When mirroring X we need:
1340 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1342 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1344 xform
->multiplier
= -scale
;
1345 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1350 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1351 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1353 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1354 struct isl_extent2d px_size_sa
=
1355 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1356 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1357 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1358 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1359 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1361 *tile_x_px
= info
->tile_x_sa
;
1362 *tile_y_px
= info
->tile_y_sa
;
1367 surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1368 struct brw_blorp_surface_info
*info
)
1370 /* Just bail if we have nothing to do. */
1371 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1372 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1373 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1376 /* If this gets triggered then we've gotten here twice which. This
1377 * shouldn't happen thanks to the above early return.
1379 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1381 uint32_t layer
= 0, z
= 0;
1382 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1383 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1385 layer
= info
->view
.base_array_layer
;
1387 uint32_t x_offset_sa
, y_offset_sa
;
1388 isl_surf_get_image_offset_sa(&info
->surf
, info
->view
.base_level
,
1389 layer
, z
, &x_offset_sa
, &y_offset_sa
);
1391 uint32_t byte_offset
;
1392 isl_tiling_get_intratile_offset_sa(isl_dev
, info
->surf
.tiling
,
1393 info
->surf
.format
, info
->surf
.row_pitch
,
1394 x_offset_sa
, y_offset_sa
,
1396 &info
->tile_x_sa
, &info
->tile_y_sa
);
1397 info
->addr
.offset
+= byte_offset
;
1399 const uint32_t slice_width_px
=
1400 minify(info
->surf
.logical_level0_px
.width
, info
->view
.base_level
);
1401 const uint32_t slice_height_px
=
1402 minify(info
->surf
.logical_level0_px
.height
, info
->view
.base_level
);
1404 uint32_t tile_x_px
, tile_y_px
;
1405 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1407 struct isl_surf_init_info init_info
= {
1408 .dim
= ISL_SURF_DIM_2D
,
1409 .format
= info
->surf
.format
,
1410 .width
= slice_width_px
+ tile_x_px
,
1411 .height
= slice_height_px
+ tile_y_px
,
1415 .samples
= info
->surf
.samples
,
1416 .min_pitch
= info
->surf
.row_pitch
,
1417 .usage
= info
->surf
.usage
,
1418 .tiling_flags
= 1 << info
->surf
.tiling
,
1421 isl_surf_init_s(isl_dev
, &info
->surf
, &init_info
);
1422 assert(info
->surf
.row_pitch
== init_info
.min_pitch
);
1424 /* The view is also different now. */
1425 info
->view
.base_level
= 0;
1426 info
->view
.levels
= 1;
1427 info
->view
.base_array_layer
= 0;
1428 info
->view
.array_len
= 1;
1433 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1434 struct brw_blorp_surface_info
*info
)
1436 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1438 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1439 surf_convert_to_single_slice(isl_dev
, info
);
1441 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1442 info
->surf
.samples
= 1;
1443 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1447 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1448 struct brw_blorp_surface_info
*info
)
1450 assert(info
->surf
.tiling
== ISL_TILING_W
);
1452 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1453 surf_convert_to_single_slice(isl_dev
, info
);
1455 /* On gen7+, we don't have interleaved multisampling for color render
1456 * targets so we have to fake it.
1458 * TODO: Are we sure we don't also need to fake it on gen6?
1460 if (isl_dev
->info
->gen
> 6 &&
1461 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1462 surf_fake_interleaved_msaa(isl_dev
, info
);
1465 if (isl_dev
->info
->gen
== 6) {
1466 /* Gen6 stencil buffers have a very large alignment coming in from the
1467 * miptree. It's out-of-bounds for what the surface state can handle.
1468 * Since we have a single layer and level, it doesn't really matter as
1469 * long as we don't pass a bogus value into isl_surf_fill_state().
1471 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1474 /* Now that we've converted everything to a simple 2-D surface with only
1475 * one miplevel, we can go about retiling it.
1477 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1478 info
->surf
.tiling
= ISL_TILING_Y0
;
1479 info
->surf
.logical_level0_px
.width
=
1480 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1481 info
->surf
.logical_level0_px
.height
=
1482 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1483 info
->tile_x_sa
*= 2;
1484 info
->tile_y_sa
/= 2;
1488 double src0
, src1
, dst0
, dst1
;
1493 struct blt_axis x
, y
;
1497 do_blorp_blit(struct blorp_batch
*batch
,
1498 struct blorp_params
*params
,
1499 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1500 const struct blt_coords
*coords
)
1502 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1504 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1505 wm_prog_key
->texture_data_type
= nir_type_int
;
1506 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1507 wm_prog_key
->texture_data_type
= nir_type_uint
;
1509 wm_prog_key
->texture_data_type
= nir_type_float
;
1512 /* src_samples and dst_samples are the true sample counts */
1513 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1514 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1516 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1518 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1521 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1522 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1524 /* Round floating point values to nearest integer to avoid "off by one texel"
1525 * kind of errors when blitting.
1527 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1528 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1529 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1530 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1532 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1533 coords
->x
.src0
, coords
->x
.src1
,
1534 coords
->x
.dst0
, coords
->x
.dst1
,
1536 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1537 coords
->y
.src0
, coords
->y
.src1
,
1538 coords
->y
.dst0
, coords
->y
.dst1
,
1541 if (devinfo
->gen
> 6 &&
1542 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1543 assert(params
->dst
.surf
.samples
> 1);
1545 /* We must expand the rectangle we send through the rendering pipeline,
1546 * to account for the fact that we are mapping the destination region as
1547 * single-sampled when it is in fact multisampled. We must also align
1548 * it to a multiple of the multisampling pattern, because the
1549 * differences between multisampled and single-sampled surface formats
1550 * will mean that pixels are scrambled within the multisampling pattern.
1551 * TODO: what if this makes the coordinates too large?
1553 * Note: this only works if the destination surface uses the IMS layout.
1554 * If it's UMS, then we have no choice but to set up the rendering
1555 * pipeline as multisampled.
1557 struct isl_extent2d px_size_sa
=
1558 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1559 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1560 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1561 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1562 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1564 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1566 wm_prog_key
->use_kill
= true;
1567 wm_prog_key
->need_dst_offset
= true;
1570 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1571 /* We must modify the rectangle we send through the rendering pipeline
1572 * (and the size and x/y offset of the destination surface), to account
1573 * for the fact that we are mapping it as Y-tiled when it is in fact
1576 * Both Y tiling and W tiling can be understood as organizations of
1577 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1578 * is different, but the layout of the 32-byte sub-tiles within the 4k
1579 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1580 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1581 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1583 * Therefore, to account for the layout differences within the 32-byte
1584 * sub-tiles, we must expand the rectangle so the X coordinates of its
1585 * edges are multiples of 8 (the W sub-tile width), and its Y
1586 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1587 * Then we need to scale the X and Y coordinates of the rectangle to
1588 * account for the differences in aspect ratio between the Y and W
1589 * sub-tiles. We need to modify the layer width and height similarly.
1591 * A correction needs to be applied when MSAA is in use: since
1592 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1593 * we need to align the Y coordinates to multiples of 8, so that when
1594 * they are divided by two they are still multiples of 4.
1596 * Note: Since the x/y offset of the surface will be applied using the
1597 * SURFACE_STATE command packet, it will be invisible to the swizzling
1598 * code in the shader; therefore it needs to be in a multiple of the
1599 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1600 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1601 * buffer), and the miplevel alignment used for stencil buffers is 8
1602 * pixels horizontally and either 4 or 8 pixels vertically (see
1603 * intel_horizontal_texture_alignment_unit() and
1604 * intel_vertical_texture_alignment_unit()).
1606 * Note: Also, since the SURFACE_STATE command packet can only apply
1607 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1608 * vertically, it is important that the offsets will be multiples of
1609 * these sizes after they are converted into Y-tiled coordinates.
1610 * Fortunately they will be, since we know from above that the offsets
1611 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1612 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1614 * TODO: what if this makes the coordinates (or the texture size) too
1617 const unsigned x_align
= 8;
1618 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1619 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1620 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1621 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1622 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1624 /* Retile the surface to Y-tiled */
1625 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1627 wm_prog_key
->dst_tiled_w
= true;
1628 wm_prog_key
->use_kill
= true;
1629 wm_prog_key
->need_dst_offset
= true;
1631 if (params
->dst
.surf
.samples
> 1) {
1632 /* If the destination surface is a W-tiled multisampled stencil
1633 * buffer that we're mapping as Y tiled, then we need to arrange for
1634 * the WM program to run once per sample rather than once per pixel,
1635 * because the memory layout of related samples doesn't match between
1638 wm_prog_key
->persample_msaa_dispatch
= true;
1642 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1643 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1644 * Broadwell adds support for sampling from stencil.
1646 * See the comments above concerning x/y offset alignment for the
1647 * destination surface.
1649 * TODO: what if this makes the texture size too large?
1651 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1653 wm_prog_key
->src_tiled_w
= true;
1654 wm_prog_key
->need_src_offset
= true;
1657 /* tex_samples and rt_samples are the sample counts that are set up in
1660 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1661 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1663 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1664 * use to access the source and destination surfaces.
1666 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1667 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1669 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1670 /* We are blitting from a multisample buffer to a multisample buffer, so
1671 * we must preserve samples within a pixel. This means we have to
1672 * arrange for the WM program to run once per sample rather than once
1675 wm_prog_key
->persample_msaa_dispatch
= true;
1678 params
->num_samples
= params
->dst
.surf
.samples
;
1680 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
1681 assert(wm_prog_key
->need_src_offset
);
1682 surf_get_intratile_offset_px(¶ms
->src
,
1683 ¶ms
->wm_inputs
.src_offset
.x
,
1684 ¶ms
->wm_inputs
.src_offset
.y
);
1687 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
1688 assert(wm_prog_key
->need_dst_offset
);
1689 surf_get_intratile_offset_px(¶ms
->dst
,
1690 ¶ms
->wm_inputs
.dst_offset
.x
,
1691 ¶ms
->wm_inputs
.dst_offset
.y
);
1692 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
1693 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
1694 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
1695 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
1698 /* For some texture types, we need to pass the layer through the sampler. */
1699 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
1701 brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
);
1703 batch
->blorp
->exec(batch
, params
);
1707 blorp_blit(struct blorp_batch
*batch
,
1708 const struct blorp_surf
*src_surf
,
1709 unsigned src_level
, unsigned src_layer
,
1710 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
1711 const struct blorp_surf
*dst_surf
,
1712 unsigned dst_level
, unsigned dst_layer
,
1713 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
1714 float src_x0
, float src_y0
,
1715 float src_x1
, float src_y1
,
1716 float dst_x0
, float dst_y0
,
1717 float dst_x1
, float dst_y1
,
1718 GLenum filter
, bool mirror_x
, bool mirror_y
)
1720 struct blorp_params params
;
1721 blorp_params_init(¶ms
);
1723 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
1724 src_layer
, src_format
, false);
1725 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
1726 dst_layer
, dst_format
, true);
1728 params
.src
.view
.swizzle
= src_swizzle
;
1729 params
.dst
.view
.swizzle
= dst_swizzle
;
1731 struct brw_blorp_blit_prog_key wm_prog_key
= {
1732 .shader_type
= BLORP_SHADER_TYPE_BLIT
1735 /* Scaled blitting or not. */
1736 wm_prog_key
.blit_scaled
=
1737 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
1738 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
1740 /* Scaling factors used for bilinear filtering in multisample scaled
1743 if (params
.src
.surf
.samples
== 16)
1744 wm_prog_key
.x_scale
= 4.0f
;
1746 wm_prog_key
.x_scale
= 2.0f
;
1747 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
1749 if (filter
== GL_LINEAR
&&
1750 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1)
1751 wm_prog_key
.bilinear_filter
= true;
1753 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
1754 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
1755 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
1756 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
1757 /* We are downsampling a non-integer color buffer, so blend.
1759 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
1761 * "If the source formats are integer types or stencil values, a
1762 * single sample's value is selected for each pixel."
1764 * This implies we should not blend in that case.
1766 wm_prog_key
.blend
= true;
1769 params
.wm_inputs
.rect_grid
.x1
=
1770 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
1771 wm_prog_key
.x_scale
- 1.0f
;
1772 params
.wm_inputs
.rect_grid
.y1
=
1773 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
1774 wm_prog_key
.y_scale
- 1.0f
;
1776 struct blt_coords coords
= {
1793 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
1796 static enum isl_format
1797 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
1799 /* The choice of UNORM and UINT formats is very intentional here. Most
1800 * of the time, we want to use a UINT format to avoid any rounding error
1801 * in the blit. For stencil blits, R8_UINT is required by the hardware.
1802 * (It's the only format allowed in conjunction with W-tiling.) Also we
1803 * intentionally use the 4-channel formats whenever we can. This is so
1804 * that, when we do a RGB <-> RGBX copy, the two formats will line up
1805 * even though one of them is 3/4 the size of the other. The choice of
1806 * UNORM vs. UINT is also very intentional because we don't have 8 or
1807 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
1808 * Fortunately, the only time we should ever use two different formats in
1809 * the table below is for RGB -> RGBA blits and so we will never have any
1810 * UNORM/UINT mismatch.
1812 if (ISL_DEV_GEN(isl_dev
) >= 9) {
1814 case 8: return ISL_FORMAT_R8_UINT
;
1815 case 16: return ISL_FORMAT_R8G8_UINT
;
1816 case 24: return ISL_FORMAT_R8G8B8_UINT
;
1817 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
1818 case 48: return ISL_FORMAT_R16G16B16_UINT
;
1819 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
1820 case 96: return ISL_FORMAT_R32G32B32_UINT
;
1821 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
1823 unreachable("Unknown format bpb");
1827 case 8: return ISL_FORMAT_R8_UINT
;
1828 case 16: return ISL_FORMAT_R8G8_UINT
;
1829 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
1830 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
1831 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
1832 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
1833 case 96: return ISL_FORMAT_R32G32B32_UINT
;
1834 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
1836 unreachable("Unknown format bpb");
1841 /** Returns a UINT format that is CCS-compatible with the given format
1843 * The PRM's say absolutely nothing about how render compression works. The
1844 * only thing they provide is a list of formats on which it is and is not
1845 * supported. Empirical testing indicates that the compression is only based
1846 * on the bit-layout of the format and the channel encoding doesn't matter.
1847 * So, while texture views don't work in general, you can create a view as
1848 * long as the bit-layout of the formats are the same.
1850 * Fortunately, for every render compression capable format, the UINT format
1851 * with the same bit layout also supports render compression. This means that
1852 * we only need to handle UINT formats for copy operations. In order to do
1853 * copies between formats with different bit layouts, we attach both with a
1854 * UINT format and use bit_cast_color() to generate code to do the bit-cast
1855 * operation between the two bit layouts.
1857 static enum isl_format
1858 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
1860 switch (fmtl
->format
) {
1861 case ISL_FORMAT_R32G32B32A32_FLOAT
:
1862 case ISL_FORMAT_R32G32B32A32_SINT
:
1863 case ISL_FORMAT_R32G32B32A32_UINT
:
1864 case ISL_FORMAT_R32G32B32A32_UNORM
:
1865 case ISL_FORMAT_R32G32B32A32_SNORM
:
1866 return ISL_FORMAT_R32G32B32A32_UINT
;
1868 case ISL_FORMAT_R16G16B16A16_UNORM
:
1869 case ISL_FORMAT_R16G16B16A16_SNORM
:
1870 case ISL_FORMAT_R16G16B16A16_SINT
:
1871 case ISL_FORMAT_R16G16B16A16_UINT
:
1872 case ISL_FORMAT_R16G16B16A16_FLOAT
:
1873 case ISL_FORMAT_R16G16B16X16_UNORM
:
1874 case ISL_FORMAT_R16G16B16X16_FLOAT
:
1875 return ISL_FORMAT_R16G16B16A16_UINT
;
1877 case ISL_FORMAT_R32G32_FLOAT
:
1878 case ISL_FORMAT_R32G32_SINT
:
1879 case ISL_FORMAT_R32G32_UINT
:
1880 case ISL_FORMAT_R32G32_UNORM
:
1881 case ISL_FORMAT_R32G32_SNORM
:
1882 return ISL_FORMAT_R32G32_UINT
;
1884 case ISL_FORMAT_B8G8R8A8_UNORM
:
1885 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
1886 case ISL_FORMAT_R8G8B8A8_UNORM
:
1887 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
1888 case ISL_FORMAT_R8G8B8A8_SNORM
:
1889 case ISL_FORMAT_R8G8B8A8_SINT
:
1890 case ISL_FORMAT_R8G8B8A8_UINT
:
1891 case ISL_FORMAT_B8G8R8X8_UNORM
:
1892 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
1893 case ISL_FORMAT_R8G8B8X8_UNORM
:
1894 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
1895 return ISL_FORMAT_R8G8B8A8_UINT
;
1897 case ISL_FORMAT_R16G16_UNORM
:
1898 case ISL_FORMAT_R16G16_SNORM
:
1899 case ISL_FORMAT_R16G16_SINT
:
1900 case ISL_FORMAT_R16G16_UINT
:
1901 case ISL_FORMAT_R16G16_FLOAT
:
1902 return ISL_FORMAT_R16G16_UINT
;
1904 case ISL_FORMAT_R32_SINT
:
1905 case ISL_FORMAT_R32_UINT
:
1906 case ISL_FORMAT_R32_FLOAT
:
1907 case ISL_FORMAT_R32_UNORM
:
1908 case ISL_FORMAT_R32_SNORM
:
1909 return ISL_FORMAT_R32_UINT
;
1912 unreachable("Not a compressible format");
1917 surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
1918 struct brw_blorp_surface_info
*info
,
1919 uint32_t *x
, uint32_t *y
,
1920 uint32_t *width
, uint32_t *height
)
1922 const struct isl_format_layout
*fmtl
=
1923 isl_format_get_layout(info
->surf
.format
);
1925 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
1927 /* This is a compressed surface. We need to convert it to a single
1928 * slice (because compressed layouts don't perfectly match uncompressed
1929 * ones with the same bpb) and divide x, y, width, and height by the
1932 surf_convert_to_single_slice(isl_dev
, info
);
1934 if (width
|| height
) {
1936 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
1937 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
1938 assert(*width
% fmtl
->bw
== 0 ||
1939 right_edge_px
== info
->surf
.logical_level0_px
.width
);
1940 assert(*height
% fmtl
->bh
== 0 ||
1941 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
1943 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
1944 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
1947 assert(*x
% fmtl
->bw
== 0);
1948 assert(*y
% fmtl
->bh
== 0);
1952 info
->surf
.logical_level0_px
.width
=
1953 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
1954 info
->surf
.logical_level0_px
.height
=
1955 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
1957 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
1958 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
1959 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
1960 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
1962 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
1963 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
1964 info
->tile_x_sa
/= fmtl
->bw
;
1965 info
->tile_y_sa
/= fmtl
->bh
;
1967 /* It's now an uncompressed surface so we need an uncompressed format */
1968 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
1972 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1973 struct brw_blorp_surface_info
*info
,
1974 uint32_t *x
, uint32_t *width
)
1976 surf_convert_to_single_slice(isl_dev
, info
);
1978 info
->surf
.logical_level0_px
.width
*= 3;
1979 info
->surf
.phys_level0_sa
.width
*= 3;
1983 enum isl_format red_format
;
1984 switch (info
->view
.format
) {
1985 case ISL_FORMAT_R8G8B8_UNORM
:
1986 red_format
= ISL_FORMAT_R8_UNORM
;
1988 case ISL_FORMAT_R8G8B8_UINT
:
1989 red_format
= ISL_FORMAT_R8_UINT
;
1991 case ISL_FORMAT_R16G16B16_UNORM
:
1992 red_format
= ISL_FORMAT_R16_UNORM
;
1994 case ISL_FORMAT_R16G16B16_UINT
:
1995 red_format
= ISL_FORMAT_R16_UINT
;
1997 case ISL_FORMAT_R32G32B32_UINT
:
1998 red_format
= ISL_FORMAT_R32_UINT
;
2001 unreachable("Invalid RGB copy destination format");
2003 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
2004 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
2005 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
2006 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
2008 info
->surf
.format
= info
->view
.format
= red_format
;
2012 blorp_copy(struct blorp_batch
*batch
,
2013 const struct blorp_surf
*src_surf
,
2014 unsigned src_level
, unsigned src_layer
,
2015 const struct blorp_surf
*dst_surf
,
2016 unsigned dst_level
, unsigned dst_layer
,
2017 uint32_t src_x
, uint32_t src_y
,
2018 uint32_t dst_x
, uint32_t dst_y
,
2019 uint32_t src_width
, uint32_t src_height
)
2021 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2022 struct blorp_params params
;
2024 if (src_width
== 0 || src_height
== 0)
2027 blorp_params_init(¶ms
);
2028 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2029 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2030 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2031 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2033 struct brw_blorp_blit_prog_key wm_prog_key
= {
2034 .shader_type
= BLORP_SHADER_TYPE_BLIT
2037 const struct isl_format_layout
*src_fmtl
=
2038 isl_format_get_layout(params
.src
.surf
.format
);
2039 const struct isl_format_layout
*dst_fmtl
=
2040 isl_format_get_layout(params
.dst
.surf
.format
);
2042 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2043 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2044 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2045 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2046 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2047 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2049 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2050 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2051 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2052 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2053 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2054 params
.src
.view
.format
= params
.dst
.view
.format
;
2056 params
.src
.view
.format
=
2057 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2059 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2060 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2061 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2062 params
.dst
.view
.format
= params
.src
.view
.format
;
2064 params
.dst
.view
.format
=
2065 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2068 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2069 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2072 wm_prog_key
.src_bpc
=
2073 isl_format_get_layout(params
.src
.view
.format
)->channels
.r
.bits
;
2074 wm_prog_key
.dst_bpc
=
2075 isl_format_get_layout(params
.dst
.view
.format
)->channels
.r
.bits
;
2077 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2078 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2079 &src_x
, &src_y
, &src_width
, &src_height
);
2080 wm_prog_key
.need_src_offset
= true;
2083 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2084 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2085 &dst_x
, &dst_y
, NULL
, NULL
);
2086 wm_prog_key
.need_dst_offset
= true;
2089 /* Once both surfaces are stompped to uncompressed as needed, the
2090 * destination size is the same as the source size.
2092 uint32_t dst_width
= src_width
;
2093 uint32_t dst_height
= src_height
;
2095 if (dst_fmtl
->bpb
% 3 == 0) {
2096 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2097 &dst_x
, &dst_width
);
2098 wm_prog_key
.dst_rgb
= true;
2099 wm_prog_key
.need_dst_offset
= true;
2102 struct blt_coords coords
= {
2105 .src1
= src_x
+ src_width
,
2107 .dst1
= dst_x
+ dst_width
,
2112 .src1
= src_y
+ src_height
,
2114 .dst1
= dst_y
+ dst_height
,
2119 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);