2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/nir/nir_builder.h"
26 #include "blorp_priv.h"
27 #include "brw_meta_util.h"
29 #define FILE_DEBUG_FLAG DEBUG_BLORP
31 static const bool split_blorp_blit_debug
= false;
34 * Enum to specify the order of arguments in a sampler message
36 enum sampler_message_arg
38 SAMPLER_MESSAGE_ARG_U_FLOAT
,
39 SAMPLER_MESSAGE_ARG_V_FLOAT
,
40 SAMPLER_MESSAGE_ARG_U_INT
,
41 SAMPLER_MESSAGE_ARG_V_INT
,
42 SAMPLER_MESSAGE_ARG_R_INT
,
43 SAMPLER_MESSAGE_ARG_SI_INT
,
44 SAMPLER_MESSAGE_ARG_MCS_INT
,
45 SAMPLER_MESSAGE_ARG_ZERO_INT
,
48 struct brw_blorp_blit_vars
{
49 /* Input values from brw_blorp_wm_inputs */
50 nir_variable
*v_discard_rect
;
51 nir_variable
*v_rect_grid
;
52 nir_variable
*v_coord_transform
;
53 nir_variable
*v_src_z
;
54 nir_variable
*v_src_offset
;
55 nir_variable
*v_dst_offset
;
58 nir_variable
*frag_coord
;
61 nir_variable
*color_out
;
65 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
66 const struct brw_blorp_blit_prog_key
*key
)
68 /* Blended and scaled blits never use pixel discard. */
69 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
71 #define LOAD_INPUT(name, type)\
72 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
74 LOAD_INPUT(discard_rect
, glsl_vec4_type())
75 LOAD_INPUT(rect_grid
, glsl_vec4_type())
76 LOAD_INPUT(coord_transform
, glsl_vec4_type())
77 LOAD_INPUT(src_z
, glsl_uint_type())
78 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
79 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
83 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
84 glsl_vec4_type(), "gl_FragCoord");
85 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
86 v
->frag_coord
->data
.origin_upper_left
= true;
88 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
89 glsl_vec4_type(), "gl_FragColor");
90 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
94 blorp_blit_get_frag_coords(nir_builder
*b
,
95 const struct brw_blorp_blit_prog_key
*key
,
96 struct brw_blorp_blit_vars
*v
)
98 nir_ssa_def
*coord
= nir_f2i(b
, nir_load_var(b
, v
->frag_coord
));
100 /* Account for destination surface intratile offset
102 * Transformation parameters giving translation from destination to source
103 * coordinates don't take into account possible intra-tile destination
104 * offset. Therefore it has to be first subtracted from the incoming
105 * coordinates. Vertices are set up based on coordinates containing the
108 if (key
->need_dst_offset
)
109 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
111 if (key
->persample_msaa_dispatch
) {
112 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
113 nir_load_sample_id(b
));
115 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
120 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
124 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
125 struct brw_blorp_blit_vars
*v
)
127 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
129 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
130 nir_channel(b
, coord_transform
, 3));
131 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
132 nir_channel(b
, coord_transform
, 2));
134 return nir_ffma(b
, src_pos
, mul
, offset
);
138 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
139 struct brw_blorp_blit_vars
*v
)
141 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
142 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
143 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
144 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
145 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
146 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
148 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
149 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
150 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
151 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
153 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
155 nir_intrinsic_instr
*discard
=
156 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
157 discard
->src
[0] = nir_src_for_ssa(oob
);
158 nir_builder_instr_insert(b
, &discard
->instr
);
161 static nir_tex_instr
*
162 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
163 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
164 nir_alu_type dst_type
)
166 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
170 tex
->dest_type
= dst_type
;
171 tex
->is_array
= false;
172 tex
->is_shadow
= false;
174 /* Blorp only has one texture and it's bound at unit 0 */
177 tex
->texture_index
= 0;
178 tex
->sampler_index
= 0;
180 /* To properly handle 3-D and 2-D array textures, we pull the Z component
181 * from an input. TODO: This is a bit magic; we should probably make this
182 * more explicit in the future.
184 assert(pos
->num_components
>= 2);
185 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
186 nir_load_var(b
, v
->v_src_z
));
188 tex
->src
[0].src_type
= nir_tex_src_coord
;
189 tex
->src
[0].src
= nir_src_for_ssa(pos
);
190 tex
->coord_components
= 3;
192 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
198 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
199 nir_ssa_def
*pos
, nir_alu_type dst_type
)
202 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2, dst_type
);
204 assert(pos
->num_components
== 2);
205 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
206 tex
->src
[1].src_type
= nir_tex_src_lod
;
207 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
209 nir_builder_instr_insert(b
, &tex
->instr
);
211 return &tex
->dest
.ssa
;
215 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
216 nir_ssa_def
*pos
, nir_alu_type dst_type
)
219 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
221 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
222 tex
->src
[1].src_type
= nir_tex_src_lod
;
223 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
225 nir_builder_instr_insert(b
, &tex
->instr
);
227 return &tex
->dest
.ssa
;
231 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
232 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
235 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
236 mcs
!= NULL
? 3 : 2, dst_type
);
238 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
240 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
241 if (pos
->num_components
== 2) {
242 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
244 assert(pos
->num_components
== 3);
245 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
249 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
250 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
253 nir_builder_instr_insert(b
, &tex
->instr
);
255 return &tex
->dest
.ssa
;
259 blorp_nir_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
, nir_ssa_def
*pos
)
262 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
263 pos
, 1, nir_type_int
);
265 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
267 nir_builder_instr_insert(b
, &tex
->instr
);
269 return &tex
->dest
.ssa
;
273 nir_mask_shift_or(struct nir_builder
*b
, nir_ssa_def
*dst
, nir_ssa_def
*src
,
274 uint32_t src_mask
, int src_left_shift
)
276 nir_ssa_def
*masked
= nir_iand(b
, src
, nir_imm_int(b
, src_mask
));
278 nir_ssa_def
*shifted
;
279 if (src_left_shift
> 0) {
280 shifted
= nir_ishl(b
, masked
, nir_imm_int(b
, src_left_shift
));
281 } else if (src_left_shift
< 0) {
282 shifted
= nir_ushr(b
, masked
, nir_imm_int(b
, -src_left_shift
));
284 assert(src_left_shift
== 0);
288 return nir_ior(b
, dst
, shifted
);
292 * Emit code to compensate for the difference between Y and W tiling.
294 * This code modifies the X and Y coordinates according to the formula:
296 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
298 * (See brw_blorp_build_nir_shader).
300 static inline nir_ssa_def
*
301 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
303 assert(pos
->num_components
== 2);
304 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
305 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
307 /* Given X and Y coordinates that describe an address using Y tiling,
308 * translate to the X and Y coordinates that describe the same address
311 * If we break down the low order bits of X and Y, using a
312 * single letter to represent each low-order bit:
314 * X = A << 7 | 0bBCDEFGH
315 * Y = J << 5 | 0bKLMNP (1)
317 * Then we can apply the Y tiling formula to see the memory offset being
320 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
322 * If we apply the W detiling formula to this memory location, that the
323 * corresponding X' and Y' coordinates are:
325 * X' = A << 6 | 0bBCDPFH (3)
326 * Y' = J << 6 | 0bKLMNEG
328 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
329 * we need to make the following computation:
331 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
332 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
334 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
335 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
336 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
337 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
339 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
340 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
341 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
342 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
344 return nir_vec2(b
, x_W
, y_W
);
348 * Emit code to compensate for the difference between Y and W tiling.
350 * This code modifies the X and Y coordinates according to the formula:
352 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
354 * (See brw_blorp_build_nir_shader).
356 static inline nir_ssa_def
*
357 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
359 assert(pos
->num_components
== 2);
360 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
361 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
363 /* Applying the same logic as above, but in reverse, we obtain the
366 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
367 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
369 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
370 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
371 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
372 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
373 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
375 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
376 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
377 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
379 return nir_vec2(b
, x_Y
, y_Y
);
383 * Emit code to compensate for the difference between MSAA and non-MSAA
386 * This code modifies the X and Y coordinates according to the formula:
388 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
390 * (See brw_blorp_blit_program).
392 static inline nir_ssa_def
*
393 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
394 unsigned num_samples
, enum isl_msaa_layout layout
)
396 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
399 case ISL_MSAA_LAYOUT_NONE
:
400 assert(pos
->num_components
== 2);
402 case ISL_MSAA_LAYOUT_ARRAY
:
403 /* No translation needed */
405 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
406 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
407 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
408 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
409 nir_channel(b
, pos
, 2);
411 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
412 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
413 switch (num_samples
) {
416 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
417 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
420 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
421 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
422 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
424 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
425 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
426 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
427 if (num_samples
== 2) {
430 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
431 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
432 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
437 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
438 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
440 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
442 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
443 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
444 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
445 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
446 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
447 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
448 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
452 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
453 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
455 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
458 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
459 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
460 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
461 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
462 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
463 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
464 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
465 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
469 unreachable("Invalid number of samples for IMS layout");
472 return nir_vec2(b
, x_out
, y_out
);
476 unreachable("Invalid MSAA layout");
481 * Emit code to compensate for the difference between MSAA and non-MSAA
484 * This code modifies the X and Y coordinates according to the formula:
486 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
488 * (See brw_blorp_blit_program).
490 static inline nir_ssa_def
*
491 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
492 unsigned num_samples
, enum isl_msaa_layout layout
)
494 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
497 case ISL_MSAA_LAYOUT_NONE
:
498 /* No translation necessary, and S should already be zero. */
499 assert(pos
->num_components
== 2);
501 case ISL_MSAA_LAYOUT_ARRAY
:
502 /* No translation necessary. */
504 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
505 assert(pos
->num_components
== 2);
507 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
508 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
510 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
511 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
512 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
513 switch (num_samples
) {
516 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
517 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
518 * S = (X & 0b10) >> 1
520 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
521 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
522 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
523 * S = (Y & 0b10) | (X & 0b10) >> 1
525 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
526 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
527 if (num_samples
== 2) {
529 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
531 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
532 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
533 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
534 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
539 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
540 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
541 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
542 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
544 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
545 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
546 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
547 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
548 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
549 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
550 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
554 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
555 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
556 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
557 * S = (Y & 0b100) << 1 | (X & 0b100) |
558 * (Y & 0b10) | (X & 0b10) >> 1
560 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
561 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
562 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
563 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
564 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
565 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
566 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
567 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
571 unreachable("Invalid number of samples for IMS layout");
574 return nir_vec3(b
, x_out
, y_out
, s_out
);
578 unreachable("Invalid MSAA layout");
583 * Count the number of trailing 1 bits in the given value. For example:
585 * count_trailing_one_bits(0) == 0
586 * count_trailing_one_bits(7) == 3
587 * count_trailing_one_bits(11) == 2
589 static inline int count_trailing_one_bits(unsigned value
)
591 #ifdef HAVE___BUILTIN_CTZ
592 return __builtin_ctz(~value
);
594 return _mesa_bitcount(value
& ~(value
+ 1));
599 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
600 nir_ssa_def
*pos
, unsigned tex_samples
,
601 enum isl_aux_usage tex_aux_usage
,
602 nir_alu_type dst_type
)
604 /* If non-null, this is the outer-most if statement */
605 nir_if
*outer_if
= NULL
;
607 nir_variable
*color
=
608 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
610 nir_ssa_def
*mcs
= NULL
;
611 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
612 mcs
= blorp_nir_txf_ms_mcs(b
, v
, pos
);
614 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
616 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
618 * This ensures that when all samples have the same value, no numerical
619 * precision is lost, since each addition operation always adds two equal
620 * values, and summing two equal floating point values does not lose
623 * We perform this computation by treating the texture_data array as a
624 * stack and performing the following operations:
626 * - push sample 0 onto stack
627 * - push sample 1 onto stack
628 * - add top two stack entries
629 * - push sample 2 onto stack
630 * - push sample 3 onto stack
631 * - add top two stack entries
632 * - add top two stack entries
633 * - divide top stack entry by 4
635 * Note that after pushing sample i onto the stack, the number of add
636 * operations we do is equal to the number of trailing 1 bits in i. This
637 * works provided the total number of samples is a power of two, which it
638 * always is for i965.
640 * For integer formats, we replace the add operations with average
641 * operations and skip the final division.
643 nir_ssa_def
*texture_data
[5];
644 unsigned stack_depth
= 0;
645 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
646 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
648 /* Push sample i onto the stack */
649 assert(stack_depth
< ARRAY_SIZE(texture_data
));
651 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
652 nir_channel(b
, pos
, 1),
654 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
656 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
657 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
658 * suggests an optimization:
660 * "A simple optimization with probable large return in
661 * performance is to compare the MCS value to zero (indicating
662 * all samples are on sample slice 0), and sample only from
663 * sample slice 0 using ld2dss if MCS is zero."
665 * Note that in the case where the MCS value is zero, sampling from
666 * sample slice 0 using ld2dss and sampling from sample 0 using
667 * ld2dms are equivalent (since all samples are on sample slice 0).
668 * Since we have already sampled from sample 0, all we need to do is
669 * skip the remaining fetches and averaging if MCS is zero.
671 nir_ssa_def
*mcs_zero
=
672 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
673 if (tex_samples
== 16) {
674 mcs_zero
= nir_iand(b
, mcs_zero
,
675 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
678 nir_if
*if_stmt
= nir_if_create(b
->shader
);
679 if_stmt
->condition
= nir_src_for_ssa(mcs_zero
);
680 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
682 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
683 nir_store_var(b
, color
, texture_data
[0], 0xf);
685 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
689 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
690 assert(stack_depth
>= 2);
693 assert(dst_type
== nir_type_float
);
694 texture_data
[stack_depth
- 1] =
695 nir_fadd(b
, texture_data
[stack_depth
- 1],
696 texture_data
[stack_depth
]);
700 /* We should have just 1 sample on the stack now. */
701 assert(stack_depth
== 1);
703 texture_data
[0] = nir_fmul(b
, texture_data
[0],
704 nir_imm_float(b
, 1.0 / tex_samples
));
706 nir_store_var(b
, color
, texture_data
[0], 0xf);
709 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
711 return nir_load_var(b
, color
);
714 static inline nir_ssa_def
*
715 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
719 memset(&v
, 0, sizeof(v
));
723 return nir_build_imm(build
, 4, 32, v
);
727 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
728 unsigned tex_samples
,
729 const struct brw_blorp_blit_prog_key
*key
,
730 struct brw_blorp_blit_vars
*v
)
732 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
733 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
734 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
736 /* Translate coordinates to lay out the samples in a rectangular grid
737 * roughly corresponding to sample locations.
739 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
740 /* Adjust coordinates so that integers represent pixel centers rather
743 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
744 /* Clamp the X, Y texture coordinates to properly handle the sampling of
745 * texels on texture edges.
747 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
748 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
749 nir_channel(b
, rect_grid
, 1)));
751 /* Store the fractional parts to be used as bilinear interpolation
754 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
755 /* Round the float coordinates down to nearest integer */
756 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
758 nir_ssa_def
*tex_data
[4];
759 for (unsigned i
= 0; i
< 4; ++i
) {
760 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
761 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
762 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
764 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
765 nir_ssa_def
*sample_coords_int
= nir_f2i(b
, sample_coords
);
767 /* The MCS value we fetch has to match up with the pixel that we're
768 * sampling from. Since we sample from different pixels in each
769 * iteration of this "for" loop, the call to mcs_fetch() should be
770 * here inside the loop after computing the pixel coordinates.
772 nir_ssa_def
*mcs
= NULL
;
773 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
774 mcs
= blorp_nir_txf_ms_mcs(b
, v
, sample_coords_int
);
776 /* Compute sample index and map the sample index to a sample number.
777 * Sample index layout shows the numbering of slots in a rectangular
778 * grid of samples with in a pixel. Sample number layout shows the
779 * rectangular grid of samples roughly corresponding to the real sample
780 * locations with in a pixel.
781 * In case of 4x MSAA, layout of sample indices matches the layout of
789 * In case of 8x MSAA the two layouts don't match.
790 * sample index layout : --------- sample number layout : ---------
791 * | 0 | 1 | | 3 | 7 |
792 * --------- ---------
793 * | 2 | 3 | | 5 | 0 |
794 * --------- ---------
795 * | 4 | 5 | | 1 | 2 |
796 * --------- ---------
797 * | 6 | 7 | | 4 | 6 |
798 * --------- ---------
800 * Fortunately, this can be done fairly easily as:
801 * S' = (0x17306425 >> (S * 4)) & 0xf
803 * In the case of 16x MSAA the two layouts don't match.
804 * Sample index layout: Sample number layout:
805 * --------------------- ---------------------
806 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
807 * --------------------- ---------------------
808 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
809 * --------------------- ---------------------
810 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
811 * --------------------- ---------------------
812 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
813 * --------------------- ---------------------
815 * This is equivalent to
816 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
818 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
819 nir_ssa_def
*sample
=
820 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
821 key
->x_scale
* key
->y_scale
));
822 sample
= nir_f2i(b
, sample
);
824 if (tex_samples
== 8) {
825 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
826 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
827 nir_imm_int(b
, 0xf));
828 } else if (tex_samples
== 16) {
829 nir_ssa_def
*sample_low
=
830 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
831 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
832 nir_imm_int(b
, 0xf));
833 nir_ssa_def
*sample_high
=
834 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
835 nir_ishl(b
, nir_iadd(b
, sample
,
838 nir_imm_int(b
, 0xf));
840 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
841 sample_low
, sample_high
);
843 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
844 nir_channel(b
, sample_coords_int
, 1),
846 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
849 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
850 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
851 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
852 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
856 /** Perform a color bit-cast operation
858 * For copy operations involving CCS, we may need to use different formats for
859 * the source and destination surfaces. The two formats must both be UINT
860 * formats and must have the same size but may have different bit layouts.
861 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
862 * to R16G16_UINT. This function generates code to shuffle bits around to get
863 * us from one to the other.
866 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
867 const struct brw_blorp_blit_prog_key
*key
)
869 assert(key
->texture_data_type
== nir_type_uint
);
871 if (key
->dst_bpc
> key
->src_bpc
) {
872 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
873 nir_ssa_def
*dst_chan
[2] = { u
, u
};
875 unsigned dst_idx
= 0;
876 for (unsigned i
= 0; i
< 4; i
++) {
877 nir_ssa_def
*shifted
= nir_ishl(b
, nir_channel(b
, color
, i
),
878 nir_imm_int(b
, shift
));
880 dst_chan
[dst_idx
] = shifted
;
882 dst_chan
[dst_idx
] = nir_ior(b
, dst_chan
[dst_idx
], shifted
);
885 shift
+= key
->src_bpc
;
886 if (shift
>= key
->dst_bpc
) {
892 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], u
, u
);
894 assert(key
->dst_bpc
< key
->src_bpc
);
896 nir_ssa_def
*mask
= nir_imm_int(b
, ~0u >> (32 - key
->dst_bpc
));
898 nir_ssa_def
*dst_chan
[4];
899 unsigned src_idx
= 0;
901 for (unsigned i
= 0; i
< 4; i
++) {
902 dst_chan
[i
] = nir_iand(b
, nir_ushr(b
, nir_channel(b
, color
, src_idx
),
903 nir_imm_int(b
, shift
)),
905 shift
+= key
->dst_bpc
;
906 if (shift
>= key
->src_bpc
) {
912 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], dst_chan
[2], dst_chan
[3]);
917 * Generator for WM programs used in BLORP blits.
919 * The bulk of the work done by the WM program is to wrap and unwrap the
920 * coordinate transformations used by the hardware to store surfaces in
921 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
922 * sample index for a multisampled surface) to a memory offset by the
923 * following formulas:
925 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
926 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
928 * For a single-sampled surface, or for a multisampled surface using
929 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
932 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
933 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
934 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
935 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
937 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
938 * embeds the sample number into bit 1 of the X and Y coordinates:
940 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
941 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
942 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
943 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
944 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
945 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
946 * S = (Y & 0b10) | (X & 0b10) >> 1
948 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
949 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
952 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
953 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
954 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
955 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
956 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
957 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
958 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
960 * For X tiling, tile() combines together the low-order bits of the X and Y
961 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
962 * bytes wide and 8 rows high:
964 * tile(x_tiled, X, Y, S) = A
965 * where A = tile_num << 12 | offset
966 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
967 * offset = (Y' & 0b111) << 9
968 * | (X & 0b111111111)
970 * Y' = Y + S * qpitch
971 * detile(x_tiled, A) = (X, Y, S)
975 * Y' = (tile_num / tile_pitch) << 3
976 * | (A & 0b111000000000) >> 9
977 * X' = (tile_num % tile_pitch) << 9
978 * | (A & 0b111111111)
980 * (In all tiling formulas, cpp is the number of bytes occupied by a single
981 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
982 * to fill the width of the surface, and qpitch is the spacing (in rows)
983 * between array slices).
985 * For Y tiling, tile() combines together the low-order bits of the X and Y
986 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
987 * bytes wide and 32 rows high:
989 * tile(y_tiled, X, Y, S) = A
990 * where A = tile_num << 12 | offset
991 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
992 * offset = (X' & 0b1110000) << 5
993 * | (Y' & 0b11111) << 4
996 * Y' = Y + S * qpitch
997 * detile(y_tiled, A) = (X, Y, S)
1001 * Y' = (tile_num / tile_pitch) << 5
1002 * | (A & 0b111110000) >> 4
1003 * X' = (tile_num % tile_pitch) << 7
1004 * | (A & 0b111000000000) >> 5
1007 * For W tiling, tile() combines together the low-order bits of the X and Y
1008 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1009 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1010 * buffers, which always have cpp = 1 and S=0):
1012 * tile(w_tiled, X, Y, S) = A
1013 * where A = tile_num << 12 | offset
1014 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1015 * offset = (X' & 0b111000) << 6
1016 * | (Y' & 0b111100) << 3
1017 * | (X' & 0b100) << 2
1018 * | (Y' & 0b10) << 2
1019 * | (X' & 0b10) << 1
1023 * Y' = Y + S * qpitch
1024 * detile(w_tiled, A) = (X, Y, S)
1025 * where X = X' / cpp = X'
1026 * Y = Y' % qpitch = Y'
1027 * S = Y / qpitch = 0
1028 * Y' = (tile_num / tile_pitch) << 6
1029 * | (A & 0b111100000) >> 3
1030 * | (A & 0b1000) >> 2
1032 * X' = (tile_num % tile_pitch) << 6
1033 * | (A & 0b111000000000) >> 6
1034 * | (A & 0b10000) >> 2
1035 * | (A & 0b100) >> 1
1038 * Finally, for a non-tiled surface, tile() simply combines together the X and
1039 * Y coordinates in the natural way:
1041 * tile(untiled, X, Y, S) = A
1042 * where A = Y * pitch + X'
1044 * Y' = Y + S * qpitch
1045 * detile(untiled, A) = (X, Y, S)
1046 * where X = X' / cpp
1052 * (In these formulas, pitch is the number of bytes occupied by a single row
1056 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1057 const struct brw_blorp_blit_prog_key
*key
)
1059 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1060 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1063 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1064 /* If the destination image is W tiled and multisampled, then the thread
1065 * must be dispatched once per sample, not once per pixel. This is
1066 * necessary because after conversion between W and Y tiling, there's no
1067 * guarantee that all samples corresponding to a single pixel will still
1070 assert(key
->persample_msaa_dispatch
);
1074 /* We are blending, which means we won't have an opportunity to
1075 * translate the tiling and sample count for the texture surface. So
1076 * the surface state for the texture must be configured with the correct
1077 * tiling and sample count.
1079 assert(!key
->src_tiled_w
);
1080 assert(key
->tex_samples
== key
->src_samples
);
1081 assert(key
->tex_layout
== key
->src_layout
);
1082 assert(key
->tex_samples
> 0);
1085 if (key
->persample_msaa_dispatch
) {
1086 /* It only makes sense to do persample dispatch if the render target is
1087 * configured as multisampled.
1089 assert(key
->rt_samples
> 0);
1092 /* Make sure layout is consistent with sample count */
1093 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1094 (key
->tex_samples
<= 1));
1095 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1096 (key
->rt_samples
<= 1));
1097 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1098 (key
->src_samples
<= 1));
1099 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1100 (key
->dst_samples
<= 1));
1103 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1105 struct brw_blorp_blit_vars v
;
1106 brw_blorp_blit_vars_init(&b
, &v
, key
);
1108 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1110 /* Render target and texture hardware don't support W tiling until Gen8. */
1111 const bool rt_tiled_w
= false;
1112 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1114 /* The address that data will be written to is determined by the
1115 * coordinates supplied to the WM thread and the tiling and sample count of
1116 * the render target, according to the formula:
1118 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1120 * If the actual tiling and sample count of the destination surface are not
1121 * the same as the configuration of the render target, then these
1122 * coordinates are wrong and we have to adjust them to compensate for the
1125 if (rt_tiled_w
!= key
->dst_tiled_w
||
1126 key
->rt_samples
!= key
->dst_samples
||
1127 key
->rt_layout
!= key
->dst_layout
) {
1128 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1130 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1131 if (rt_tiled_w
!= key
->dst_tiled_w
)
1132 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1133 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1134 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1138 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1140 * That is: X, Y and S now contain the true coordinates and sample index of
1141 * the data that the WM thread should output.
1143 * If we need to kill pixels that are outside the destination rectangle,
1144 * now is the time to do it.
1146 if (key
->use_kill
) {
1147 assert(!(key
->blend
&& key
->blit_scaled
));
1148 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1151 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f(&b
, dst_pos
), &v
);
1152 if (dst_pos
->num_components
== 3) {
1153 /* The sample coordinate is an integer that we want left alone but
1154 * blorp_blit_apply_transform() blindly applies the transform to all
1155 * three coordinates. Grab the original sample index.
1157 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1158 nir_channel(&b
, src_pos
, 1),
1159 nir_channel(&b
, dst_pos
, 2));
1162 /* If the source image is not multisampled, then we want to fetch sample
1163 * number 0, because that's the only sample there is.
1165 if (key
->src_samples
== 1)
1166 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1168 /* X, Y, and S are now the coordinates of the pixel in the source image
1169 * that we want to texture from. Exception: if we are blending, then S is
1170 * irrelevant, because we are going to fetch all samples.
1172 if (key
->blend
&& !key
->blit_scaled
) {
1173 /* Resolves (effecively) use texelFetch, so we need integers and we
1174 * don't care about the sample index if we got one.
1176 src_pos
= nir_f2i(&b
, nir_channels(&b
, src_pos
, 0x3));
1178 if (devinfo
->gen
== 6) {
1179 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1180 * blending we need with a single linear-interpolated texture lookup
1181 * at the center of the sample. The texture coordinates to be odd
1182 * integers so that they correspond to the center of a 2x2 block
1183 * representing the four samples that maxe up a pixel. So we need
1184 * to multiply our X and Y coordinates each by 2 and then add 1.
1186 src_pos
= nir_ishl(&b
, src_pos
, nir_imm_int(&b
, 1));
1187 src_pos
= nir_iadd(&b
, src_pos
, nir_imm_int(&b
, 1));
1188 src_pos
= nir_i2f(&b
, src_pos
);
1189 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1191 /* Gen7+ hardware doesn't automaticaly blend. */
1192 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1194 key
->texture_data_type
);
1196 } else if (key
->blend
&& key
->blit_scaled
) {
1197 assert(!key
->use_kill
);
1198 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1200 if (key
->bilinear_filter
) {
1201 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1203 /* We're going to use texelFetch, so we need integers */
1204 if (src_pos
->num_components
== 2) {
1205 src_pos
= nir_f2i(&b
, src_pos
);
1207 assert(src_pos
->num_components
== 3);
1208 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i(&b
, src_pos
), 0),
1209 nir_channel(&b
, nir_f2i(&b
, src_pos
), 1),
1210 nir_channel(&b
, src_pos
, 2));
1213 /* We aren't blending, which means we just want to fetch a single
1214 * sample from the source surface. The address that we want to fetch
1215 * from is related to the X, Y and S values according to the formula:
1217 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1219 * If the actual tiling and sample count of the source surface are
1220 * not the same as the configuration of the texture, then we need to
1221 * adjust the coordinates to compensate for the difference.
1223 if (tex_tiled_w
!= key
->src_tiled_w
||
1224 key
->tex_samples
!= key
->src_samples
||
1225 key
->tex_layout
!= key
->src_layout
) {
1226 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1228 /* Now (X, Y, S) = detile(src_tiling, offset) */
1229 if (tex_tiled_w
!= key
->src_tiled_w
)
1230 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1231 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1232 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1236 if (key
->need_src_offset
)
1237 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1239 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1241 * In other words: X, Y, and S now contain values which, when passed to
1242 * the texturing unit, will cause data to be read from the correct
1243 * memory location. So we can fetch the texel now.
1245 if (key
->src_samples
== 1) {
1246 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1248 nir_ssa_def
*mcs
= NULL
;
1249 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1250 mcs
= blorp_nir_txf_ms_mcs(&b
, &v
, src_pos
);
1252 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1257 if (key
->dst_bpc
!= key
->src_bpc
)
1258 color
= bit_cast_color(&b
, color
, key
);
1261 /* The destination image is bound as a red texture three times as wide
1262 * as the actual image. Our shader is effectively running one color
1263 * component at a time. We need to pick off the appropriate component
1264 * from the source color and write that to destination red.
1266 assert(dst_pos
->num_components
== 2);
1268 nir_umod(&b
, nir_channel(&b
, dst_pos
, 0), nir_imm_int(&b
, 3));
1270 nir_ssa_def
*color_component
=
1271 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1272 nir_channel(&b
, color
, 0),
1273 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1274 nir_channel(&b
, color
, 1),
1275 nir_channel(&b
, color
, 2)));
1277 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1278 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1281 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1287 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1288 struct blorp_params
*params
,
1289 const struct brw_blorp_blit_prog_key
*prog_key
)
1291 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1292 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1295 void *mem_ctx
= ralloc_context(NULL
);
1297 const unsigned *program
;
1298 unsigned program_size
;
1299 struct brw_wm_prog_data prog_data
;
1301 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1302 struct brw_wm_prog_key wm_key
;
1303 brw_blorp_init_wm_prog_key(&wm_key
);
1304 wm_key
.tex
.compressed_multisample_layout_mask
=
1305 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1306 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1307 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1309 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1310 &prog_data
, &program_size
);
1312 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1313 program
, program_size
,
1314 &prog_data
.base
, sizeof(prog_data
),
1315 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1317 ralloc_free(mem_ctx
);
1321 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1322 GLfloat src0
, GLfloat src1
,
1323 GLfloat dst0
, GLfloat dst1
,
1326 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1328 /* When not mirroring a coordinate (say, X), we need:
1329 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1331 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1333 * blorp program uses "round toward zero" to convert the
1334 * transformed floating point coordinates to integer coordinates,
1335 * whereas the behaviour we actually want is "round to nearest",
1336 * so 0.5 provides the necessary correction.
1338 xform
->multiplier
= scale
;
1339 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1341 /* When mirroring X we need:
1342 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1344 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1346 xform
->multiplier
= -scale
;
1347 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1352 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1353 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1355 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1356 struct isl_extent2d px_size_sa
=
1357 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1358 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1359 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1360 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1361 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1363 *tile_x_px
= info
->tile_x_sa
;
1364 *tile_y_px
= info
->tile_y_sa
;
1369 surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1370 struct brw_blorp_surface_info
*info
)
1372 /* Just bail if we have nothing to do. */
1373 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1374 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1375 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1378 /* If this gets triggered then we've gotten here twice which. This
1379 * shouldn't happen thanks to the above early return.
1381 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1383 uint32_t layer
= 0, z
= 0;
1384 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1385 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1387 layer
= info
->view
.base_array_layer
;
1389 uint32_t x_offset_sa
, y_offset_sa
;
1390 isl_surf_get_image_offset_sa(&info
->surf
, info
->view
.base_level
,
1391 layer
, z
, &x_offset_sa
, &y_offset_sa
);
1393 uint32_t byte_offset
;
1394 isl_tiling_get_intratile_offset_sa(isl_dev
, info
->surf
.tiling
,
1395 info
->surf
.format
, info
->surf
.row_pitch
,
1396 x_offset_sa
, y_offset_sa
,
1398 &info
->tile_x_sa
, &info
->tile_y_sa
);
1399 info
->addr
.offset
+= byte_offset
;
1401 const uint32_t slice_width_px
=
1402 minify(info
->surf
.logical_level0_px
.width
, info
->view
.base_level
);
1403 const uint32_t slice_height_px
=
1404 minify(info
->surf
.logical_level0_px
.height
, info
->view
.base_level
);
1406 uint32_t tile_x_px
, tile_y_px
;
1407 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1409 struct isl_surf_init_info init_info
= {
1410 .dim
= ISL_SURF_DIM_2D
,
1411 .format
= info
->surf
.format
,
1412 .width
= slice_width_px
+ tile_x_px
,
1413 .height
= slice_height_px
+ tile_y_px
,
1417 .samples
= info
->surf
.samples
,
1418 .min_pitch
= info
->surf
.row_pitch
,
1419 .usage
= info
->surf
.usage
,
1420 .tiling_flags
= 1 << info
->surf
.tiling
,
1423 isl_surf_init_s(isl_dev
, &info
->surf
, &init_info
);
1424 assert(info
->surf
.row_pitch
== init_info
.min_pitch
);
1426 /* The view is also different now. */
1427 info
->view
.base_level
= 0;
1428 info
->view
.levels
= 1;
1429 info
->view
.base_array_layer
= 0;
1430 info
->view
.array_len
= 1;
1435 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1436 struct brw_blorp_surface_info
*info
)
1438 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1440 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1441 surf_convert_to_single_slice(isl_dev
, info
);
1443 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1444 info
->surf
.samples
= 1;
1445 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1449 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1450 struct brw_blorp_surface_info
*info
)
1452 assert(info
->surf
.tiling
== ISL_TILING_W
);
1454 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1455 surf_convert_to_single_slice(isl_dev
, info
);
1457 /* On gen7+, we don't have interleaved multisampling for color render
1458 * targets so we have to fake it.
1460 * TODO: Are we sure we don't also need to fake it on gen6?
1462 if (isl_dev
->info
->gen
> 6 &&
1463 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1464 surf_fake_interleaved_msaa(isl_dev
, info
);
1467 if (isl_dev
->info
->gen
== 6) {
1468 /* Gen6 stencil buffers have a very large alignment coming in from the
1469 * miptree. It's out-of-bounds for what the surface state can handle.
1470 * Since we have a single layer and level, it doesn't really matter as
1471 * long as we don't pass a bogus value into isl_surf_fill_state().
1473 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1476 /* Now that we've converted everything to a simple 2-D surface with only
1477 * one miplevel, we can go about retiling it.
1479 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1480 info
->surf
.tiling
= ISL_TILING_Y0
;
1481 info
->surf
.logical_level0_px
.width
=
1482 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1483 info
->surf
.logical_level0_px
.height
=
1484 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1485 info
->tile_x_sa
*= 2;
1486 info
->tile_y_sa
/= 2;
1490 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1492 /* The current code doesn't support offsets into the aux buffers. This
1493 * should be possible, but we need to make sure the offset is page
1494 * aligned for both the surface and the aux buffer surface. Generally
1495 * this mean using the page aligned offset for the aux buffer.
1497 * Currently the cases where we must split the blit are limited to cases
1498 * where we don't have a aux buffer.
1500 if (surf
->aux_addr
.buffer
!= NULL
)
1503 /* We can't support splitting the blit for gen <= 7, because the qpitch
1504 * size is calculated by the hardware based on the surface height for
1505 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1507 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1514 can_shrink_surfaces(const struct blorp_params
*params
)
1517 can_shrink_surface(¶ms
->src
) &&
1518 can_shrink_surface(¶ms
->dst
);
1522 get_max_surface_size(const struct gen_device_info
*devinfo
,
1523 const struct blorp_params
*params
)
1525 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1526 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1527 return max
>> 4; /* A smaller restriction when debug is enabled */
1533 double src0
, src1
, dst0
, dst1
;
1538 struct blt_axis x
, y
;
1542 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1543 struct brw_blorp_surface_info
*info
,
1544 uint32_t *x
, uint32_t *width
)
1546 surf_convert_to_single_slice(isl_dev
, info
);
1548 info
->surf
.logical_level0_px
.width
*= 3;
1549 info
->surf
.phys_level0_sa
.width
*= 3;
1553 enum isl_format red_format
;
1554 switch (info
->view
.format
) {
1555 case ISL_FORMAT_R8G8B8_UNORM
:
1556 red_format
= ISL_FORMAT_R8_UNORM
;
1558 case ISL_FORMAT_R8G8B8_UINT
:
1559 red_format
= ISL_FORMAT_R8_UINT
;
1561 case ISL_FORMAT_R16G16B16_UNORM
:
1562 red_format
= ISL_FORMAT_R16_UNORM
;
1564 case ISL_FORMAT_R16G16B16_UINT
:
1565 red_format
= ISL_FORMAT_R16_UINT
;
1567 case ISL_FORMAT_R32G32B32_UINT
:
1568 red_format
= ISL_FORMAT_R32_UINT
;
1571 unreachable("Invalid RGB copy destination format");
1573 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1574 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1575 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1576 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1578 info
->surf
.format
= info
->view
.format
= red_format
;
1582 fake_dest_rgb_with_red(const struct isl_device
*dev
,
1583 struct blorp_params
*params
,
1584 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1585 struct blt_coords
*coords
)
1587 /* Handle RGB destinations for blorp_copy */
1588 const struct isl_format_layout
*dst_fmtl
=
1589 isl_format_get_layout(params
->dst
.surf
.format
);
1591 if (dst_fmtl
->bpb
% 3 == 0) {
1592 uint32_t dst_x
= coords
->x
.dst0
;
1593 uint32_t dst_width
= coords
->x
.dst1
- dst_x
;
1594 surf_fake_rgb_with_red(dev
, ¶ms
->dst
,
1595 &dst_x
, &dst_width
);
1596 coords
->x
.dst0
= dst_x
;
1597 coords
->x
.dst1
= dst_x
+ dst_width
;
1598 wm_prog_key
->dst_rgb
= true;
1599 wm_prog_key
->need_dst_offset
= true;
1603 enum blit_shrink_status
{
1605 BLIT_WIDTH_SHRINK
= 1,
1606 BLIT_HEIGHT_SHRINK
= 2,
1609 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1610 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1611 * returned, then the blit was successful.
1613 static enum blit_shrink_status
1614 try_blorp_blit(struct blorp_batch
*batch
,
1615 struct blorp_params
*params
,
1616 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1617 struct blt_coords
*coords
)
1619 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1621 fake_dest_rgb_with_red(batch
->blorp
->isl_dev
, params
, wm_prog_key
, coords
);
1623 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1624 wm_prog_key
->texture_data_type
= nir_type_int
;
1625 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1626 wm_prog_key
->texture_data_type
= nir_type_uint
;
1628 wm_prog_key
->texture_data_type
= nir_type_float
;
1631 /* src_samples and dst_samples are the true sample counts */
1632 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1633 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1635 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1637 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1640 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1641 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1643 /* Round floating point values to nearest integer to avoid "off by one texel"
1644 * kind of errors when blitting.
1646 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1647 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1648 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1649 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1651 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1652 coords
->x
.src0
, coords
->x
.src1
,
1653 coords
->x
.dst0
, coords
->x
.dst1
,
1655 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1656 coords
->y
.src0
, coords
->y
.src1
,
1657 coords
->y
.dst0
, coords
->y
.dst1
,
1660 if (devinfo
->gen
> 6 &&
1661 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1662 assert(params
->dst
.surf
.samples
> 1);
1664 /* We must expand the rectangle we send through the rendering pipeline,
1665 * to account for the fact that we are mapping the destination region as
1666 * single-sampled when it is in fact multisampled. We must also align
1667 * it to a multiple of the multisampling pattern, because the
1668 * differences between multisampled and single-sampled surface formats
1669 * will mean that pixels are scrambled within the multisampling pattern.
1670 * TODO: what if this makes the coordinates too large?
1672 * Note: this only works if the destination surface uses the IMS layout.
1673 * If it's UMS, then we have no choice but to set up the rendering
1674 * pipeline as multisampled.
1676 struct isl_extent2d px_size_sa
=
1677 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1678 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1679 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1680 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1681 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1683 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1685 wm_prog_key
->use_kill
= true;
1686 wm_prog_key
->need_dst_offset
= true;
1689 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1690 /* We must modify the rectangle we send through the rendering pipeline
1691 * (and the size and x/y offset of the destination surface), to account
1692 * for the fact that we are mapping it as Y-tiled when it is in fact
1695 * Both Y tiling and W tiling can be understood as organizations of
1696 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1697 * is different, but the layout of the 32-byte sub-tiles within the 4k
1698 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1699 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1700 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1702 * Therefore, to account for the layout differences within the 32-byte
1703 * sub-tiles, we must expand the rectangle so the X coordinates of its
1704 * edges are multiples of 8 (the W sub-tile width), and its Y
1705 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1706 * Then we need to scale the X and Y coordinates of the rectangle to
1707 * account for the differences in aspect ratio between the Y and W
1708 * sub-tiles. We need to modify the layer width and height similarly.
1710 * A correction needs to be applied when MSAA is in use: since
1711 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1712 * we need to align the Y coordinates to multiples of 8, so that when
1713 * they are divided by two they are still multiples of 4.
1715 * Note: Since the x/y offset of the surface will be applied using the
1716 * SURFACE_STATE command packet, it will be invisible to the swizzling
1717 * code in the shader; therefore it needs to be in a multiple of the
1718 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1719 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1720 * buffer), and the miplevel alignment used for stencil buffers is 8
1721 * pixels horizontally and either 4 or 8 pixels vertically (see
1722 * intel_horizontal_texture_alignment_unit() and
1723 * intel_vertical_texture_alignment_unit()).
1725 * Note: Also, since the SURFACE_STATE command packet can only apply
1726 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1727 * vertically, it is important that the offsets will be multiples of
1728 * these sizes after they are converted into Y-tiled coordinates.
1729 * Fortunately they will be, since we know from above that the offsets
1730 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1731 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1733 * TODO: what if this makes the coordinates (or the texture size) too
1736 const unsigned x_align
= 8;
1737 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1738 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1739 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1740 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1741 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1743 /* Retile the surface to Y-tiled */
1744 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1746 wm_prog_key
->dst_tiled_w
= true;
1747 wm_prog_key
->use_kill
= true;
1748 wm_prog_key
->need_dst_offset
= true;
1750 if (params
->dst
.surf
.samples
> 1) {
1751 /* If the destination surface is a W-tiled multisampled stencil
1752 * buffer that we're mapping as Y tiled, then we need to arrange for
1753 * the WM program to run once per sample rather than once per pixel,
1754 * because the memory layout of related samples doesn't match between
1757 wm_prog_key
->persample_msaa_dispatch
= true;
1761 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1762 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1763 * Broadwell adds support for sampling from stencil.
1765 * See the comments above concerning x/y offset alignment for the
1766 * destination surface.
1768 * TODO: what if this makes the texture size too large?
1770 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1772 wm_prog_key
->src_tiled_w
= true;
1773 wm_prog_key
->need_src_offset
= true;
1776 /* tex_samples and rt_samples are the sample counts that are set up in
1779 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1780 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1782 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1783 * use to access the source and destination surfaces.
1785 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1786 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1788 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1789 /* We are blitting from a multisample buffer to a multisample buffer, so
1790 * we must preserve samples within a pixel. This means we have to
1791 * arrange for the WM program to run once per sample rather than once
1794 wm_prog_key
->persample_msaa_dispatch
= true;
1797 params
->num_samples
= params
->dst
.surf
.samples
;
1799 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
1800 assert(wm_prog_key
->need_src_offset
);
1801 surf_get_intratile_offset_px(¶ms
->src
,
1802 ¶ms
->wm_inputs
.src_offset
.x
,
1803 ¶ms
->wm_inputs
.src_offset
.y
);
1806 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
1807 assert(wm_prog_key
->need_dst_offset
);
1808 surf_get_intratile_offset_px(¶ms
->dst
,
1809 ¶ms
->wm_inputs
.dst_offset
.x
,
1810 ¶ms
->wm_inputs
.dst_offset
.y
);
1811 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
1812 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
1813 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
1814 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
1817 /* For some texture types, we need to pass the layer through the sampler. */
1818 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
1820 brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
);
1822 unsigned result
= 0;
1823 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
1824 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
1825 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
1826 result
|= BLIT_WIDTH_SHRINK
;
1827 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
1828 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
1829 result
|= BLIT_HEIGHT_SHRINK
;
1832 batch
->blorp
->exec(batch
, params
);
1838 /* Adjust split blit source coordinates for the current destination
1842 adjust_split_source_coords(const struct blt_axis
*orig
,
1843 struct blt_axis
*split_coords
,
1846 /* When scale is greater than 0, then we are growing from the start, so
1847 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
1848 * source range shrinks from the end. In that case src0 is adjusted by
1849 * delta1, and src1 is adjusted by delta0.
1851 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
1852 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
1853 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
1854 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
1857 static const struct isl_extent2d
1858 get_px_size_sa(const struct isl_surf
*surf
)
1860 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
1862 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
1865 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
1869 shrink_surface_params(const struct isl_device
*dev
,
1870 struct brw_blorp_surface_info
*info
,
1871 double *x0
, double *x1
, double *y0
, double *y1
)
1873 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
1874 struct isl_extent2d px_size_sa
;
1877 surf_convert_to_single_slice(dev
, info
);
1879 px_size_sa
= get_px_size_sa(&info
->surf
);
1881 /* Because this gets called after we lower compressed images, the tile
1882 * offsets may be non-zero and we need to incorporate them in our
1885 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
1886 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
1887 isl_tiling_get_intratile_offset_sa(dev
, info
->surf
.tiling
,
1888 info
->surf
.format
, info
->surf
.row_pitch
,
1889 x_offset_sa
, y_offset_sa
,
1891 &info
->tile_x_sa
, &info
->tile_y_sa
);
1893 info
->addr
.offset
+= byte_offset
;
1895 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
1898 info
->tile_x_sa
= 0;
1900 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
1903 info
->tile_y_sa
= 0;
1905 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
1906 info
->surf
.logical_level0_px
.width
= size
;
1907 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
1909 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
1910 info
->surf
.logical_level0_px
.height
= size
;
1911 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
1915 shrink_surfaces(const struct isl_device
*dev
,
1916 struct blorp_params
*params
,
1917 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1918 struct blt_coords
*coords
)
1920 /* Shrink source surface */
1921 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
1922 &coords
->y
.src0
, &coords
->y
.src1
);
1923 wm_prog_key
->need_src_offset
= false;
1925 /* Shrink destination surface */
1926 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
1927 &coords
->y
.dst0
, &coords
->y
.dst1
);
1928 wm_prog_key
->need_dst_offset
= false;
1932 do_blorp_blit(struct blorp_batch
*batch
,
1933 const struct blorp_params
*orig_params
,
1934 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1935 const struct blt_coords
*orig
)
1937 struct blorp_params params
;
1938 struct blt_coords blit_coords
;
1939 struct blt_coords split_coords
= *orig
;
1940 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
1941 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
1942 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
1943 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
1949 bool x_done
, y_done
;
1950 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
1952 params
= *orig_params
;
1953 blit_coords
= split_coords
;
1955 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
1957 enum blit_shrink_status result
=
1958 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
1960 if (result
& BLIT_WIDTH_SHRINK
) {
1963 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
1964 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
1966 if (result
& BLIT_HEIGHT_SHRINK
) {
1969 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
1970 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
1974 assert(can_shrink_surfaces(orig_params
));
1979 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
1980 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
1983 } else if (y_done
) {
1984 split_coords
.x
.dst0
+= w
;
1985 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
1986 split_coords
.y
.dst0
= orig
->y
.dst0
;
1987 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
1988 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
1990 split_coords
.y
.dst0
+= h
;
1991 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
1992 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
1998 blorp_blit(struct blorp_batch
*batch
,
1999 const struct blorp_surf
*src_surf
,
2000 unsigned src_level
, unsigned src_layer
,
2001 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2002 const struct blorp_surf
*dst_surf
,
2003 unsigned dst_level
, unsigned dst_layer
,
2004 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2005 float src_x0
, float src_y0
,
2006 float src_x1
, float src_y1
,
2007 float dst_x0
, float dst_y0
,
2008 float dst_x1
, float dst_y1
,
2009 GLenum filter
, bool mirror_x
, bool mirror_y
)
2011 struct blorp_params params
;
2012 blorp_params_init(¶ms
);
2014 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2015 src_layer
, src_format
, false);
2016 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2017 dst_layer
, dst_format
, true);
2019 params
.src
.view
.swizzle
= src_swizzle
;
2020 params
.dst
.view
.swizzle
= dst_swizzle
;
2022 struct brw_blorp_blit_prog_key wm_prog_key
= {
2023 .shader_type
= BLORP_SHADER_TYPE_BLIT
2026 /* Scaled blitting or not. */
2027 wm_prog_key
.blit_scaled
=
2028 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2029 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2031 /* Scaling factors used for bilinear filtering in multisample scaled
2034 if (params
.src
.surf
.samples
== 16)
2035 wm_prog_key
.x_scale
= 4.0f
;
2037 wm_prog_key
.x_scale
= 2.0f
;
2038 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2040 if (filter
== GL_LINEAR
&&
2041 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1)
2042 wm_prog_key
.bilinear_filter
= true;
2044 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
2045 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
2046 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
2047 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
2048 /* We are downsampling a non-integer color buffer, so blend.
2050 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
2052 * "If the source formats are integer types or stencil values, a
2053 * single sample's value is selected for each pixel."
2055 * This implies we should not blend in that case.
2057 wm_prog_key
.blend
= true;
2060 params
.wm_inputs
.rect_grid
.x1
=
2061 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2062 wm_prog_key
.x_scale
- 1.0f
;
2063 params
.wm_inputs
.rect_grid
.y1
=
2064 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2065 wm_prog_key
.y_scale
- 1.0f
;
2067 struct blt_coords coords
= {
2084 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2087 static enum isl_format
2088 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2090 /* The choice of UNORM and UINT formats is very intentional here. Most
2091 * of the time, we want to use a UINT format to avoid any rounding error
2092 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2093 * (It's the only format allowed in conjunction with W-tiling.) Also we
2094 * intentionally use the 4-channel formats whenever we can. This is so
2095 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2096 * even though one of them is 3/4 the size of the other. The choice of
2097 * UNORM vs. UINT is also very intentional because we don't have 8 or
2098 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2099 * Fortunately, the only time we should ever use two different formats in
2100 * the table below is for RGB -> RGBA blits and so we will never have any
2101 * UNORM/UINT mismatch.
2103 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2105 case 8: return ISL_FORMAT_R8_UINT
;
2106 case 16: return ISL_FORMAT_R8G8_UINT
;
2107 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2108 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2109 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2110 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2111 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2112 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2114 unreachable("Unknown format bpb");
2118 case 8: return ISL_FORMAT_R8_UINT
;
2119 case 16: return ISL_FORMAT_R8G8_UINT
;
2120 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2121 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2122 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2123 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2124 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2125 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2127 unreachable("Unknown format bpb");
2132 /** Returns a UINT format that is CCS-compatible with the given format
2134 * The PRM's say absolutely nothing about how render compression works. The
2135 * only thing they provide is a list of formats on which it is and is not
2136 * supported. Empirical testing indicates that the compression is only based
2137 * on the bit-layout of the format and the channel encoding doesn't matter.
2138 * So, while texture views don't work in general, you can create a view as
2139 * long as the bit-layout of the formats are the same.
2141 * Fortunately, for every render compression capable format, the UINT format
2142 * with the same bit layout also supports render compression. This means that
2143 * we only need to handle UINT formats for copy operations. In order to do
2144 * copies between formats with different bit layouts, we attach both with a
2145 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2146 * operation between the two bit layouts.
2148 static enum isl_format
2149 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2151 switch (fmtl
->format
) {
2152 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2153 case ISL_FORMAT_R32G32B32A32_SINT
:
2154 case ISL_FORMAT_R32G32B32A32_UINT
:
2155 case ISL_FORMAT_R32G32B32A32_UNORM
:
2156 case ISL_FORMAT_R32G32B32A32_SNORM
:
2157 return ISL_FORMAT_R32G32B32A32_UINT
;
2159 case ISL_FORMAT_R16G16B16A16_UNORM
:
2160 case ISL_FORMAT_R16G16B16A16_SNORM
:
2161 case ISL_FORMAT_R16G16B16A16_SINT
:
2162 case ISL_FORMAT_R16G16B16A16_UINT
:
2163 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2164 case ISL_FORMAT_R16G16B16X16_UNORM
:
2165 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2166 return ISL_FORMAT_R16G16B16A16_UINT
;
2168 case ISL_FORMAT_R32G32_FLOAT
:
2169 case ISL_FORMAT_R32G32_SINT
:
2170 case ISL_FORMAT_R32G32_UINT
:
2171 case ISL_FORMAT_R32G32_UNORM
:
2172 case ISL_FORMAT_R32G32_SNORM
:
2173 return ISL_FORMAT_R32G32_UINT
;
2175 case ISL_FORMAT_B8G8R8A8_UNORM
:
2176 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2177 case ISL_FORMAT_R8G8B8A8_UNORM
:
2178 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2179 case ISL_FORMAT_R8G8B8A8_SNORM
:
2180 case ISL_FORMAT_R8G8B8A8_SINT
:
2181 case ISL_FORMAT_R8G8B8A8_UINT
:
2182 case ISL_FORMAT_B8G8R8X8_UNORM
:
2183 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2184 case ISL_FORMAT_R8G8B8X8_UNORM
:
2185 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2186 return ISL_FORMAT_R8G8B8A8_UINT
;
2188 case ISL_FORMAT_R16G16_UNORM
:
2189 case ISL_FORMAT_R16G16_SNORM
:
2190 case ISL_FORMAT_R16G16_SINT
:
2191 case ISL_FORMAT_R16G16_UINT
:
2192 case ISL_FORMAT_R16G16_FLOAT
:
2193 return ISL_FORMAT_R16G16_UINT
;
2195 case ISL_FORMAT_R32_SINT
:
2196 case ISL_FORMAT_R32_UINT
:
2197 case ISL_FORMAT_R32_FLOAT
:
2198 case ISL_FORMAT_R32_UNORM
:
2199 case ISL_FORMAT_R32_SNORM
:
2200 return ISL_FORMAT_R32_UINT
;
2203 unreachable("Not a compressible format");
2208 surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2209 struct brw_blorp_surface_info
*info
,
2210 uint32_t *x
, uint32_t *y
,
2211 uint32_t *width
, uint32_t *height
)
2213 const struct isl_format_layout
*fmtl
=
2214 isl_format_get_layout(info
->surf
.format
);
2216 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2218 /* This is a compressed surface. We need to convert it to a single
2219 * slice (because compressed layouts don't perfectly match uncompressed
2220 * ones with the same bpb) and divide x, y, width, and height by the
2223 surf_convert_to_single_slice(isl_dev
, info
);
2225 if (width
|| height
) {
2227 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2228 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2229 assert(*width
% fmtl
->bw
== 0 ||
2230 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2231 assert(*height
% fmtl
->bh
== 0 ||
2232 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2234 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2235 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2238 assert(*x
% fmtl
->bw
== 0);
2239 assert(*y
% fmtl
->bh
== 0);
2243 info
->surf
.logical_level0_px
.width
=
2244 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
2245 info
->surf
.logical_level0_px
.height
=
2246 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
2248 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
2249 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
2250 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2251 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2253 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2254 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2255 info
->tile_x_sa
/= fmtl
->bw
;
2256 info
->tile_y_sa
/= fmtl
->bh
;
2258 /* It's now an uncompressed surface so we need an uncompressed format */
2259 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2263 blorp_copy(struct blorp_batch
*batch
,
2264 const struct blorp_surf
*src_surf
,
2265 unsigned src_level
, unsigned src_layer
,
2266 const struct blorp_surf
*dst_surf
,
2267 unsigned dst_level
, unsigned dst_layer
,
2268 uint32_t src_x
, uint32_t src_y
,
2269 uint32_t dst_x
, uint32_t dst_y
,
2270 uint32_t src_width
, uint32_t src_height
)
2272 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2273 struct blorp_params params
;
2275 if (src_width
== 0 || src_height
== 0)
2278 blorp_params_init(¶ms
);
2279 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2280 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2281 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2282 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2284 struct brw_blorp_blit_prog_key wm_prog_key
= {
2285 .shader_type
= BLORP_SHADER_TYPE_BLIT
2288 const struct isl_format_layout
*src_fmtl
=
2289 isl_format_get_layout(params
.src
.surf
.format
);
2290 const struct isl_format_layout
*dst_fmtl
=
2291 isl_format_get_layout(params
.dst
.surf
.format
);
2293 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2294 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2295 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2296 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2297 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2298 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2300 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2301 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2302 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2303 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2304 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2305 params
.src
.view
.format
= params
.dst
.view
.format
;
2307 params
.src
.view
.format
=
2308 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2310 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2311 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2312 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2313 params
.dst
.view
.format
= params
.src
.view
.format
;
2315 params
.dst
.view
.format
=
2316 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2319 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2320 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2323 wm_prog_key
.src_bpc
=
2324 isl_format_get_layout(params
.src
.view
.format
)->channels
.r
.bits
;
2325 wm_prog_key
.dst_bpc
=
2326 isl_format_get_layout(params
.dst
.view
.format
)->channels
.r
.bits
;
2328 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2329 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2330 &src_x
, &src_y
, &src_width
, &src_height
);
2331 wm_prog_key
.need_src_offset
= true;
2334 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2335 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2336 &dst_x
, &dst_y
, NULL
, NULL
);
2337 wm_prog_key
.need_dst_offset
= true;
2340 /* Once both surfaces are stompped to uncompressed as needed, the
2341 * destination size is the same as the source size.
2343 uint32_t dst_width
= src_width
;
2344 uint32_t dst_height
= src_height
;
2346 struct blt_coords coords
= {
2349 .src1
= src_x
+ src_width
,
2351 .dst1
= dst_x
+ dst_width
,
2356 .src1
= src_y
+ src_height
,
2358 .dst1
= dst_y
+ dst_height
,
2363 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);