2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/nir/nir_builder.h"
26 #include "blorp_priv.h"
27 #include "brw_meta_util.h"
29 #define FILE_DEBUG_FLAG DEBUG_BLORP
32 * Enum to specify the order of arguments in a sampler message
34 enum sampler_message_arg
36 SAMPLER_MESSAGE_ARG_U_FLOAT
,
37 SAMPLER_MESSAGE_ARG_V_FLOAT
,
38 SAMPLER_MESSAGE_ARG_U_INT
,
39 SAMPLER_MESSAGE_ARG_V_INT
,
40 SAMPLER_MESSAGE_ARG_R_INT
,
41 SAMPLER_MESSAGE_ARG_SI_INT
,
42 SAMPLER_MESSAGE_ARG_MCS_INT
,
43 SAMPLER_MESSAGE_ARG_ZERO_INT
,
46 struct brw_blorp_blit_vars
{
47 /* Input values from brw_blorp_wm_inputs */
48 nir_variable
*v_discard_rect
;
49 nir_variable
*v_rect_grid
;
50 nir_variable
*v_coord_transform
;
51 nir_variable
*v_src_z
;
52 nir_variable
*v_src_offset
;
53 nir_variable
*v_dst_offset
;
56 nir_variable
*frag_coord
;
59 nir_variable
*color_out
;
63 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
64 const struct brw_blorp_blit_prog_key
*key
)
66 /* Blended and scaled blits never use pixel discard. */
67 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
69 #define LOAD_INPUT(name, type)\
70 v->v_##name = nir_variable_create(b->shader, nir_var_shader_in, \
72 v->v_##name->data.interpolation = INTERP_MODE_FLAT; \
73 v->v_##name->data.location = VARYING_SLOT_VAR0 + \
74 offsetof(struct brw_blorp_wm_inputs, name) / (4 * sizeof(float)); \
75 v->v_##name->data.location_frac = \
76 (offsetof(struct brw_blorp_wm_inputs, name) / sizeof(float)) % 4;
78 LOAD_INPUT(discard_rect
, glsl_vec4_type())
79 LOAD_INPUT(rect_grid
, glsl_vec4_type())
80 LOAD_INPUT(coord_transform
, glsl_vec4_type())
81 LOAD_INPUT(src_z
, glsl_uint_type())
82 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
83 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
87 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
88 glsl_vec4_type(), "gl_FragCoord");
89 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
90 v
->frag_coord
->data
.origin_upper_left
= true;
92 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
93 glsl_vec4_type(), "gl_FragColor");
94 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
98 blorp_blit_get_frag_coords(nir_builder
*b
,
99 const struct brw_blorp_blit_prog_key
*key
,
100 struct brw_blorp_blit_vars
*v
)
102 nir_ssa_def
*coord
= nir_f2i(b
, nir_load_var(b
, v
->frag_coord
));
104 /* Account for destination surface intratile offset
106 * Transformation parameters giving translation from destination to source
107 * coordinates don't take into account possible intra-tile destination
108 * offset. Therefore it has to be first subtracted from the incoming
109 * coordinates. Vertices are set up based on coordinates containing the
112 if (key
->need_dst_offset
)
113 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
115 if (key
->persample_msaa_dispatch
) {
116 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
117 nir_load_sample_id(b
));
119 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
124 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
128 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
129 struct brw_blorp_blit_vars
*v
)
131 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
133 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
134 nir_channel(b
, coord_transform
, 3));
135 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
136 nir_channel(b
, coord_transform
, 2));
138 return nir_ffma(b
, src_pos
, mul
, offset
);
142 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
143 struct brw_blorp_blit_vars
*v
)
145 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
146 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
147 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
148 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
149 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
150 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
152 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
153 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
154 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
155 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
157 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
159 nir_intrinsic_instr
*discard
=
160 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
161 discard
->src
[0] = nir_src_for_ssa(oob
);
162 nir_builder_instr_insert(b
, &discard
->instr
);
165 static nir_tex_instr
*
166 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
167 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
168 nir_alu_type dst_type
)
170 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
174 tex
->dest_type
= dst_type
;
175 tex
->is_array
= false;
176 tex
->is_shadow
= false;
178 /* Blorp only has one texture and it's bound at unit 0 */
181 tex
->texture_index
= 0;
182 tex
->sampler_index
= 0;
184 /* To properly handle 3-D and 2-D array textures, we pull the Z component
185 * from an input. TODO: This is a bit magic; we should probably make this
186 * more explicit in the future.
188 assert(pos
->num_components
>= 2);
189 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
190 nir_load_var(b
, v
->v_src_z
));
192 tex
->src
[0].src_type
= nir_tex_src_coord
;
193 tex
->src
[0].src
= nir_src_for_ssa(pos
);
194 tex
->coord_components
= 3;
196 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
202 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
203 nir_ssa_def
*pos
, nir_alu_type dst_type
)
206 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2, dst_type
);
208 assert(pos
->num_components
== 2);
209 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
210 tex
->src
[1].src_type
= nir_tex_src_lod
;
211 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
213 nir_builder_instr_insert(b
, &tex
->instr
);
215 return &tex
->dest
.ssa
;
219 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
220 nir_ssa_def
*pos
, nir_alu_type dst_type
)
223 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
225 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
226 tex
->src
[1].src_type
= nir_tex_src_lod
;
227 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
229 nir_builder_instr_insert(b
, &tex
->instr
);
231 return &tex
->dest
.ssa
;
235 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
236 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
239 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
240 mcs
!= NULL
? 3 : 2, dst_type
);
242 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
244 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
245 if (pos
->num_components
== 2) {
246 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
248 assert(pos
->num_components
== 3);
249 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
253 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
254 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
257 nir_builder_instr_insert(b
, &tex
->instr
);
259 return &tex
->dest
.ssa
;
263 blorp_nir_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
, nir_ssa_def
*pos
)
266 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
267 pos
, 1, nir_type_int
);
269 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
271 nir_builder_instr_insert(b
, &tex
->instr
);
273 return &tex
->dest
.ssa
;
277 nir_mask_shift_or(struct nir_builder
*b
, nir_ssa_def
*dst
, nir_ssa_def
*src
,
278 uint32_t src_mask
, int src_left_shift
)
280 nir_ssa_def
*masked
= nir_iand(b
, src
, nir_imm_int(b
, src_mask
));
282 nir_ssa_def
*shifted
;
283 if (src_left_shift
> 0) {
284 shifted
= nir_ishl(b
, masked
, nir_imm_int(b
, src_left_shift
));
285 } else if (src_left_shift
< 0) {
286 shifted
= nir_ushr(b
, masked
, nir_imm_int(b
, -src_left_shift
));
288 assert(src_left_shift
== 0);
292 return nir_ior(b
, dst
, shifted
);
296 * Emit code to compensate for the difference between Y and W tiling.
298 * This code modifies the X and Y coordinates according to the formula:
300 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
302 * (See brw_blorp_build_nir_shader).
304 static inline nir_ssa_def
*
305 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
307 assert(pos
->num_components
== 2);
308 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
309 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
311 /* Given X and Y coordinates that describe an address using Y tiling,
312 * translate to the X and Y coordinates that describe the same address
315 * If we break down the low order bits of X and Y, using a
316 * single letter to represent each low-order bit:
318 * X = A << 7 | 0bBCDEFGH
319 * Y = J << 5 | 0bKLMNP (1)
321 * Then we can apply the Y tiling formula to see the memory offset being
324 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
326 * If we apply the W detiling formula to this memory location, that the
327 * corresponding X' and Y' coordinates are:
329 * X' = A << 6 | 0bBCDPFH (3)
330 * Y' = J << 6 | 0bKLMNEG
332 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
333 * we need to make the following computation:
335 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
336 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
338 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
339 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
340 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
341 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
343 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
344 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
345 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
346 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
348 return nir_vec2(b
, x_W
, y_W
);
352 * Emit code to compensate for the difference between Y and W tiling.
354 * This code modifies the X and Y coordinates according to the formula:
356 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
358 * (See brw_blorp_build_nir_shader).
360 static inline nir_ssa_def
*
361 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
363 assert(pos
->num_components
== 2);
364 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
365 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
367 /* Applying the same logic as above, but in reverse, we obtain the
370 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
371 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
373 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
374 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
375 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
376 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
377 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
379 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
380 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
381 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
383 return nir_vec2(b
, x_Y
, y_Y
);
387 * Emit code to compensate for the difference between MSAA and non-MSAA
390 * This code modifies the X and Y coordinates according to the formula:
392 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
394 * (See brw_blorp_blit_program).
396 static inline nir_ssa_def
*
397 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
398 unsigned num_samples
, enum isl_msaa_layout layout
)
400 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
403 case ISL_MSAA_LAYOUT_NONE
:
404 assert(pos
->num_components
== 2);
406 case ISL_MSAA_LAYOUT_ARRAY
:
407 /* No translation needed */
409 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
410 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
411 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
412 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
413 nir_channel(b
, pos
, 2);
415 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
416 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
417 switch (num_samples
) {
420 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
421 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
424 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
425 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
426 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
428 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
429 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
430 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
431 if (num_samples
== 2) {
434 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
435 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
436 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
441 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
442 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
444 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
446 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
447 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
448 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
449 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
450 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
451 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
452 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
456 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
457 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
459 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
462 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
463 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
464 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
465 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
466 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
467 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
468 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
469 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
473 unreachable("Invalid number of samples for IMS layout");
476 return nir_vec2(b
, x_out
, y_out
);
480 unreachable("Invalid MSAA layout");
485 * Emit code to compensate for the difference between MSAA and non-MSAA
488 * This code modifies the X and Y coordinates according to the formula:
490 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
492 * (See brw_blorp_blit_program).
494 static inline nir_ssa_def
*
495 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
496 unsigned num_samples
, enum isl_msaa_layout layout
)
498 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
501 case ISL_MSAA_LAYOUT_NONE
:
502 /* No translation necessary, and S should already be zero. */
503 assert(pos
->num_components
== 2);
505 case ISL_MSAA_LAYOUT_ARRAY
:
506 /* No translation necessary. */
508 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
509 assert(pos
->num_components
== 2);
511 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
512 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
514 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
515 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
516 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
517 switch (num_samples
) {
520 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
521 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
522 * S = (X & 0b10) >> 1
524 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
525 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
526 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
527 * S = (Y & 0b10) | (X & 0b10) >> 1
529 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
530 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
531 if (num_samples
== 2) {
533 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
535 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
536 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
537 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
538 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
543 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
544 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
545 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
546 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
548 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
549 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
550 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
551 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
552 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
553 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
554 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
558 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
559 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
560 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
561 * S = (Y & 0b100) << 1 | (X & 0b100) |
562 * (Y & 0b10) | (X & 0b10) >> 1
564 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
565 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
566 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
567 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
568 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
569 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
570 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
571 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
575 unreachable("Invalid number of samples for IMS layout");
578 return nir_vec3(b
, x_out
, y_out
, s_out
);
582 unreachable("Invalid MSAA layout");
587 * Count the number of trailing 1 bits in the given value. For example:
589 * count_trailing_one_bits(0) == 0
590 * count_trailing_one_bits(7) == 3
591 * count_trailing_one_bits(11) == 2
593 static inline int count_trailing_one_bits(unsigned value
)
595 #ifdef HAVE___BUILTIN_CTZ
596 return __builtin_ctz(~value
);
598 return _mesa_bitcount(value
& ~(value
+ 1));
603 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
604 nir_ssa_def
*pos
, unsigned tex_samples
,
605 enum isl_aux_usage tex_aux_usage
,
606 nir_alu_type dst_type
)
608 /* If non-null, this is the outer-most if statement */
609 nir_if
*outer_if
= NULL
;
611 nir_variable
*color
=
612 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
614 nir_ssa_def
*mcs
= NULL
;
615 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
616 mcs
= blorp_nir_txf_ms_mcs(b
, v
, pos
);
618 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
620 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
622 * This ensures that when all samples have the same value, no numerical
623 * precision is lost, since each addition operation always adds two equal
624 * values, and summing two equal floating point values does not lose
627 * We perform this computation by treating the texture_data array as a
628 * stack and performing the following operations:
630 * - push sample 0 onto stack
631 * - push sample 1 onto stack
632 * - add top two stack entries
633 * - push sample 2 onto stack
634 * - push sample 3 onto stack
635 * - add top two stack entries
636 * - add top two stack entries
637 * - divide top stack entry by 4
639 * Note that after pushing sample i onto the stack, the number of add
640 * operations we do is equal to the number of trailing 1 bits in i. This
641 * works provided the total number of samples is a power of two, which it
642 * always is for i965.
644 * For integer formats, we replace the add operations with average
645 * operations and skip the final division.
647 nir_ssa_def
*texture_data
[5];
648 unsigned stack_depth
= 0;
649 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
650 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
652 /* Push sample i onto the stack */
653 assert(stack_depth
< ARRAY_SIZE(texture_data
));
655 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
656 nir_channel(b
, pos
, 1),
658 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
660 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
661 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
662 * suggests an optimization:
664 * "A simple optimization with probable large return in
665 * performance is to compare the MCS value to zero (indicating
666 * all samples are on sample slice 0), and sample only from
667 * sample slice 0 using ld2dss if MCS is zero."
669 * Note that in the case where the MCS value is zero, sampling from
670 * sample slice 0 using ld2dss and sampling from sample 0 using
671 * ld2dms are equivalent (since all samples are on sample slice 0).
672 * Since we have already sampled from sample 0, all we need to do is
673 * skip the remaining fetches and averaging if MCS is zero.
675 nir_ssa_def
*mcs_zero
=
676 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
677 if (tex_samples
== 16) {
678 mcs_zero
= nir_iand(b
, mcs_zero
,
679 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
682 nir_if
*if_stmt
= nir_if_create(b
->shader
);
683 if_stmt
->condition
= nir_src_for_ssa(mcs_zero
);
684 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
686 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
687 nir_store_var(b
, color
, texture_data
[0], 0xf);
689 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
693 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
694 assert(stack_depth
>= 2);
697 assert(dst_type
== nir_type_float
);
698 texture_data
[stack_depth
- 1] =
699 nir_fadd(b
, texture_data
[stack_depth
- 1],
700 texture_data
[stack_depth
]);
704 /* We should have just 1 sample on the stack now. */
705 assert(stack_depth
== 1);
707 texture_data
[0] = nir_fmul(b
, texture_data
[0],
708 nir_imm_float(b
, 1.0 / tex_samples
));
710 nir_store_var(b
, color
, texture_data
[0], 0xf);
713 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
715 return nir_load_var(b
, color
);
718 static inline nir_ssa_def
*
719 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
723 memset(&v
, 0, sizeof(v
));
727 return nir_build_imm(build
, 4, 32, v
);
731 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
732 unsigned tex_samples
,
733 const struct brw_blorp_blit_prog_key
*key
,
734 struct brw_blorp_blit_vars
*v
)
736 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
737 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
738 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
740 /* Translate coordinates to lay out the samples in a rectangular grid
741 * roughly corresponding to sample locations.
743 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
744 /* Adjust coordinates so that integers represent pixel centers rather
747 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
748 /* Clamp the X, Y texture coordinates to properly handle the sampling of
749 * texels on texture edges.
751 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
752 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
753 nir_channel(b
, rect_grid
, 1)));
755 /* Store the fractional parts to be used as bilinear interpolation
758 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
759 /* Round the float coordinates down to nearest integer */
760 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
762 nir_ssa_def
*tex_data
[4];
763 for (unsigned i
= 0; i
< 4; ++i
) {
764 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
765 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
766 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
768 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
769 nir_ssa_def
*sample_coords_int
= nir_f2i(b
, sample_coords
);
771 /* The MCS value we fetch has to match up with the pixel that we're
772 * sampling from. Since we sample from different pixels in each
773 * iteration of this "for" loop, the call to mcs_fetch() should be
774 * here inside the loop after computing the pixel coordinates.
776 nir_ssa_def
*mcs
= NULL
;
777 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
778 mcs
= blorp_nir_txf_ms_mcs(b
, v
, sample_coords_int
);
780 /* Compute sample index and map the sample index to a sample number.
781 * Sample index layout shows the numbering of slots in a rectangular
782 * grid of samples with in a pixel. Sample number layout shows the
783 * rectangular grid of samples roughly corresponding to the real sample
784 * locations with in a pixel.
785 * In case of 4x MSAA, layout of sample indices matches the layout of
793 * In case of 8x MSAA the two layouts don't match.
794 * sample index layout : --------- sample number layout : ---------
795 * | 0 | 1 | | 3 | 7 |
796 * --------- ---------
797 * | 2 | 3 | | 5 | 0 |
798 * --------- ---------
799 * | 4 | 5 | | 1 | 2 |
800 * --------- ---------
801 * | 6 | 7 | | 4 | 6 |
802 * --------- ---------
804 * Fortunately, this can be done fairly easily as:
805 * S' = (0x17306425 >> (S * 4)) & 0xf
807 * In the case of 16x MSAA the two layouts don't match.
808 * Sample index layout: Sample number layout:
809 * --------------------- ---------------------
810 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
811 * --------------------- ---------------------
812 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
813 * --------------------- ---------------------
814 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
815 * --------------------- ---------------------
816 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
817 * --------------------- ---------------------
819 * This is equivalent to
820 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
822 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
823 nir_ssa_def
*sample
=
824 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
825 key
->x_scale
* key
->y_scale
));
826 sample
= nir_f2i(b
, sample
);
828 if (tex_samples
== 8) {
829 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
830 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
831 nir_imm_int(b
, 0xf));
832 } else if (tex_samples
== 16) {
833 nir_ssa_def
*sample_low
=
834 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
835 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
836 nir_imm_int(b
, 0xf));
837 nir_ssa_def
*sample_high
=
838 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
839 nir_ishl(b
, nir_iadd(b
, sample
,
842 nir_imm_int(b
, 0xf));
844 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
845 sample_low
, sample_high
);
847 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
848 nir_channel(b
, sample_coords_int
, 1),
850 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
853 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
854 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
855 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
856 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
861 * Generator for WM programs used in BLORP blits.
863 * The bulk of the work done by the WM program is to wrap and unwrap the
864 * coordinate transformations used by the hardware to store surfaces in
865 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
866 * sample index for a multisampled surface) to a memory offset by the
867 * following formulas:
869 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
870 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
872 * For a single-sampled surface, or for a multisampled surface using
873 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
876 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
877 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
878 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
879 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
881 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
882 * embeds the sample number into bit 1 of the X and Y coordinates:
884 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
885 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
886 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
887 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
888 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
889 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
890 * S = (Y & 0b10) | (X & 0b10) >> 1
892 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
893 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
896 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
897 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
898 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
899 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
900 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
901 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
902 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
904 * For X tiling, tile() combines together the low-order bits of the X and Y
905 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
906 * bytes wide and 8 rows high:
908 * tile(x_tiled, X, Y, S) = A
909 * where A = tile_num << 12 | offset
910 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
911 * offset = (Y' & 0b111) << 9
912 * | (X & 0b111111111)
914 * Y' = Y + S * qpitch
915 * detile(x_tiled, A) = (X, Y, S)
919 * Y' = (tile_num / tile_pitch) << 3
920 * | (A & 0b111000000000) >> 9
921 * X' = (tile_num % tile_pitch) << 9
922 * | (A & 0b111111111)
924 * (In all tiling formulas, cpp is the number of bytes occupied by a single
925 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
926 * to fill the width of the surface, and qpitch is the spacing (in rows)
927 * between array slices).
929 * For Y tiling, tile() combines together the low-order bits of the X and Y
930 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
931 * bytes wide and 32 rows high:
933 * tile(y_tiled, X, Y, S) = A
934 * where A = tile_num << 12 | offset
935 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
936 * offset = (X' & 0b1110000) << 5
937 * | (Y' & 0b11111) << 4
940 * Y' = Y + S * qpitch
941 * detile(y_tiled, A) = (X, Y, S)
945 * Y' = (tile_num / tile_pitch) << 5
946 * | (A & 0b111110000) >> 4
947 * X' = (tile_num % tile_pitch) << 7
948 * | (A & 0b111000000000) >> 5
951 * For W tiling, tile() combines together the low-order bits of the X and Y
952 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
953 * bytes wide and 64 rows high (note that W tiling is only used for stencil
954 * buffers, which always have cpp = 1 and S=0):
956 * tile(w_tiled, X, Y, S) = A
957 * where A = tile_num << 12 | offset
958 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
959 * offset = (X' & 0b111000) << 6
960 * | (Y' & 0b111100) << 3
961 * | (X' & 0b100) << 2
967 * Y' = Y + S * qpitch
968 * detile(w_tiled, A) = (X, Y, S)
969 * where X = X' / cpp = X'
970 * Y = Y' % qpitch = Y'
972 * Y' = (tile_num / tile_pitch) << 6
973 * | (A & 0b111100000) >> 3
974 * | (A & 0b1000) >> 2
976 * X' = (tile_num % tile_pitch) << 6
977 * | (A & 0b111000000000) >> 6
978 * | (A & 0b10000) >> 2
982 * Finally, for a non-tiled surface, tile() simply combines together the X and
983 * Y coordinates in the natural way:
985 * tile(untiled, X, Y, S) = A
986 * where A = Y * pitch + X'
988 * Y' = Y + S * qpitch
989 * detile(untiled, A) = (X, Y, S)
996 * (In these formulas, pitch is the number of bytes occupied by a single row
1000 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1001 const struct brw_blorp_blit_prog_key
*key
)
1003 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1004 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1007 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1008 /* If the destination image is W tiled and multisampled, then the thread
1009 * must be dispatched once per sample, not once per pixel. This is
1010 * necessary because after conversion between W and Y tiling, there's no
1011 * guarantee that all samples corresponding to a single pixel will still
1014 assert(key
->persample_msaa_dispatch
);
1018 /* We are blending, which means we won't have an opportunity to
1019 * translate the tiling and sample count for the texture surface. So
1020 * the surface state for the texture must be configured with the correct
1021 * tiling and sample count.
1023 assert(!key
->src_tiled_w
);
1024 assert(key
->tex_samples
== key
->src_samples
);
1025 assert(key
->tex_layout
== key
->src_layout
);
1026 assert(key
->tex_samples
> 0);
1029 if (key
->persample_msaa_dispatch
) {
1030 /* It only makes sense to do persample dispatch if the render target is
1031 * configured as multisampled.
1033 assert(key
->rt_samples
> 0);
1036 /* Make sure layout is consistent with sample count */
1037 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1038 (key
->tex_samples
<= 1));
1039 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1040 (key
->rt_samples
<= 1));
1041 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1042 (key
->src_samples
<= 1));
1043 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1044 (key
->dst_samples
<= 1));
1047 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1049 struct brw_blorp_blit_vars v
;
1050 brw_blorp_blit_vars_init(&b
, &v
, key
);
1052 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1054 /* Render target and texture hardware don't support W tiling until Gen8. */
1055 const bool rt_tiled_w
= false;
1056 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1058 /* The address that data will be written to is determined by the
1059 * coordinates supplied to the WM thread and the tiling and sample count of
1060 * the render target, according to the formula:
1062 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1064 * If the actual tiling and sample count of the destination surface are not
1065 * the same as the configuration of the render target, then these
1066 * coordinates are wrong and we have to adjust them to compensate for the
1069 if (rt_tiled_w
!= key
->dst_tiled_w
||
1070 key
->rt_samples
!= key
->dst_samples
||
1071 key
->rt_layout
!= key
->dst_layout
) {
1072 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1074 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1075 if (rt_tiled_w
!= key
->dst_tiled_w
)
1076 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1077 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1078 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1082 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1084 * That is: X, Y and S now contain the true coordinates and sample index of
1085 * the data that the WM thread should output.
1087 * If we need to kill pixels that are outside the destination rectangle,
1088 * now is the time to do it.
1090 if (key
->use_kill
) {
1091 assert(!(key
->blend
&& key
->blit_scaled
));
1092 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1095 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f(&b
, dst_pos
), &v
);
1096 if (dst_pos
->num_components
== 3) {
1097 /* The sample coordinate is an integer that we want left alone but
1098 * blorp_blit_apply_transform() blindly applies the transform to all
1099 * three coordinates. Grab the original sample index.
1101 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1102 nir_channel(&b
, src_pos
, 1),
1103 nir_channel(&b
, dst_pos
, 2));
1106 /* If the source image is not multisampled, then we want to fetch sample
1107 * number 0, because that's the only sample there is.
1109 if (key
->src_samples
== 1)
1110 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1112 /* X, Y, and S are now the coordinates of the pixel in the source image
1113 * that we want to texture from. Exception: if we are blending, then S is
1114 * irrelevant, because we are going to fetch all samples.
1116 if (key
->blend
&& !key
->blit_scaled
) {
1117 /* Resolves (effecively) use texelFetch, so we need integers and we
1118 * don't care about the sample index if we got one.
1120 src_pos
= nir_f2i(&b
, nir_channels(&b
, src_pos
, 0x3));
1122 if (devinfo
->gen
== 6) {
1123 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1124 * blending we need with a single linear-interpolated texture lookup
1125 * at the center of the sample. The texture coordinates to be odd
1126 * integers so that they correspond to the center of a 2x2 block
1127 * representing the four samples that maxe up a pixel. So we need
1128 * to multiply our X and Y coordinates each by 2 and then add 1.
1130 src_pos
= nir_ishl(&b
, src_pos
, nir_imm_int(&b
, 1));
1131 src_pos
= nir_iadd(&b
, src_pos
, nir_imm_int(&b
, 1));
1132 src_pos
= nir_i2f(&b
, src_pos
);
1133 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1135 /* Gen7+ hardware doesn't automaticaly blend. */
1136 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1138 key
->texture_data_type
);
1140 } else if (key
->blend
&& key
->blit_scaled
) {
1141 assert(!key
->use_kill
);
1142 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1144 if (key
->bilinear_filter
) {
1145 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1147 /* We're going to use texelFetch, so we need integers */
1148 if (src_pos
->num_components
== 2) {
1149 src_pos
= nir_f2i(&b
, src_pos
);
1151 assert(src_pos
->num_components
== 3);
1152 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i(&b
, src_pos
), 0),
1153 nir_channel(&b
, nir_f2i(&b
, src_pos
), 1),
1154 nir_channel(&b
, src_pos
, 2));
1157 /* We aren't blending, which means we just want to fetch a single
1158 * sample from the source surface. The address that we want to fetch
1159 * from is related to the X, Y and S values according to the formula:
1161 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1163 * If the actual tiling and sample count of the source surface are
1164 * not the same as the configuration of the texture, then we need to
1165 * adjust the coordinates to compensate for the difference.
1167 if (tex_tiled_w
!= key
->src_tiled_w
||
1168 key
->tex_samples
!= key
->src_samples
||
1169 key
->tex_layout
!= key
->src_layout
) {
1170 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1172 /* Now (X, Y, S) = detile(src_tiling, offset) */
1173 if (tex_tiled_w
!= key
->src_tiled_w
)
1174 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1175 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1176 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1180 if (key
->need_src_offset
)
1181 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1183 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1185 * In other words: X, Y, and S now contain values which, when passed to
1186 * the texturing unit, will cause data to be read from the correct
1187 * memory location. So we can fetch the texel now.
1189 if (key
->src_samples
== 1) {
1190 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1192 nir_ssa_def
*mcs
= NULL
;
1193 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1194 mcs
= blorp_nir_txf_ms_mcs(&b
, &v
, src_pos
);
1196 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1202 /* The destination image is bound as a red texture three times as wide
1203 * as the actual image. Our shader is effectively running one color
1204 * component at a time. We need to pick off the appropriate component
1205 * from the source color and write that to destination red.
1207 assert(dst_pos
->num_components
== 2);
1209 nir_umod(&b
, nir_channel(&b
, dst_pos
, 0), nir_imm_int(&b
, 3));
1211 nir_ssa_def
*color_component
=
1212 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1213 nir_channel(&b
, color
, 0),
1214 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1215 nir_channel(&b
, color
, 1),
1216 nir_channel(&b
, color
, 2)));
1218 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1219 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1222 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1228 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1229 struct blorp_params
*params
,
1230 const struct brw_blorp_blit_prog_key
*prog_key
)
1232 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1233 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1236 void *mem_ctx
= ralloc_context(NULL
);
1238 const unsigned *program
;
1239 unsigned program_size
;
1240 struct brw_wm_prog_data prog_data
;
1242 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1243 struct brw_wm_prog_key wm_key
;
1244 brw_blorp_init_wm_prog_key(&wm_key
);
1245 wm_key
.tex
.compressed_multisample_layout_mask
=
1246 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1247 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1248 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1250 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1251 &prog_data
, &program_size
);
1253 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1254 program
, program_size
,
1255 &prog_data
.base
, sizeof(prog_data
),
1256 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1258 ralloc_free(mem_ctx
);
1262 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1263 GLfloat src0
, GLfloat src1
,
1264 GLfloat dst0
, GLfloat dst1
,
1267 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1269 /* When not mirroring a coordinate (say, X), we need:
1270 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1272 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1274 * blorp program uses "round toward zero" to convert the
1275 * transformed floating point coordinates to integer coordinates,
1276 * whereas the behaviour we actually want is "round to nearest",
1277 * so 0.5 provides the necessary correction.
1279 xform
->multiplier
= scale
;
1280 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1282 /* When mirroring X we need:
1283 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1285 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1287 xform
->multiplier
= -scale
;
1288 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1293 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1294 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1296 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1297 struct isl_extent2d px_size_sa
=
1298 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1299 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1300 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1301 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1302 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1304 *tile_x_px
= info
->tile_x_sa
;
1305 *tile_y_px
= info
->tile_y_sa
;
1310 surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1311 struct brw_blorp_surface_info
*info
)
1313 /* Just bail if we have nothing to do. */
1314 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1315 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1316 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1319 /* If this gets triggered then we've gotten here twice which. This
1320 * shouldn't happen thanks to the above early return.
1322 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1324 uint32_t layer
= 0, z
= 0;
1325 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1326 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1328 layer
= info
->view
.base_array_layer
;
1330 uint32_t x_offset_sa
, y_offset_sa
;
1331 isl_surf_get_image_offset_sa(&info
->surf
, info
->view
.base_level
,
1332 layer
, z
, &x_offset_sa
, &y_offset_sa
);
1334 uint32_t byte_offset
;
1335 isl_tiling_get_intratile_offset_sa(isl_dev
, info
->surf
.tiling
,
1336 info
->surf
.format
, info
->surf
.row_pitch
,
1337 x_offset_sa
, y_offset_sa
,
1339 &info
->tile_x_sa
, &info
->tile_y_sa
);
1340 info
->addr
.offset
+= byte_offset
;
1342 const uint32_t slice_width_px
=
1343 minify(info
->surf
.logical_level0_px
.width
, info
->view
.base_level
);
1344 const uint32_t slice_height_px
=
1345 minify(info
->surf
.logical_level0_px
.height
, info
->view
.base_level
);
1347 uint32_t tile_x_px
, tile_y_px
;
1348 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1350 struct isl_surf_init_info init_info
= {
1351 .dim
= ISL_SURF_DIM_2D
,
1352 .format
= info
->surf
.format
,
1353 .width
= slice_width_px
+ tile_x_px
,
1354 .height
= slice_height_px
+ tile_y_px
,
1358 .samples
= info
->surf
.samples
,
1359 .min_pitch
= info
->surf
.row_pitch
,
1360 .usage
= info
->surf
.usage
,
1361 .tiling_flags
= 1 << info
->surf
.tiling
,
1364 isl_surf_init_s(isl_dev
, &info
->surf
, &init_info
);
1365 assert(info
->surf
.row_pitch
== init_info
.min_pitch
);
1367 /* The view is also different now. */
1368 info
->view
.base_level
= 0;
1369 info
->view
.levels
= 1;
1370 info
->view
.base_array_layer
= 0;
1371 info
->view
.array_len
= 1;
1376 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1377 struct brw_blorp_surface_info
*info
)
1379 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1381 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1382 surf_convert_to_single_slice(isl_dev
, info
);
1384 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1385 info
->surf
.samples
= 1;
1386 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1390 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1391 struct brw_blorp_surface_info
*info
)
1393 assert(info
->surf
.tiling
== ISL_TILING_W
);
1395 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1396 surf_convert_to_single_slice(isl_dev
, info
);
1398 /* On gen7+, we don't have interleaved multisampling for color render
1399 * targets so we have to fake it.
1401 * TODO: Are we sure we don't also need to fake it on gen6?
1403 if (isl_dev
->info
->gen
> 6 &&
1404 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1405 surf_fake_interleaved_msaa(isl_dev
, info
);
1408 if (isl_dev
->info
->gen
== 6) {
1409 /* Gen6 stencil buffers have a very large alignment coming in from the
1410 * miptree. It's out-of-bounds for what the surface state can handle.
1411 * Since we have a single layer and level, it doesn't really matter as
1412 * long as we don't pass a bogus value into isl_surf_fill_state().
1414 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1417 /* Now that we've converted everything to a simple 2-D surface with only
1418 * one miplevel, we can go about retiling it.
1420 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1421 info
->surf
.tiling
= ISL_TILING_Y0
;
1422 info
->surf
.logical_level0_px
.width
=
1423 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1424 info
->surf
.logical_level0_px
.height
=
1425 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1426 info
->tile_x_sa
*= 2;
1427 info
->tile_y_sa
/= 2;
1431 do_blorp_blit(struct blorp_batch
*batch
,
1432 struct blorp_params
*params
,
1433 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1434 float src_x0
, float src_y0
,
1435 float src_x1
, float src_y1
,
1436 float dst_x0
, float dst_y0
,
1437 float dst_x1
, float dst_y1
,
1438 bool mirror_x
, bool mirror_y
)
1440 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1442 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1443 wm_prog_key
->texture_data_type
= nir_type_int
;
1444 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1445 wm_prog_key
->texture_data_type
= nir_type_uint
;
1447 wm_prog_key
->texture_data_type
= nir_type_float
;
1450 /* src_samples and dst_samples are the true sample counts */
1451 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1452 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1454 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1456 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1459 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1460 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1462 /* Round floating point values to nearest integer to avoid "off by one texel"
1463 * kind of errors when blitting.
1465 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= roundf(dst_x0
);
1466 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= roundf(dst_y0
);
1467 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= roundf(dst_x1
);
1468 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= roundf(dst_y1
);
1470 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1471 src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
1472 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1473 src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
1475 if (devinfo
->gen
> 6 &&
1476 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1477 assert(params
->dst
.surf
.samples
> 1);
1479 /* We must expand the rectangle we send through the rendering pipeline,
1480 * to account for the fact that we are mapping the destination region as
1481 * single-sampled when it is in fact multisampled. We must also align
1482 * it to a multiple of the multisampling pattern, because the
1483 * differences between multisampled and single-sampled surface formats
1484 * will mean that pixels are scrambled within the multisampling pattern.
1485 * TODO: what if this makes the coordinates too large?
1487 * Note: this only works if the destination surface uses the IMS layout.
1488 * If it's UMS, then we have no choice but to set up the rendering
1489 * pipeline as multisampled.
1491 struct isl_extent2d px_size_sa
=
1492 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1493 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1494 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1495 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1496 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1498 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1500 wm_prog_key
->use_kill
= true;
1501 wm_prog_key
->need_dst_offset
= true;
1504 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1505 /* We must modify the rectangle we send through the rendering pipeline
1506 * (and the size and x/y offset of the destination surface), to account
1507 * for the fact that we are mapping it as Y-tiled when it is in fact
1510 * Both Y tiling and W tiling can be understood as organizations of
1511 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1512 * is different, but the layout of the 32-byte sub-tiles within the 4k
1513 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1514 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1515 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1517 * Therefore, to account for the layout differences within the 32-byte
1518 * sub-tiles, we must expand the rectangle so the X coordinates of its
1519 * edges are multiples of 8 (the W sub-tile width), and its Y
1520 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1521 * Then we need to scale the X and Y coordinates of the rectangle to
1522 * account for the differences in aspect ratio between the Y and W
1523 * sub-tiles. We need to modify the layer width and height similarly.
1525 * A correction needs to be applied when MSAA is in use: since
1526 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1527 * we need to align the Y coordinates to multiples of 8, so that when
1528 * they are divided by two they are still multiples of 4.
1530 * Note: Since the x/y offset of the surface will be applied using the
1531 * SURFACE_STATE command packet, it will be invisible to the swizzling
1532 * code in the shader; therefore it needs to be in a multiple of the
1533 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1534 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1535 * buffer), and the miplevel alignment used for stencil buffers is 8
1536 * pixels horizontally and either 4 or 8 pixels vertically (see
1537 * intel_horizontal_texture_alignment_unit() and
1538 * intel_vertical_texture_alignment_unit()).
1540 * Note: Also, since the SURFACE_STATE command packet can only apply
1541 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1542 * vertically, it is important that the offsets will be multiples of
1543 * these sizes after they are converted into Y-tiled coordinates.
1544 * Fortunately they will be, since we know from above that the offsets
1545 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1546 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1548 * TODO: what if this makes the coordinates (or the texture size) too
1551 const unsigned x_align
= 8;
1552 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1553 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1554 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1555 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1556 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1558 /* Retile the surface to Y-tiled */
1559 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1561 wm_prog_key
->dst_tiled_w
= true;
1562 wm_prog_key
->use_kill
= true;
1563 wm_prog_key
->need_dst_offset
= true;
1565 if (params
->dst
.surf
.samples
> 1) {
1566 /* If the destination surface is a W-tiled multisampled stencil
1567 * buffer that we're mapping as Y tiled, then we need to arrange for
1568 * the WM program to run once per sample rather than once per pixel,
1569 * because the memory layout of related samples doesn't match between
1572 wm_prog_key
->persample_msaa_dispatch
= true;
1576 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1577 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1578 * Broadwell adds support for sampling from stencil.
1580 * See the comments above concerning x/y offset alignment for the
1581 * destination surface.
1583 * TODO: what if this makes the texture size too large?
1585 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1587 wm_prog_key
->src_tiled_w
= true;
1588 wm_prog_key
->need_src_offset
= true;
1591 /* tex_samples and rt_samples are the sample counts that are set up in
1594 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1595 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1597 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1598 * use to access the source and destination surfaces.
1600 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1601 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1603 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1604 /* We are blitting from a multisample buffer to a multisample buffer, so
1605 * we must preserve samples within a pixel. This means we have to
1606 * arrange for the WM program to run once per sample rather than once
1609 wm_prog_key
->persample_msaa_dispatch
= true;
1612 params
->num_samples
= params
->dst
.surf
.samples
;
1614 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
1615 assert(wm_prog_key
->need_src_offset
);
1616 surf_get_intratile_offset_px(¶ms
->src
,
1617 ¶ms
->wm_inputs
.src_offset
.x
,
1618 ¶ms
->wm_inputs
.src_offset
.y
);
1621 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
1622 assert(wm_prog_key
->need_dst_offset
);
1623 surf_get_intratile_offset_px(¶ms
->dst
,
1624 ¶ms
->wm_inputs
.dst_offset
.x
,
1625 ¶ms
->wm_inputs
.dst_offset
.y
);
1626 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
1627 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
1628 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
1629 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
1632 /* For some texture types, we need to pass the layer through the sampler. */
1633 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
1635 brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
);
1637 batch
->blorp
->exec(batch
, params
);
1641 blorp_blit(struct blorp_batch
*batch
,
1642 const struct blorp_surf
*src_surf
,
1643 unsigned src_level
, unsigned src_layer
,
1644 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
1645 const struct blorp_surf
*dst_surf
,
1646 unsigned dst_level
, unsigned dst_layer
,
1647 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
1648 float src_x0
, float src_y0
,
1649 float src_x1
, float src_y1
,
1650 float dst_x0
, float dst_y0
,
1651 float dst_x1
, float dst_y1
,
1652 GLenum filter
, bool mirror_x
, bool mirror_y
)
1654 struct blorp_params params
;
1655 blorp_params_init(¶ms
);
1657 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
1658 src_layer
, src_format
, false);
1659 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
1660 dst_layer
, dst_format
, true);
1662 params
.src
.view
.swizzle
= src_swizzle
;
1663 params
.dst
.view
.swizzle
= dst_swizzle
;
1665 struct brw_blorp_blit_prog_key wm_prog_key
;
1666 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1668 /* Scaled blitting or not. */
1669 wm_prog_key
.blit_scaled
=
1670 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
1671 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
1673 /* Scaling factors used for bilinear filtering in multisample scaled
1676 if (params
.src
.surf
.samples
== 16)
1677 wm_prog_key
.x_scale
= 4.0f
;
1679 wm_prog_key
.x_scale
= 2.0f
;
1680 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
1682 if (filter
== GL_LINEAR
&&
1683 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1)
1684 wm_prog_key
.bilinear_filter
= true;
1686 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
1687 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
1688 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
1689 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
1690 /* We are downsampling a non-integer color buffer, so blend.
1692 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
1694 * "If the source formats are integer types or stencil values, a
1695 * single sample's value is selected for each pixel."
1697 * This implies we should not blend in that case.
1699 wm_prog_key
.blend
= true;
1702 params
.wm_inputs
.rect_grid
.x1
=
1703 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
1704 wm_prog_key
.x_scale
- 1.0f
;
1705 params
.wm_inputs
.rect_grid
.y1
=
1706 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
1707 wm_prog_key
.y_scale
- 1.0f
;
1709 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
,
1710 src_x0
, src_y0
, src_x1
, src_y1
,
1711 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
1712 mirror_x
, mirror_y
);
1715 static enum isl_format
1716 get_copy_format_for_bpb(unsigned bpb
)
1718 /* The choice of UNORM and UINT formats is very intentional here. Most of
1719 * the time, we want to use a UINT format to avoid any rounding error in
1720 * the blit. For stencil blits, R8_UINT is required by the hardware.
1721 * (It's the only format allowed in conjunction with W-tiling.) Also we
1722 * intentionally use the 4-channel formats whenever we can. This is so
1723 * that, when we do a RGB <-> RGBX copy, the two formats will line up even
1724 * though one of them is 3/4 the size of the other. The choice of UNORM
1725 * vs. UINT is also very intentional because Haswell doesn't handle 8 or
1726 * 16-bit RGB UINT formats at all so we have to use UNORM there.
1727 * Fortunately, the only time we should ever use two different formats in
1728 * the table below is for RGB -> RGBA blits and so we will never have any
1729 * UNORM/UINT mismatch.
1732 case 8: return ISL_FORMAT_R8_UINT
;
1733 case 16: return ISL_FORMAT_R8G8_UINT
;
1734 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
1735 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
1736 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
1737 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
1738 case 96: return ISL_FORMAT_R32G32B32_UINT
;
1739 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
1741 unreachable("Unknown format bpb");
1746 surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
1747 struct brw_blorp_surface_info
*info
,
1748 uint32_t *x
, uint32_t *y
,
1749 uint32_t *width
, uint32_t *height
)
1751 const struct isl_format_layout
*fmtl
=
1752 isl_format_get_layout(info
->surf
.format
);
1754 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
1756 /* This is a compressed surface. We need to convert it to a single
1757 * slice (because compressed layouts don't perfectly match uncompressed
1758 * ones with the same bpb) and divide x, y, width, and height by the
1761 surf_convert_to_single_slice(isl_dev
, info
);
1763 if (width
|| height
) {
1765 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
1766 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
1767 assert(*width
% fmtl
->bw
== 0 ||
1768 right_edge_px
== info
->surf
.logical_level0_px
.width
);
1769 assert(*height
% fmtl
->bh
== 0 ||
1770 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
1772 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
1773 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
1776 assert(*x
% fmtl
->bw
== 0);
1777 assert(*y
% fmtl
->bh
== 0);
1781 info
->surf
.logical_level0_px
.width
=
1782 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
1783 info
->surf
.logical_level0_px
.height
=
1784 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
1786 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
1787 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
1788 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
1789 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
1791 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
1792 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
1793 info
->tile_x_sa
/= fmtl
->bw
;
1794 info
->tile_y_sa
/= fmtl
->bh
;
1796 /* It's now an uncompressed surface so we need an uncompressed format */
1797 info
->surf
.format
= get_copy_format_for_bpb(fmtl
->bpb
);
1801 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1802 struct brw_blorp_surface_info
*info
,
1803 uint32_t *x
, uint32_t *width
)
1805 surf_convert_to_single_slice(isl_dev
, info
);
1807 info
->surf
.logical_level0_px
.width
*= 3;
1808 info
->surf
.phys_level0_sa
.width
*= 3;
1812 enum isl_format red_format
;
1813 switch (info
->view
.format
) {
1814 case ISL_FORMAT_R8G8B8_UNORM
:
1815 red_format
= ISL_FORMAT_R8_UNORM
;
1817 case ISL_FORMAT_R16G16B16_UNORM
:
1818 red_format
= ISL_FORMAT_R16_UNORM
;
1820 case ISL_FORMAT_R32G32B32_UINT
:
1821 red_format
= ISL_FORMAT_R32_UINT
;
1824 unreachable("Invalid RGB copy destination format");
1826 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1827 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1828 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1829 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1831 info
->surf
.format
= info
->view
.format
= red_format
;
1835 blorp_copy(struct blorp_batch
*batch
,
1836 const struct blorp_surf
*src_surf
,
1837 unsigned src_level
, unsigned src_layer
,
1838 const struct blorp_surf
*dst_surf
,
1839 unsigned dst_level
, unsigned dst_layer
,
1840 uint32_t src_x
, uint32_t src_y
,
1841 uint32_t dst_x
, uint32_t dst_y
,
1842 uint32_t src_width
, uint32_t src_height
)
1844 struct blorp_params params
;
1846 if (src_width
== 0 || src_height
== 0)
1849 blorp_params_init(¶ms
);
1850 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
1851 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
1852 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
1853 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
1855 struct brw_blorp_blit_prog_key wm_prog_key
;
1856 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1858 const struct isl_format_layout
*src_fmtl
=
1859 isl_format_get_layout(params
.src
.surf
.format
);
1860 const struct isl_format_layout
*dst_fmtl
=
1861 isl_format_get_layout(params
.dst
.surf
.format
);
1863 params
.src
.view
.format
= get_copy_format_for_bpb(src_fmtl
->bpb
);
1864 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
1865 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
1866 &src_x
, &src_y
, &src_width
, &src_height
);
1867 wm_prog_key
.need_src_offset
= true;
1870 params
.dst
.view
.format
= get_copy_format_for_bpb(dst_fmtl
->bpb
);
1871 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
1872 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
1873 &dst_x
, &dst_y
, NULL
, NULL
);
1874 wm_prog_key
.need_dst_offset
= true;
1877 /* Once both surfaces are stompped to uncompressed as needed, the
1878 * destination size is the same as the source size.
1880 uint32_t dst_width
= src_width
;
1881 uint32_t dst_height
= src_height
;
1883 if (dst_fmtl
->bpb
% 3 == 0) {
1884 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
.dst
,
1885 &dst_x
, &dst_width
);
1886 wm_prog_key
.dst_rgb
= true;
1887 wm_prog_key
.need_dst_offset
= true;
1890 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
,
1891 src_x
, src_y
, src_x
+ src_width
, src_y
+ src_height
,
1892 dst_x
, dst_y
, dst_x
+ dst_width
, dst_y
+ dst_height
,