2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "program/prog_instruction.h"
25 #include "compiler/nir/nir_builder.h"
27 #include "blorp_priv.h"
28 #include "brw_meta_util.h"
30 #define FILE_DEBUG_FLAG DEBUG_BLORP
33 * Enum to specify the order of arguments in a sampler message
35 enum sampler_message_arg
37 SAMPLER_MESSAGE_ARG_U_FLOAT
,
38 SAMPLER_MESSAGE_ARG_V_FLOAT
,
39 SAMPLER_MESSAGE_ARG_U_INT
,
40 SAMPLER_MESSAGE_ARG_V_INT
,
41 SAMPLER_MESSAGE_ARG_R_INT
,
42 SAMPLER_MESSAGE_ARG_SI_INT
,
43 SAMPLER_MESSAGE_ARG_MCS_INT
,
44 SAMPLER_MESSAGE_ARG_ZERO_INT
,
47 struct brw_blorp_blit_vars
{
48 /* Input values from brw_blorp_wm_inputs */
49 nir_variable
*v_discard_rect
;
50 nir_variable
*v_rect_grid
;
51 nir_variable
*v_coord_transform
;
52 nir_variable
*v_src_z
;
55 nir_variable
*frag_coord
;
58 nir_variable
*color_out
;
62 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
63 const struct brw_blorp_blit_prog_key
*key
)
65 /* Blended and scaled blits never use pixel discard. */
66 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
68 #define LOAD_INPUT(name, type)\
69 v->v_##name = nir_variable_create(b->shader, nir_var_shader_in, \
71 v->v_##name->data.interpolation = INTERP_MODE_FLAT; \
72 v->v_##name->data.location = VARYING_SLOT_VAR0 + \
73 offsetof(struct brw_blorp_wm_inputs, name) / (4 * sizeof(float));
75 LOAD_INPUT(discard_rect
, glsl_vec4_type())
76 LOAD_INPUT(rect_grid
, glsl_vec4_type())
77 LOAD_INPUT(coord_transform
, glsl_vec4_type())
78 LOAD_INPUT(src_z
, glsl_uint_type())
82 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
83 glsl_vec4_type(), "gl_FragCoord");
84 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
85 v
->frag_coord
->data
.origin_upper_left
= true;
87 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
88 glsl_vec4_type(), "gl_FragColor");
89 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
93 blorp_blit_get_frag_coords(nir_builder
*b
,
94 const struct brw_blorp_blit_prog_key
*key
,
95 struct brw_blorp_blit_vars
*v
)
97 nir_ssa_def
*coord
= nir_f2i(b
, nir_load_var(b
, v
->frag_coord
));
99 if (key
->persample_msaa_dispatch
) {
100 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
101 nir_load_sample_id(b
));
103 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
108 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
112 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
113 struct brw_blorp_blit_vars
*v
)
115 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
117 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
118 nir_channel(b
, coord_transform
, 3));
119 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
120 nir_channel(b
, coord_transform
, 2));
122 return nir_ffma(b
, src_pos
, mul
, offset
);
126 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
127 struct brw_blorp_blit_vars
*v
)
129 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
130 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
131 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
132 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
133 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
134 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
136 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
137 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
138 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
139 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
141 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
143 nir_intrinsic_instr
*discard
=
144 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
145 discard
->src
[0] = nir_src_for_ssa(oob
);
146 nir_builder_instr_insert(b
, &discard
->instr
);
149 static nir_tex_instr
*
150 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
151 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
152 nir_alu_type dst_type
)
154 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
158 tex
->dest_type
= dst_type
;
159 tex
->is_array
= false;
160 tex
->is_shadow
= false;
162 /* Blorp only has one texture and it's bound at unit 0 */
165 tex
->texture_index
= 0;
166 tex
->sampler_index
= 0;
168 /* To properly handle 3-D and 2-D array textures, we pull the Z component
169 * from an input. TODO: This is a bit magic; we should probably make this
170 * more explicit in the future.
172 assert(pos
->num_components
>= 2);
173 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
174 nir_load_var(b
, v
->v_src_z
));
176 tex
->src
[0].src_type
= nir_tex_src_coord
;
177 tex
->src
[0].src
= nir_src_for_ssa(pos
);
178 tex
->coord_components
= 3;
180 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
186 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
187 nir_ssa_def
*pos
, nir_alu_type dst_type
)
190 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2, dst_type
);
192 assert(pos
->num_components
== 2);
193 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
194 tex
->src
[1].src_type
= nir_tex_src_lod
;
195 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
197 nir_builder_instr_insert(b
, &tex
->instr
);
199 return &tex
->dest
.ssa
;
203 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
204 nir_ssa_def
*pos
, nir_alu_type dst_type
)
207 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
209 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
210 tex
->src
[1].src_type
= nir_tex_src_lod
;
211 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
213 nir_builder_instr_insert(b
, &tex
->instr
);
215 return &tex
->dest
.ssa
;
219 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
220 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
223 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
224 mcs
!= NULL
? 3 : 2, dst_type
);
226 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
228 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
229 if (pos
->num_components
== 2) {
230 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
232 assert(pos
->num_components
== 3);
233 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
237 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
238 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
241 nir_builder_instr_insert(b
, &tex
->instr
);
243 return &tex
->dest
.ssa
;
247 blorp_nir_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
, nir_ssa_def
*pos
)
250 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
251 pos
, 1, nir_type_int
);
253 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
255 nir_builder_instr_insert(b
, &tex
->instr
);
257 return &tex
->dest
.ssa
;
261 nir_mask_shift_or(struct nir_builder
*b
, nir_ssa_def
*dst
, nir_ssa_def
*src
,
262 uint32_t src_mask
, int src_left_shift
)
264 nir_ssa_def
*masked
= nir_iand(b
, src
, nir_imm_int(b
, src_mask
));
266 nir_ssa_def
*shifted
;
267 if (src_left_shift
> 0) {
268 shifted
= nir_ishl(b
, masked
, nir_imm_int(b
, src_left_shift
));
269 } else if (src_left_shift
< 0) {
270 shifted
= nir_ushr(b
, masked
, nir_imm_int(b
, -src_left_shift
));
272 assert(src_left_shift
== 0);
276 return nir_ior(b
, dst
, shifted
);
280 * Emit code to compensate for the difference between Y and W tiling.
282 * This code modifies the X and Y coordinates according to the formula:
284 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
286 * (See brw_blorp_build_nir_shader).
288 static inline nir_ssa_def
*
289 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
291 assert(pos
->num_components
== 2);
292 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
293 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
295 /* Given X and Y coordinates that describe an address using Y tiling,
296 * translate to the X and Y coordinates that describe the same address
299 * If we break down the low order bits of X and Y, using a
300 * single letter to represent each low-order bit:
302 * X = A << 7 | 0bBCDEFGH
303 * Y = J << 5 | 0bKLMNP (1)
305 * Then we can apply the Y tiling formula to see the memory offset being
308 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
310 * If we apply the W detiling formula to this memory location, that the
311 * corresponding X' and Y' coordinates are:
313 * X' = A << 6 | 0bBCDPFH (3)
314 * Y' = J << 6 | 0bKLMNEG
316 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
317 * we need to make the following computation:
319 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
320 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
322 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
323 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
324 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
325 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
327 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
328 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
329 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
330 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
332 return nir_vec2(b
, x_W
, y_W
);
336 * Emit code to compensate for the difference between Y and W tiling.
338 * This code modifies the X and Y coordinates according to the formula:
340 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
342 * (See brw_blorp_build_nir_shader).
344 static inline nir_ssa_def
*
345 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
347 assert(pos
->num_components
== 2);
348 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
349 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
351 /* Applying the same logic as above, but in reverse, we obtain the
354 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
355 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
357 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
358 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
359 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
360 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
361 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
363 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
364 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
365 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
367 return nir_vec2(b
, x_Y
, y_Y
);
371 * Emit code to compensate for the difference between MSAA and non-MSAA
374 * This code modifies the X and Y coordinates according to the formula:
376 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
378 * (See brw_blorp_blit_program).
380 static inline nir_ssa_def
*
381 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
382 unsigned num_samples
, enum isl_msaa_layout layout
)
384 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
387 case ISL_MSAA_LAYOUT_NONE
:
388 assert(pos
->num_components
== 2);
390 case ISL_MSAA_LAYOUT_ARRAY
:
391 /* No translation needed */
393 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
394 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
395 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
396 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
397 nir_channel(b
, pos
, 2);
399 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
400 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
401 switch (num_samples
) {
404 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
405 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
408 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
409 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
410 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
412 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
413 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
414 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
415 if (num_samples
== 2) {
418 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
419 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
420 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
425 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
426 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
428 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
430 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
431 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
432 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
433 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
434 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
435 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
436 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
440 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
441 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
443 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
446 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
447 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
448 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
449 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
450 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
451 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
452 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
453 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
457 unreachable("Invalid number of samples for IMS layout");
460 return nir_vec2(b
, x_out
, y_out
);
464 unreachable("Invalid MSAA layout");
469 * Emit code to compensate for the difference between MSAA and non-MSAA
472 * This code modifies the X and Y coordinates according to the formula:
474 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
476 * (See brw_blorp_blit_program).
478 static inline nir_ssa_def
*
479 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
480 unsigned num_samples
, enum isl_msaa_layout layout
)
482 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
485 case ISL_MSAA_LAYOUT_NONE
:
486 /* No translation necessary, and S should already be zero. */
487 assert(pos
->num_components
== 2);
489 case ISL_MSAA_LAYOUT_ARRAY
:
490 /* No translation necessary. */
492 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
493 assert(pos
->num_components
== 2);
495 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
496 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
498 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
499 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
500 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
501 switch (num_samples
) {
504 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
505 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
506 * S = (X & 0b10) >> 1
508 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
509 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
510 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
511 * S = (Y & 0b10) | (X & 0b10) >> 1
513 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
514 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
515 if (num_samples
== 2) {
517 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
519 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
520 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
521 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
522 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
527 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
528 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
529 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
530 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
532 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
533 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
534 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
535 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
536 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
537 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
538 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
542 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
543 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
544 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
545 * S = (Y & 0b100) << 1 | (X & 0b100) |
546 * (Y & 0b10) | (X & 0b10) >> 1
548 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
549 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
550 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
551 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
552 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
553 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
554 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
555 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
559 unreachable("Invalid number of samples for IMS layout");
562 return nir_vec3(b
, x_out
, y_out
, s_out
);
566 unreachable("Invalid MSAA layout");
571 * Count the number of trailing 1 bits in the given value. For example:
573 * count_trailing_one_bits(0) == 0
574 * count_trailing_one_bits(7) == 3
575 * count_trailing_one_bits(11) == 2
577 static inline int count_trailing_one_bits(unsigned value
)
579 #ifdef HAVE___BUILTIN_CTZ
580 return __builtin_ctz(~value
);
582 return _mesa_bitcount(value
& ~(value
+ 1));
587 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
588 nir_ssa_def
*pos
, unsigned tex_samples
,
589 enum isl_aux_usage tex_aux_usage
,
590 nir_alu_type dst_type
)
592 /* If non-null, this is the outer-most if statement */
593 nir_if
*outer_if
= NULL
;
595 nir_variable
*color
=
596 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
598 nir_ssa_def
*mcs
= NULL
;
599 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
600 mcs
= blorp_nir_txf_ms_mcs(b
, v
, pos
);
602 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
604 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
606 * This ensures that when all samples have the same value, no numerical
607 * precision is lost, since each addition operation always adds two equal
608 * values, and summing two equal floating point values does not lose
611 * We perform this computation by treating the texture_data array as a
612 * stack and performing the following operations:
614 * - push sample 0 onto stack
615 * - push sample 1 onto stack
616 * - add top two stack entries
617 * - push sample 2 onto stack
618 * - push sample 3 onto stack
619 * - add top two stack entries
620 * - add top two stack entries
621 * - divide top stack entry by 4
623 * Note that after pushing sample i onto the stack, the number of add
624 * operations we do is equal to the number of trailing 1 bits in i. This
625 * works provided the total number of samples is a power of two, which it
626 * always is for i965.
628 * For integer formats, we replace the add operations with average
629 * operations and skip the final division.
631 nir_ssa_def
*texture_data
[5];
632 unsigned stack_depth
= 0;
633 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
634 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
636 /* Push sample i onto the stack */
637 assert(stack_depth
< ARRAY_SIZE(texture_data
));
639 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
640 nir_channel(b
, pos
, 1),
642 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
644 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
645 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
646 * suggests an optimization:
648 * "A simple optimization with probable large return in
649 * performance is to compare the MCS value to zero (indicating
650 * all samples are on sample slice 0), and sample only from
651 * sample slice 0 using ld2dss if MCS is zero."
653 * Note that in the case where the MCS value is zero, sampling from
654 * sample slice 0 using ld2dss and sampling from sample 0 using
655 * ld2dms are equivalent (since all samples are on sample slice 0).
656 * Since we have already sampled from sample 0, all we need to do is
657 * skip the remaining fetches and averaging if MCS is zero.
659 nir_ssa_def
*mcs_zero
=
660 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
661 if (tex_samples
== 16) {
662 mcs_zero
= nir_iand(b
, mcs_zero
,
663 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
666 nir_if
*if_stmt
= nir_if_create(b
->shader
);
667 if_stmt
->condition
= nir_src_for_ssa(mcs_zero
);
668 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
670 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
671 nir_store_var(b
, color
, texture_data
[0], 0xf);
673 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
677 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
678 assert(stack_depth
>= 2);
681 assert(dst_type
== nir_type_float
);
682 texture_data
[stack_depth
- 1] =
683 nir_fadd(b
, texture_data
[stack_depth
- 1],
684 texture_data
[stack_depth
]);
688 /* We should have just 1 sample on the stack now. */
689 assert(stack_depth
== 1);
691 texture_data
[0] = nir_fmul(b
, texture_data
[0],
692 nir_imm_float(b
, 1.0 / tex_samples
));
694 nir_store_var(b
, color
, texture_data
[0], 0xf);
697 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
699 return nir_load_var(b
, color
);
702 static inline nir_ssa_def
*
703 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
707 memset(&v
, 0, sizeof(v
));
711 return nir_build_imm(build
, 4, 32, v
);
715 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
716 unsigned tex_samples
,
717 const struct brw_blorp_blit_prog_key
*key
,
718 struct brw_blorp_blit_vars
*v
)
720 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
721 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
722 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
724 /* Translate coordinates to lay out the samples in a rectangular grid
725 * roughly corresponding to sample locations.
727 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
728 /* Adjust coordinates so that integers represent pixel centers rather
731 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
732 /* Clamp the X, Y texture coordinates to properly handle the sampling of
733 * texels on texture edges.
735 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
736 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
737 nir_channel(b
, rect_grid
, 1)));
739 /* Store the fractional parts to be used as bilinear interpolation
742 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
743 /* Round the float coordinates down to nearest integer */
744 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
746 nir_ssa_def
*tex_data
[4];
747 for (unsigned i
= 0; i
< 4; ++i
) {
748 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
749 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
750 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
752 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
753 nir_ssa_def
*sample_coords_int
= nir_f2i(b
, sample_coords
);
755 /* The MCS value we fetch has to match up with the pixel that we're
756 * sampling from. Since we sample from different pixels in each
757 * iteration of this "for" loop, the call to mcs_fetch() should be
758 * here inside the loop after computing the pixel coordinates.
760 nir_ssa_def
*mcs
= NULL
;
761 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
762 mcs
= blorp_nir_txf_ms_mcs(b
, v
, sample_coords_int
);
764 /* Compute sample index and map the sample index to a sample number.
765 * Sample index layout shows the numbering of slots in a rectangular
766 * grid of samples with in a pixel. Sample number layout shows the
767 * rectangular grid of samples roughly corresponding to the real sample
768 * locations with in a pixel.
769 * In case of 4x MSAA, layout of sample indices matches the layout of
777 * In case of 8x MSAA the two layouts don't match.
778 * sample index layout : --------- sample number layout : ---------
779 * | 0 | 1 | | 3 | 7 |
780 * --------- ---------
781 * | 2 | 3 | | 5 | 0 |
782 * --------- ---------
783 * | 4 | 5 | | 1 | 2 |
784 * --------- ---------
785 * | 6 | 7 | | 4 | 6 |
786 * --------- ---------
788 * Fortunately, this can be done fairly easily as:
789 * S' = (0x17306425 >> (S * 4)) & 0xf
791 * In the case of 16x MSAA the two layouts don't match.
792 * Sample index layout: Sample number layout:
793 * --------------------- ---------------------
794 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
795 * --------------------- ---------------------
796 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
797 * --------------------- ---------------------
798 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
799 * --------------------- ---------------------
800 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
801 * --------------------- ---------------------
803 * This is equivalent to
804 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
806 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
807 nir_ssa_def
*sample
=
808 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
809 key
->x_scale
* key
->y_scale
));
810 sample
= nir_f2i(b
, sample
);
812 if (tex_samples
== 8) {
813 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
814 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
815 nir_imm_int(b
, 0xf));
816 } else if (tex_samples
== 16) {
817 nir_ssa_def
*sample_low
=
818 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
819 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
820 nir_imm_int(b
, 0xf));
821 nir_ssa_def
*sample_high
=
822 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
823 nir_ishl(b
, nir_iadd(b
, sample
,
826 nir_imm_int(b
, 0xf));
828 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
829 sample_low
, sample_high
);
831 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
832 nir_channel(b
, sample_coords_int
, 1),
834 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
837 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
838 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
839 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
840 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
845 * Generator for WM programs used in BLORP blits.
847 * The bulk of the work done by the WM program is to wrap and unwrap the
848 * coordinate transformations used by the hardware to store surfaces in
849 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
850 * sample index for a multisampled surface) to a memory offset by the
851 * following formulas:
853 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
854 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
856 * For a single-sampled surface, or for a multisampled surface using
857 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
860 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
861 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
862 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
863 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
865 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
866 * embeds the sample number into bit 1 of the X and Y coordinates:
868 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
869 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
870 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
871 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
872 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
873 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
874 * S = (Y & 0b10) | (X & 0b10) >> 1
876 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
877 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
880 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
881 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
882 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
883 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
884 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
885 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
886 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
888 * For X tiling, tile() combines together the low-order bits of the X and Y
889 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
890 * bytes wide and 8 rows high:
892 * tile(x_tiled, X, Y, S) = A
893 * where A = tile_num << 12 | offset
894 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
895 * offset = (Y' & 0b111) << 9
896 * | (X & 0b111111111)
898 * Y' = Y + S * qpitch
899 * detile(x_tiled, A) = (X, Y, S)
903 * Y' = (tile_num / tile_pitch) << 3
904 * | (A & 0b111000000000) >> 9
905 * X' = (tile_num % tile_pitch) << 9
906 * | (A & 0b111111111)
908 * (In all tiling formulas, cpp is the number of bytes occupied by a single
909 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
910 * to fill the width of the surface, and qpitch is the spacing (in rows)
911 * between array slices).
913 * For Y tiling, tile() combines together the low-order bits of the X and Y
914 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
915 * bytes wide and 32 rows high:
917 * tile(y_tiled, X, Y, S) = A
918 * where A = tile_num << 12 | offset
919 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
920 * offset = (X' & 0b1110000) << 5
921 * | (Y' & 0b11111) << 4
924 * Y' = Y + S * qpitch
925 * detile(y_tiled, A) = (X, Y, S)
929 * Y' = (tile_num / tile_pitch) << 5
930 * | (A & 0b111110000) >> 4
931 * X' = (tile_num % tile_pitch) << 7
932 * | (A & 0b111000000000) >> 5
935 * For W tiling, tile() combines together the low-order bits of the X and Y
936 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
937 * bytes wide and 64 rows high (note that W tiling is only used for stencil
938 * buffers, which always have cpp = 1 and S=0):
940 * tile(w_tiled, X, Y, S) = A
941 * where A = tile_num << 12 | offset
942 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
943 * offset = (X' & 0b111000) << 6
944 * | (Y' & 0b111100) << 3
945 * | (X' & 0b100) << 2
951 * Y' = Y + S * qpitch
952 * detile(w_tiled, A) = (X, Y, S)
953 * where X = X' / cpp = X'
954 * Y = Y' % qpitch = Y'
956 * Y' = (tile_num / tile_pitch) << 6
957 * | (A & 0b111100000) >> 3
958 * | (A & 0b1000) >> 2
960 * X' = (tile_num % tile_pitch) << 6
961 * | (A & 0b111000000000) >> 6
962 * | (A & 0b10000) >> 2
966 * Finally, for a non-tiled surface, tile() simply combines together the X and
967 * Y coordinates in the natural way:
969 * tile(untiled, X, Y, S) = A
970 * where A = Y * pitch + X'
972 * Y' = Y + S * qpitch
973 * detile(untiled, A) = (X, Y, S)
980 * (In these formulas, pitch is the number of bytes occupied by a single row
984 brw_blorp_build_nir_shader(struct blorp_context
*blorp
,
985 const struct brw_blorp_blit_prog_key
*key
)
987 const struct brw_device_info
*devinfo
= blorp
->isl_dev
->info
;
988 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
991 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
992 /* If the destination image is W tiled and multisampled, then the thread
993 * must be dispatched once per sample, not once per pixel. This is
994 * necessary because after conversion between W and Y tiling, there's no
995 * guarantee that all samples corresponding to a single pixel will still
998 assert(key
->persample_msaa_dispatch
);
1002 /* We are blending, which means we won't have an opportunity to
1003 * translate the tiling and sample count for the texture surface. So
1004 * the surface state for the texture must be configured with the correct
1005 * tiling and sample count.
1007 assert(!key
->src_tiled_w
);
1008 assert(key
->tex_samples
== key
->src_samples
);
1009 assert(key
->tex_layout
== key
->src_layout
);
1010 assert(key
->tex_samples
> 0);
1013 if (key
->persample_msaa_dispatch
) {
1014 /* It only makes sense to do persample dispatch if the render target is
1015 * configured as multisampled.
1017 assert(key
->rt_samples
> 0);
1020 /* Make sure layout is consistent with sample count */
1021 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1022 (key
->tex_samples
<= 1));
1023 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1024 (key
->rt_samples
<= 1));
1025 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1026 (key
->src_samples
<= 1));
1027 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1028 (key
->dst_samples
<= 1));
1031 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
1033 struct brw_blorp_blit_vars v
;
1034 brw_blorp_blit_vars_init(&b
, &v
, key
);
1036 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1038 /* Render target and texture hardware don't support W tiling until Gen8. */
1039 const bool rt_tiled_w
= false;
1040 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1042 /* The address that data will be written to is determined by the
1043 * coordinates supplied to the WM thread and the tiling and sample count of
1044 * the render target, according to the formula:
1046 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1048 * If the actual tiling and sample count of the destination surface are not
1049 * the same as the configuration of the render target, then these
1050 * coordinates are wrong and we have to adjust them to compensate for the
1053 if (rt_tiled_w
!= key
->dst_tiled_w
||
1054 key
->rt_samples
!= key
->dst_samples
||
1055 key
->rt_layout
!= key
->dst_layout
) {
1056 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1058 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1059 if (rt_tiled_w
!= key
->dst_tiled_w
)
1060 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1061 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1062 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1066 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1068 * That is: X, Y and S now contain the true coordinates and sample index of
1069 * the data that the WM thread should output.
1071 * If we need to kill pixels that are outside the destination rectangle,
1072 * now is the time to do it.
1074 if (key
->use_kill
) {
1075 assert(!(key
->blend
&& key
->blit_scaled
));
1076 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1079 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f(&b
, dst_pos
), &v
);
1080 if (dst_pos
->num_components
== 3) {
1081 /* The sample coordinate is an integer that we want left alone but
1082 * blorp_blit_apply_transform() blindly applies the transform to all
1083 * three coordinates. Grab the original sample index.
1085 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1086 nir_channel(&b
, src_pos
, 1),
1087 nir_channel(&b
, dst_pos
, 2));
1090 /* If the source image is not multisampled, then we want to fetch sample
1091 * number 0, because that's the only sample there is.
1093 if (key
->src_samples
== 1)
1094 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1096 /* X, Y, and S are now the coordinates of the pixel in the source image
1097 * that we want to texture from. Exception: if we are blending, then S is
1098 * irrelevant, because we are going to fetch all samples.
1100 if (key
->blend
&& !key
->blit_scaled
) {
1101 /* Resolves (effecively) use texelFetch, so we need integers and we
1102 * don't care about the sample index if we got one.
1104 src_pos
= nir_f2i(&b
, nir_channels(&b
, src_pos
, 0x3));
1106 if (devinfo
->gen
== 6) {
1107 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1108 * blending we need with a single linear-interpolated texture lookup
1109 * at the center of the sample. The texture coordinates to be odd
1110 * integers so that they correspond to the center of a 2x2 block
1111 * representing the four samples that maxe up a pixel. So we need
1112 * to multiply our X and Y coordinates each by 2 and then add 1.
1114 src_pos
= nir_ishl(&b
, src_pos
, nir_imm_int(&b
, 1));
1115 src_pos
= nir_iadd(&b
, src_pos
, nir_imm_int(&b
, 1));
1116 src_pos
= nir_i2f(&b
, src_pos
);
1117 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1119 /* Gen7+ hardware doesn't automaticaly blend. */
1120 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1122 key
->texture_data_type
);
1124 } else if (key
->blend
&& key
->blit_scaled
) {
1125 assert(!key
->use_kill
);
1126 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1128 if (key
->bilinear_filter
) {
1129 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1131 /* We're going to use texelFetch, so we need integers */
1132 if (src_pos
->num_components
== 2) {
1133 src_pos
= nir_f2i(&b
, src_pos
);
1135 assert(src_pos
->num_components
== 3);
1136 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i(&b
, src_pos
), 0),
1137 nir_channel(&b
, nir_f2i(&b
, src_pos
), 1),
1138 nir_channel(&b
, src_pos
, 2));
1141 /* We aren't blending, which means we just want to fetch a single
1142 * sample from the source surface. The address that we want to fetch
1143 * from is related to the X, Y and S values according to the formula:
1145 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1147 * If the actual tiling and sample count of the source surface are
1148 * not the same as the configuration of the texture, then we need to
1149 * adjust the coordinates to compensate for the difference.
1151 if (tex_tiled_w
!= key
->src_tiled_w
||
1152 key
->tex_samples
!= key
->src_samples
||
1153 key
->tex_layout
!= key
->src_layout
) {
1154 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1156 /* Now (X, Y, S) = detile(src_tiling, offset) */
1157 if (tex_tiled_w
!= key
->src_tiled_w
)
1158 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1159 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1160 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1164 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1166 * In other words: X, Y, and S now contain values which, when passed to
1167 * the texturing unit, will cause data to be read from the correct
1168 * memory location. So we can fetch the texel now.
1170 if (key
->src_samples
== 1) {
1171 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1173 nir_ssa_def
*mcs
= NULL
;
1174 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1175 mcs
= blorp_nir_txf_ms_mcs(&b
, &v
, src_pos
);
1177 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1182 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1188 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1189 struct blorp_params
*params
,
1190 const struct brw_blorp_blit_prog_key
*prog_key
)
1192 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1193 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1196 const unsigned *program
;
1197 unsigned program_size
;
1198 struct brw_blorp_prog_data prog_data
;
1200 /* Try and compile with NIR first. If that fails, fall back to the old
1201 * method of building shaders manually.
1203 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, prog_key
);
1204 struct brw_wm_prog_key wm_key
;
1205 brw_blorp_init_wm_prog_key(&wm_key
);
1206 wm_key
.tex
.compressed_multisample_layout_mask
=
1207 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1208 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1209 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1211 program
= brw_blorp_compile_nir_shader(blorp
, nir
, &wm_key
, false,
1212 &prog_data
, &program_size
);
1214 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1215 program
, program_size
,
1216 &prog_data
, sizeof(prog_data
),
1217 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1221 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1222 GLfloat src0
, GLfloat src1
,
1223 GLfloat dst0
, GLfloat dst1
,
1226 float scale
= (src1
- src0
) / (dst1
- dst0
);
1228 /* When not mirroring a coordinate (say, X), we need:
1229 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1231 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1233 * blorp program uses "round toward zero" to convert the
1234 * transformed floating point coordinates to integer coordinates,
1235 * whereas the behaviour we actually want is "round to nearest",
1236 * so 0.5 provides the necessary correction.
1238 xform
->multiplier
= scale
;
1239 xform
->offset
= src0
+ (-dst0
+ 0.5f
) * scale
;
1241 /* When mirroring X we need:
1242 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1244 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1246 xform
->multiplier
= -scale
;
1247 xform
->offset
= src0
+ (dst1
- 0.5f
) * scale
;
1252 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
1253 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
1255 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
1258 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
1260 * which is simply adding 4 then modding by 8 (or anding with 7).
1262 * We then may need to apply workarounds for textureGather hardware bugs.
1264 static enum isl_channel_select
1265 swizzle_to_scs(GLenum swizzle
)
1267 return (enum isl_channel_select
)((swizzle
+ 4) & 7);
1271 surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1272 struct brw_blorp_surface_info
*info
)
1274 /* This only makes sense for a single level and array slice */
1275 assert(info
->view
.levels
== 1 && info
->view
.array_len
== 1);
1277 /* Just bail if we have nothing to do. */
1278 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1279 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1280 info
->surf
.levels
== 0 && info
->surf
.logical_level0_px
.array_len
== 0)
1283 uint32_t x_offset_sa
, y_offset_sa
;
1284 isl_surf_get_image_offset_sa(&info
->surf
, info
->view
.base_level
,
1285 info
->view
.base_array_layer
, 0,
1286 &x_offset_sa
, &y_offset_sa
);
1288 uint32_t byte_offset
;
1289 isl_tiling_get_intratile_offset_sa(isl_dev
, info
->surf
.tiling
,
1290 info
->view
.format
, info
->surf
.row_pitch
,
1291 x_offset_sa
, y_offset_sa
,
1293 &info
->tile_x_sa
, &info
->tile_y_sa
);
1294 info
->addr
.offset
+= byte_offset
;
1296 /* TODO: Once this file gets converted to C, we shouls just use designated
1299 struct isl_surf_init_info init_info
= { 0, };
1301 init_info
.dim
= ISL_SURF_DIM_2D
;
1302 init_info
.format
= ISL_FORMAT_R8_UINT
;
1304 minify(info
->surf
.logical_level0_px
.width
, info
->view
.base_level
);
1306 minify(info
->surf
.logical_level0_px
.height
, info
->view
.base_level
);
1307 init_info
.depth
= 1;
1308 init_info
.levels
= 1;
1309 init_info
.array_len
= 1;
1310 init_info
.samples
= info
->surf
.samples
;
1311 init_info
.min_pitch
= info
->surf
.row_pitch
;
1312 init_info
.usage
= info
->surf
.usage
;
1313 init_info
.tiling_flags
= 1 << info
->surf
.tiling
;
1315 isl_surf_init_s(isl_dev
, &info
->surf
, &init_info
);
1316 assert(info
->surf
.row_pitch
== init_info
.min_pitch
);
1318 /* The view is also different now. */
1319 info
->view
.base_level
= 0;
1320 info
->view
.levels
= 1;
1321 info
->view
.base_array_layer
= 0;
1322 info
->view
.array_len
= 1;
1326 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1327 struct brw_blorp_surface_info
*info
)
1329 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1331 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1332 surf_convert_to_single_slice(isl_dev
, info
);
1334 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1335 info
->surf
.samples
= 1;
1336 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1340 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1341 struct brw_blorp_surface_info
*info
)
1343 assert(info
->surf
.tiling
== ISL_TILING_W
);
1345 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1346 surf_convert_to_single_slice(isl_dev
, info
);
1348 /* On gen7+, we don't have interleaved multisampling for color render
1349 * targets so we have to fake it.
1351 * TODO: Are we sure we don't also need to fake it on gen6?
1353 if (isl_dev
->info
->gen
> 6 &&
1354 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1355 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1356 info
->surf
.samples
= 1;
1357 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1360 if (isl_dev
->info
->gen
== 6) {
1361 /* Gen6 stencil buffers have a very large alignment coming in from the
1362 * miptree. It's out-of-bounds for what the surface state can handle.
1363 * Since we have a single layer and level, it doesn't really matter as
1364 * long as we don't pass a bogus value into isl_surf_fill_state().
1366 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1369 /* Now that we've converted everything to a simple 2-D surface with only
1370 * one miplevel, we can go about retiling it.
1372 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1373 info
->surf
.tiling
= ISL_TILING_Y0
;
1374 info
->surf
.logical_level0_px
.width
=
1375 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1376 info
->surf
.logical_level0_px
.height
=
1377 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1378 info
->tile_x_sa
*= 2;
1379 info
->tile_y_sa
/= 2;
1383 blorp_blit(struct blorp_batch
*batch
,
1384 const struct blorp_surf
*src_surf
,
1385 unsigned src_level
, unsigned src_layer
,
1386 enum isl_format src_format
, int src_swizzle
,
1387 const struct blorp_surf
*dst_surf
,
1388 unsigned dst_level
, unsigned dst_layer
,
1389 enum isl_format dst_format
,
1390 float src_x0
, float src_y0
,
1391 float src_x1
, float src_y1
,
1392 float dst_x0
, float dst_y0
,
1393 float dst_x1
, float dst_y1
,
1394 GLenum filter
, bool mirror_x
, bool mirror_y
)
1396 const struct brw_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1398 struct blorp_params params
;
1399 blorp_params_init(¶ms
);
1401 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
1402 src_layer
, src_format
, false);
1403 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
1404 dst_layer
, dst_format
, true);
1406 struct brw_blorp_blit_prog_key wm_prog_key
;
1407 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1409 if (isl_format_has_sint_channel(params
.src
.view
.format
)) {
1410 wm_prog_key
.texture_data_type
= nir_type_int
;
1411 } else if (isl_format_has_uint_channel(params
.src
.view
.format
)) {
1412 wm_prog_key
.texture_data_type
= nir_type_uint
;
1414 wm_prog_key
.texture_data_type
= nir_type_float
;
1417 /* Scaled blitting or not. */
1418 wm_prog_key
.blit_scaled
=
1419 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
1420 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
1422 /* Scaling factors used for bilinear filtering in multisample scaled
1425 if (params
.src
.surf
.samples
== 16)
1426 wm_prog_key
.x_scale
= 4.0f
;
1428 wm_prog_key
.x_scale
= 2.0f
;
1429 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
1431 if (filter
== GL_LINEAR
&&
1432 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1)
1433 wm_prog_key
.bilinear_filter
= true;
1435 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
1436 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
1437 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
1438 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
1439 /* We are downsampling a non-integer color buffer, so blend.
1441 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
1443 * "If the source formats are integer types or stencil values, a
1444 * single sample's value is selected for each pixel."
1446 * This implies we should not blend in that case.
1448 wm_prog_key
.blend
= true;
1451 /* src_samples and dst_samples are the true sample counts */
1452 wm_prog_key
.src_samples
= params
.src
.surf
.samples
;
1453 wm_prog_key
.dst_samples
= params
.dst
.surf
.samples
;
1455 wm_prog_key
.tex_aux_usage
= params
.src
.aux_usage
;
1457 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1460 wm_prog_key
.src_layout
= params
.src
.surf
.msaa_layout
;
1461 wm_prog_key
.dst_layout
= params
.dst
.surf
.msaa_layout
;
1463 /* Round floating point values to nearest integer to avoid "off by one texel"
1464 * kind of errors when blitting.
1466 params
.x0
= params
.wm_inputs
.discard_rect
.x0
= roundf(dst_x0
);
1467 params
.y0
= params
.wm_inputs
.discard_rect
.y0
= roundf(dst_y0
);
1468 params
.x1
= params
.wm_inputs
.discard_rect
.x1
= roundf(dst_x1
);
1469 params
.y1
= params
.wm_inputs
.discard_rect
.y1
= roundf(dst_y1
);
1471 params
.wm_inputs
.rect_grid
.x1
=
1472 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
1473 wm_prog_key
.x_scale
- 1.0f
;
1474 params
.wm_inputs
.rect_grid
.y1
=
1475 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
1476 wm_prog_key
.y_scale
- 1.0f
;
1478 brw_blorp_setup_coord_transform(¶ms
.wm_inputs
.coord_transform
[0],
1479 src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
1480 brw_blorp_setup_coord_transform(¶ms
.wm_inputs
.coord_transform
[1],
1481 src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
1483 /* For some texture types, we need to pass the layer through the sampler. */
1484 params
.wm_inputs
.src_z
= params
.src
.z_offset
;
1486 if (devinfo
->gen
> 6 &&
1487 params
.dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1488 assert(params
.dst
.surf
.samples
> 1);
1490 /* We must expand the rectangle we send through the rendering pipeline,
1491 * to account for the fact that we are mapping the destination region as
1492 * single-sampled when it is in fact multisampled. We must also align
1493 * it to a multiple of the multisampling pattern, because the
1494 * differences between multisampled and single-sampled surface formats
1495 * will mean that pixels are scrambled within the multisampling pattern.
1496 * TODO: what if this makes the coordinates too large?
1498 * Note: this only works if the destination surface uses the IMS layout.
1499 * If it's UMS, then we have no choice but to set up the rendering
1500 * pipeline as multisampled.
1502 switch (params
.dst
.surf
.samples
) {
1504 params
.x0
= ROUND_DOWN_TO(params
.x0
* 2, 4);
1505 params
.y0
= ROUND_DOWN_TO(params
.y0
, 4);
1506 params
.x1
= ALIGN(params
.x1
* 2, 4);
1507 params
.y1
= ALIGN(params
.y1
, 4);
1510 params
.x0
= ROUND_DOWN_TO(params
.x0
* 2, 4);
1511 params
.y0
= ROUND_DOWN_TO(params
.y0
* 2, 4);
1512 params
.x1
= ALIGN(params
.x1
* 2, 4);
1513 params
.y1
= ALIGN(params
.y1
* 2, 4);
1516 params
.x0
= ROUND_DOWN_TO(params
.x0
* 4, 8);
1517 params
.y0
= ROUND_DOWN_TO(params
.y0
* 2, 4);
1518 params
.x1
= ALIGN(params
.x1
* 4, 8);
1519 params
.y1
= ALIGN(params
.y1
* 2, 4);
1522 params
.x0
= ROUND_DOWN_TO(params
.x0
* 4, 8);
1523 params
.y0
= ROUND_DOWN_TO(params
.y0
* 4, 8);
1524 params
.x1
= ALIGN(params
.x1
* 4, 8);
1525 params
.y1
= ALIGN(params
.y1
* 4, 8);
1528 unreachable("Unrecognized sample count in brw_blorp_blit_params ctor");
1531 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
.dst
);
1533 wm_prog_key
.use_kill
= true;
1536 if (params
.dst
.surf
.tiling
== ISL_TILING_W
) {
1537 /* We must modify the rectangle we send through the rendering pipeline
1538 * (and the size and x/y offset of the destination surface), to account
1539 * for the fact that we are mapping it as Y-tiled when it is in fact
1542 * Both Y tiling and W tiling can be understood as organizations of
1543 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1544 * is different, but the layout of the 32-byte sub-tiles within the 4k
1545 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1546 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1547 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1549 * Therefore, to account for the layout differences within the 32-byte
1550 * sub-tiles, we must expand the rectangle so the X coordinates of its
1551 * edges are multiples of 8 (the W sub-tile width), and its Y
1552 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1553 * Then we need to scale the X and Y coordinates of the rectangle to
1554 * account for the differences in aspect ratio between the Y and W
1555 * sub-tiles. We need to modify the layer width and height similarly.
1557 * A correction needs to be applied when MSAA is in use: since
1558 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1559 * we need to align the Y coordinates to multiples of 8, so that when
1560 * they are divided by two they are still multiples of 4.
1562 * Note: Since the x/y offset of the surface will be applied using the
1563 * SURFACE_STATE command packet, it will be invisible to the swizzling
1564 * code in the shader; therefore it needs to be in a multiple of the
1565 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1566 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1567 * buffer), and the miplevel alignment used for stencil buffers is 8
1568 * pixels horizontally and either 4 or 8 pixels vertically (see
1569 * intel_horizontal_texture_alignment_unit() and
1570 * intel_vertical_texture_alignment_unit()).
1572 * Note: Also, since the SURFACE_STATE command packet can only apply
1573 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1574 * vertically, it is important that the offsets will be multiples of
1575 * these sizes after they are converted into Y-tiled coordinates.
1576 * Fortunately they will be, since we know from above that the offsets
1577 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1578 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1580 * TODO: what if this makes the coordinates (or the texture size) too
1583 const unsigned x_align
= 8, y_align
= params
.dst
.surf
.samples
!= 0 ? 8 : 4;
1584 params
.x0
= ROUND_DOWN_TO(params
.x0
, x_align
) * 2;
1585 params
.y0
= ROUND_DOWN_TO(params
.y0
, y_align
) / 2;
1586 params
.x1
= ALIGN(params
.x1
, x_align
) * 2;
1587 params
.y1
= ALIGN(params
.y1
, y_align
) / 2;
1589 /* Retile the surface to Y-tiled */
1590 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
.dst
);
1592 wm_prog_key
.dst_tiled_w
= true;
1593 wm_prog_key
.use_kill
= true;
1595 if (params
.dst
.surf
.samples
> 1) {
1596 /* If the destination surface is a W-tiled multisampled stencil
1597 * buffer that we're mapping as Y tiled, then we need to arrange for
1598 * the WM program to run once per sample rather than once per pixel,
1599 * because the memory layout of related samples doesn't match between
1602 wm_prog_key
.persample_msaa_dispatch
= true;
1606 if (devinfo
->gen
< 8 && params
.src
.surf
.tiling
== ISL_TILING_W
) {
1607 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1608 * Broadwell adds support for sampling from stencil.
1610 * See the comments above concerning x/y offset alignment for the
1611 * destination surface.
1613 * TODO: what if this makes the texture size too large?
1615 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
.src
);
1617 wm_prog_key
.src_tiled_w
= true;
1620 /* tex_samples and rt_samples are the sample counts that are set up in
1623 wm_prog_key
.tex_samples
= params
.src
.surf
.samples
;
1624 wm_prog_key
.rt_samples
= params
.dst
.surf
.samples
;
1626 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1627 * use to access the source and destination surfaces.
1629 wm_prog_key
.tex_layout
= params
.src
.surf
.msaa_layout
;
1630 wm_prog_key
.rt_layout
= params
.dst
.surf
.msaa_layout
;
1632 if (params
.src
.surf
.samples
> 0 && params
.dst
.surf
.samples
> 1) {
1633 /* We are blitting from a multisample buffer to a multisample buffer, so
1634 * we must preserve samples within a pixel. This means we have to
1635 * arrange for the WM program to run once per sample rather than once
1638 wm_prog_key
.persample_msaa_dispatch
= true;
1641 brw_blorp_get_blit_kernel(batch
->blorp
, ¶ms
, &wm_prog_key
);
1643 for (unsigned i
= 0; i
< 4; i
++) {
1644 params
.src
.view
.channel_select
[i
] =
1645 swizzle_to_scs(GET_SWZ(src_swizzle
, i
));
1648 batch
->blorp
->exec(batch
, ¶ms
);