2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/nir/nir_builder.h"
26 #include "blorp_priv.h"
27 #include "brw_meta_util.h"
29 /* header-only include needed for _mesa_unorm_to_float and friends. */
30 #include "mesa/main/format_utils.h"
32 #define FILE_DEBUG_FLAG DEBUG_BLORP
34 static const bool split_blorp_blit_debug
= false;
37 * Enum to specify the order of arguments in a sampler message
39 enum sampler_message_arg
41 SAMPLER_MESSAGE_ARG_U_FLOAT
,
42 SAMPLER_MESSAGE_ARG_V_FLOAT
,
43 SAMPLER_MESSAGE_ARG_U_INT
,
44 SAMPLER_MESSAGE_ARG_V_INT
,
45 SAMPLER_MESSAGE_ARG_R_INT
,
46 SAMPLER_MESSAGE_ARG_SI_INT
,
47 SAMPLER_MESSAGE_ARG_MCS_INT
,
48 SAMPLER_MESSAGE_ARG_ZERO_INT
,
51 struct brw_blorp_blit_vars
{
52 /* Input values from brw_blorp_wm_inputs */
53 nir_variable
*v_discard_rect
;
54 nir_variable
*v_rect_grid
;
55 nir_variable
*v_coord_transform
;
56 nir_variable
*v_src_z
;
57 nir_variable
*v_src_offset
;
58 nir_variable
*v_dst_offset
;
61 nir_variable
*frag_coord
;
64 nir_variable
*color_out
;
68 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
69 const struct brw_blorp_blit_prog_key
*key
)
71 /* Blended and scaled blits never use pixel discard. */
72 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
74 #define LOAD_INPUT(name, type)\
75 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
77 LOAD_INPUT(discard_rect
, glsl_vec4_type())
78 LOAD_INPUT(rect_grid
, glsl_vec4_type())
79 LOAD_INPUT(coord_transform
, glsl_vec4_type())
80 LOAD_INPUT(src_z
, glsl_uint_type())
81 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
82 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
86 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
87 glsl_vec4_type(), "gl_FragCoord");
88 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
89 v
->frag_coord
->data
.origin_upper_left
= true;
91 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
92 glsl_vec4_type(), "gl_FragColor");
93 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
97 blorp_blit_get_frag_coords(nir_builder
*b
,
98 const struct brw_blorp_blit_prog_key
*key
,
99 struct brw_blorp_blit_vars
*v
)
101 nir_ssa_def
*coord
= nir_f2i(b
, nir_load_var(b
, v
->frag_coord
));
103 /* Account for destination surface intratile offset
105 * Transformation parameters giving translation from destination to source
106 * coordinates don't take into account possible intra-tile destination
107 * offset. Therefore it has to be first subtracted from the incoming
108 * coordinates. Vertices are set up based on coordinates containing the
111 if (key
->need_dst_offset
)
112 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
114 if (key
->persample_msaa_dispatch
) {
115 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
116 nir_load_sample_id(b
));
118 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
123 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
127 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
128 struct brw_blorp_blit_vars
*v
)
130 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
132 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
133 nir_channel(b
, coord_transform
, 3));
134 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
135 nir_channel(b
, coord_transform
, 2));
137 return nir_ffma(b
, src_pos
, mul
, offset
);
141 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
142 struct brw_blorp_blit_vars
*v
)
144 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
145 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
146 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
147 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
148 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
149 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
151 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
152 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
153 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
154 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
156 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
158 nir_intrinsic_instr
*discard
=
159 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
160 discard
->src
[0] = nir_src_for_ssa(oob
);
161 nir_builder_instr_insert(b
, &discard
->instr
);
164 static nir_tex_instr
*
165 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
166 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
167 nir_alu_type dst_type
)
169 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
173 tex
->dest_type
= dst_type
;
174 tex
->is_array
= false;
175 tex
->is_shadow
= false;
177 /* Blorp only has one texture and it's bound at unit 0 */
180 tex
->texture_index
= 0;
181 tex
->sampler_index
= 0;
183 /* To properly handle 3-D and 2-D array textures, we pull the Z component
184 * from an input. TODO: This is a bit magic; we should probably make this
185 * more explicit in the future.
187 assert(pos
->num_components
>= 2);
188 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
189 nir_load_var(b
, v
->v_src_z
));
191 tex
->src
[0].src_type
= nir_tex_src_coord
;
192 tex
->src
[0].src
= nir_src_for_ssa(pos
);
193 tex
->coord_components
= 3;
195 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
201 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
202 nir_ssa_def
*pos
, nir_alu_type dst_type
)
205 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2, dst_type
);
207 assert(pos
->num_components
== 2);
208 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
209 tex
->src
[1].src_type
= nir_tex_src_lod
;
210 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
212 nir_builder_instr_insert(b
, &tex
->instr
);
214 return &tex
->dest
.ssa
;
218 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
219 nir_ssa_def
*pos
, nir_alu_type dst_type
)
222 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
224 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
225 tex
->src
[1].src_type
= nir_tex_src_lod
;
226 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
228 nir_builder_instr_insert(b
, &tex
->instr
);
230 return &tex
->dest
.ssa
;
234 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
235 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
238 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
239 mcs
!= NULL
? 3 : 2, dst_type
);
241 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
243 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
244 if (pos
->num_components
== 2) {
245 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
247 assert(pos
->num_components
== 3);
248 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
252 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
253 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
256 nir_builder_instr_insert(b
, &tex
->instr
);
258 return &tex
->dest
.ssa
;
262 blorp_nir_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
, nir_ssa_def
*pos
)
265 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
266 pos
, 1, nir_type_int
);
268 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
270 nir_builder_instr_insert(b
, &tex
->instr
);
272 return &tex
->dest
.ssa
;
276 nir_mask_shift_or(struct nir_builder
*b
, nir_ssa_def
*dst
, nir_ssa_def
*src
,
277 uint32_t src_mask
, int src_left_shift
)
279 nir_ssa_def
*masked
= nir_iand(b
, src
, nir_imm_int(b
, src_mask
));
281 nir_ssa_def
*shifted
;
282 if (src_left_shift
> 0) {
283 shifted
= nir_ishl(b
, masked
, nir_imm_int(b
, src_left_shift
));
284 } else if (src_left_shift
< 0) {
285 shifted
= nir_ushr(b
, masked
, nir_imm_int(b
, -src_left_shift
));
287 assert(src_left_shift
== 0);
291 return nir_ior(b
, dst
, shifted
);
295 * Emit code to compensate for the difference between Y and W tiling.
297 * This code modifies the X and Y coordinates according to the formula:
299 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
301 * (See brw_blorp_build_nir_shader).
303 static inline nir_ssa_def
*
304 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
306 assert(pos
->num_components
== 2);
307 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
308 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
310 /* Given X and Y coordinates that describe an address using Y tiling,
311 * translate to the X and Y coordinates that describe the same address
314 * If we break down the low order bits of X and Y, using a
315 * single letter to represent each low-order bit:
317 * X = A << 7 | 0bBCDEFGH
318 * Y = J << 5 | 0bKLMNP (1)
320 * Then we can apply the Y tiling formula to see the memory offset being
323 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
325 * If we apply the W detiling formula to this memory location, that the
326 * corresponding X' and Y' coordinates are:
328 * X' = A << 6 | 0bBCDPFH (3)
329 * Y' = J << 6 | 0bKLMNEG
331 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
332 * we need to make the following computation:
334 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
335 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
337 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
338 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
339 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
340 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
342 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
343 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
344 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
345 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
347 return nir_vec2(b
, x_W
, y_W
);
351 * Emit code to compensate for the difference between Y and W tiling.
353 * This code modifies the X and Y coordinates according to the formula:
355 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
357 * (See brw_blorp_build_nir_shader).
359 static inline nir_ssa_def
*
360 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
362 assert(pos
->num_components
== 2);
363 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
364 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
366 /* Applying the same logic as above, but in reverse, we obtain the
369 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
370 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
372 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
373 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
374 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
375 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
376 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
378 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
379 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
380 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
382 return nir_vec2(b
, x_Y
, y_Y
);
386 * Emit code to compensate for the difference between MSAA and non-MSAA
389 * This code modifies the X and Y coordinates according to the formula:
391 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
393 * (See brw_blorp_blit_program).
395 static inline nir_ssa_def
*
396 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
397 unsigned num_samples
, enum isl_msaa_layout layout
)
399 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
402 case ISL_MSAA_LAYOUT_NONE
:
403 assert(pos
->num_components
== 2);
405 case ISL_MSAA_LAYOUT_ARRAY
:
406 /* No translation needed */
408 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
409 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
410 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
411 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
412 nir_channel(b
, pos
, 2);
414 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
415 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
416 switch (num_samples
) {
419 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
420 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
423 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
424 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
425 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
427 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
428 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
429 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
430 if (num_samples
== 2) {
433 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
434 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
435 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
440 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
441 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
443 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
445 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
446 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
447 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
448 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
449 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
450 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
451 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
455 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
456 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
458 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
461 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
462 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
463 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
464 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
465 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
466 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
467 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
468 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
472 unreachable("Invalid number of samples for IMS layout");
475 return nir_vec2(b
, x_out
, y_out
);
479 unreachable("Invalid MSAA layout");
484 * Emit code to compensate for the difference between MSAA and non-MSAA
487 * This code modifies the X and Y coordinates according to the formula:
489 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
491 * (See brw_blorp_blit_program).
493 static inline nir_ssa_def
*
494 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
495 unsigned num_samples
, enum isl_msaa_layout layout
)
497 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
500 case ISL_MSAA_LAYOUT_NONE
:
501 /* No translation necessary, and S should already be zero. */
502 assert(pos
->num_components
== 2);
504 case ISL_MSAA_LAYOUT_ARRAY
:
505 /* No translation necessary. */
507 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
508 assert(pos
->num_components
== 2);
510 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
511 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
513 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
514 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
515 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
516 switch (num_samples
) {
519 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
520 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
521 * S = (X & 0b10) >> 1
523 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
524 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
525 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
526 * S = (Y & 0b10) | (X & 0b10) >> 1
528 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
529 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
530 if (num_samples
== 2) {
532 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
534 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
535 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
536 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
537 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
542 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
543 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
544 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
545 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
547 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
548 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
549 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
550 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
551 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
552 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
553 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
557 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
558 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
559 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
560 * S = (Y & 0b100) << 1 | (X & 0b100) |
561 * (Y & 0b10) | (X & 0b10) >> 1
563 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
564 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
565 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
566 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
567 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
568 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
569 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
570 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
574 unreachable("Invalid number of samples for IMS layout");
577 return nir_vec3(b
, x_out
, y_out
, s_out
);
581 unreachable("Invalid MSAA layout");
586 * Count the number of trailing 1 bits in the given value. For example:
588 * count_trailing_one_bits(0) == 0
589 * count_trailing_one_bits(7) == 3
590 * count_trailing_one_bits(11) == 2
592 static inline int count_trailing_one_bits(unsigned value
)
594 #ifdef HAVE___BUILTIN_CTZ
595 return __builtin_ctz(~value
);
597 return _mesa_bitcount(value
& ~(value
+ 1));
602 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
603 nir_ssa_def
*pos
, unsigned tex_samples
,
604 enum isl_aux_usage tex_aux_usage
,
605 nir_alu_type dst_type
)
607 /* If non-null, this is the outer-most if statement */
608 nir_if
*outer_if
= NULL
;
610 nir_variable
*color
=
611 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
613 nir_ssa_def
*mcs
= NULL
;
614 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
615 mcs
= blorp_nir_txf_ms_mcs(b
, v
, pos
);
617 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
619 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
621 * This ensures that when all samples have the same value, no numerical
622 * precision is lost, since each addition operation always adds two equal
623 * values, and summing two equal floating point values does not lose
626 * We perform this computation by treating the texture_data array as a
627 * stack and performing the following operations:
629 * - push sample 0 onto stack
630 * - push sample 1 onto stack
631 * - add top two stack entries
632 * - push sample 2 onto stack
633 * - push sample 3 onto stack
634 * - add top two stack entries
635 * - add top two stack entries
636 * - divide top stack entry by 4
638 * Note that after pushing sample i onto the stack, the number of add
639 * operations we do is equal to the number of trailing 1 bits in i. This
640 * works provided the total number of samples is a power of two, which it
641 * always is for i965.
643 * For integer formats, we replace the add operations with average
644 * operations and skip the final division.
646 nir_ssa_def
*texture_data
[5];
647 unsigned stack_depth
= 0;
648 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
649 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
651 /* Push sample i onto the stack */
652 assert(stack_depth
< ARRAY_SIZE(texture_data
));
654 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
655 nir_channel(b
, pos
, 1),
657 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
659 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
660 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
661 * suggests an optimization:
663 * "A simple optimization with probable large return in
664 * performance is to compare the MCS value to zero (indicating
665 * all samples are on sample slice 0), and sample only from
666 * sample slice 0 using ld2dss if MCS is zero."
668 * Note that in the case where the MCS value is zero, sampling from
669 * sample slice 0 using ld2dss and sampling from sample 0 using
670 * ld2dms are equivalent (since all samples are on sample slice 0).
671 * Since we have already sampled from sample 0, all we need to do is
672 * skip the remaining fetches and averaging if MCS is zero.
674 nir_ssa_def
*mcs_zero
=
675 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
676 if (tex_samples
== 16) {
677 mcs_zero
= nir_iand(b
, mcs_zero
,
678 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
681 nir_if
*if_stmt
= nir_if_create(b
->shader
);
682 if_stmt
->condition
= nir_src_for_ssa(mcs_zero
);
683 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
685 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
686 nir_store_var(b
, color
, texture_data
[0], 0xf);
688 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
692 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
693 assert(stack_depth
>= 2);
696 assert(dst_type
== nir_type_float
);
697 texture_data
[stack_depth
- 1] =
698 nir_fadd(b
, texture_data
[stack_depth
- 1],
699 texture_data
[stack_depth
]);
703 /* We should have just 1 sample on the stack now. */
704 assert(stack_depth
== 1);
706 texture_data
[0] = nir_fmul(b
, texture_data
[0],
707 nir_imm_float(b
, 1.0 / tex_samples
));
709 nir_store_var(b
, color
, texture_data
[0], 0xf);
712 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
714 return nir_load_var(b
, color
);
717 static inline nir_ssa_def
*
718 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
722 memset(&v
, 0, sizeof(v
));
726 return nir_build_imm(build
, 4, 32, v
);
730 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
731 unsigned tex_samples
,
732 const struct brw_blorp_blit_prog_key
*key
,
733 struct brw_blorp_blit_vars
*v
)
735 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
736 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
737 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
739 /* Translate coordinates to lay out the samples in a rectangular grid
740 * roughly corresponding to sample locations.
742 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
743 /* Adjust coordinates so that integers represent pixel centers rather
746 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
747 /* Clamp the X, Y texture coordinates to properly handle the sampling of
748 * texels on texture edges.
750 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
751 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
752 nir_channel(b
, rect_grid
, 1)));
754 /* Store the fractional parts to be used as bilinear interpolation
757 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
758 /* Round the float coordinates down to nearest integer */
759 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
761 nir_ssa_def
*tex_data
[4];
762 for (unsigned i
= 0; i
< 4; ++i
) {
763 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
764 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
765 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
767 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
768 nir_ssa_def
*sample_coords_int
= nir_f2i(b
, sample_coords
);
770 /* The MCS value we fetch has to match up with the pixel that we're
771 * sampling from. Since we sample from different pixels in each
772 * iteration of this "for" loop, the call to mcs_fetch() should be
773 * here inside the loop after computing the pixel coordinates.
775 nir_ssa_def
*mcs
= NULL
;
776 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
777 mcs
= blorp_nir_txf_ms_mcs(b
, v
, sample_coords_int
);
779 /* Compute sample index and map the sample index to a sample number.
780 * Sample index layout shows the numbering of slots in a rectangular
781 * grid of samples with in a pixel. Sample number layout shows the
782 * rectangular grid of samples roughly corresponding to the real sample
783 * locations with in a pixel.
784 * In case of 4x MSAA, layout of sample indices matches the layout of
792 * In case of 8x MSAA the two layouts don't match.
793 * sample index layout : --------- sample number layout : ---------
794 * | 0 | 1 | | 3 | 7 |
795 * --------- ---------
796 * | 2 | 3 | | 5 | 0 |
797 * --------- ---------
798 * | 4 | 5 | | 1 | 2 |
799 * --------- ---------
800 * | 6 | 7 | | 4 | 6 |
801 * --------- ---------
803 * Fortunately, this can be done fairly easily as:
804 * S' = (0x17306425 >> (S * 4)) & 0xf
806 * In the case of 16x MSAA the two layouts don't match.
807 * Sample index layout: Sample number layout:
808 * --------------------- ---------------------
809 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
810 * --------------------- ---------------------
811 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
812 * --------------------- ---------------------
813 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
814 * --------------------- ---------------------
815 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
816 * --------------------- ---------------------
818 * This is equivalent to
819 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
821 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
822 nir_ssa_def
*sample
=
823 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
824 key
->x_scale
* key
->y_scale
));
825 sample
= nir_f2i(b
, sample
);
827 if (tex_samples
== 8) {
828 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
829 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
830 nir_imm_int(b
, 0xf));
831 } else if (tex_samples
== 16) {
832 nir_ssa_def
*sample_low
=
833 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
834 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
835 nir_imm_int(b
, 0xf));
836 nir_ssa_def
*sample_high
=
837 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
838 nir_ishl(b
, nir_iadd(b
, sample
,
841 nir_imm_int(b
, 0xf));
843 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
844 sample_low
, sample_high
);
846 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
847 nir_channel(b
, sample_coords_int
, 1),
849 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
852 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
853 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
854 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
855 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
859 /** Perform a color bit-cast operation
861 * For copy operations involving CCS, we may need to use different formats for
862 * the source and destination surfaces. The two formats must both be UINT
863 * formats and must have the same size but may have different bit layouts.
864 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
865 * to R16G16_UINT. This function generates code to shuffle bits around to get
866 * us from one to the other.
869 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
870 const struct brw_blorp_blit_prog_key
*key
)
872 assert(key
->texture_data_type
== nir_type_uint
);
874 if (key
->dst_bpc
> key
->src_bpc
) {
875 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
876 nir_ssa_def
*dst_chan
[2] = { u
, u
};
878 unsigned dst_idx
= 0;
879 for (unsigned i
= 0; i
< 4; i
++) {
880 nir_ssa_def
*shifted
= nir_ishl(b
, nir_channel(b
, color
, i
),
881 nir_imm_int(b
, shift
));
883 dst_chan
[dst_idx
] = shifted
;
885 dst_chan
[dst_idx
] = nir_ior(b
, dst_chan
[dst_idx
], shifted
);
888 shift
+= key
->src_bpc
;
889 if (shift
>= key
->dst_bpc
) {
895 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], u
, u
);
897 assert(key
->dst_bpc
< key
->src_bpc
);
899 nir_ssa_def
*mask
= nir_imm_int(b
, ~0u >> (32 - key
->dst_bpc
));
901 nir_ssa_def
*dst_chan
[4];
902 unsigned src_idx
= 0;
904 for (unsigned i
= 0; i
< 4; i
++) {
905 dst_chan
[i
] = nir_iand(b
, nir_ushr(b
, nir_channel(b
, color
, src_idx
),
906 nir_imm_int(b
, shift
)),
908 shift
+= key
->dst_bpc
;
909 if (shift
>= key
->src_bpc
) {
915 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], dst_chan
[2], dst_chan
[3]);
920 * Generator for WM programs used in BLORP blits.
922 * The bulk of the work done by the WM program is to wrap and unwrap the
923 * coordinate transformations used by the hardware to store surfaces in
924 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
925 * sample index for a multisampled surface) to a memory offset by the
926 * following formulas:
928 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
929 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
931 * For a single-sampled surface, or for a multisampled surface using
932 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
935 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
936 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
937 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
938 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
940 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
941 * embeds the sample number into bit 1 of the X and Y coordinates:
943 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
944 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
945 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
946 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
947 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
948 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
949 * S = (Y & 0b10) | (X & 0b10) >> 1
951 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
952 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
955 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
956 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
957 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
958 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
959 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
960 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
961 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
963 * For X tiling, tile() combines together the low-order bits of the X and Y
964 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
965 * bytes wide and 8 rows high:
967 * tile(x_tiled, X, Y, S) = A
968 * where A = tile_num << 12 | offset
969 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
970 * offset = (Y' & 0b111) << 9
971 * | (X & 0b111111111)
973 * Y' = Y + S * qpitch
974 * detile(x_tiled, A) = (X, Y, S)
978 * Y' = (tile_num / tile_pitch) << 3
979 * | (A & 0b111000000000) >> 9
980 * X' = (tile_num % tile_pitch) << 9
981 * | (A & 0b111111111)
983 * (In all tiling formulas, cpp is the number of bytes occupied by a single
984 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
985 * to fill the width of the surface, and qpitch is the spacing (in rows)
986 * between array slices).
988 * For Y tiling, tile() combines together the low-order bits of the X and Y
989 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
990 * bytes wide and 32 rows high:
992 * tile(y_tiled, X, Y, S) = A
993 * where A = tile_num << 12 | offset
994 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
995 * offset = (X' & 0b1110000) << 5
996 * | (Y' & 0b11111) << 4
999 * Y' = Y + S * qpitch
1000 * detile(y_tiled, A) = (X, Y, S)
1001 * where X = X' / cpp
1004 * Y' = (tile_num / tile_pitch) << 5
1005 * | (A & 0b111110000) >> 4
1006 * X' = (tile_num % tile_pitch) << 7
1007 * | (A & 0b111000000000) >> 5
1010 * For W tiling, tile() combines together the low-order bits of the X and Y
1011 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1012 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1013 * buffers, which always have cpp = 1 and S=0):
1015 * tile(w_tiled, X, Y, S) = A
1016 * where A = tile_num << 12 | offset
1017 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1018 * offset = (X' & 0b111000) << 6
1019 * | (Y' & 0b111100) << 3
1020 * | (X' & 0b100) << 2
1021 * | (Y' & 0b10) << 2
1022 * | (X' & 0b10) << 1
1026 * Y' = Y + S * qpitch
1027 * detile(w_tiled, A) = (X, Y, S)
1028 * where X = X' / cpp = X'
1029 * Y = Y' % qpitch = Y'
1030 * S = Y / qpitch = 0
1031 * Y' = (tile_num / tile_pitch) << 6
1032 * | (A & 0b111100000) >> 3
1033 * | (A & 0b1000) >> 2
1035 * X' = (tile_num % tile_pitch) << 6
1036 * | (A & 0b111000000000) >> 6
1037 * | (A & 0b10000) >> 2
1038 * | (A & 0b100) >> 1
1041 * Finally, for a non-tiled surface, tile() simply combines together the X and
1042 * Y coordinates in the natural way:
1044 * tile(untiled, X, Y, S) = A
1045 * where A = Y * pitch + X'
1047 * Y' = Y + S * qpitch
1048 * detile(untiled, A) = (X, Y, S)
1049 * where X = X' / cpp
1055 * (In these formulas, pitch is the number of bytes occupied by a single row
1059 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1060 const struct brw_blorp_blit_prog_key
*key
)
1062 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1063 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1066 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1067 /* If the destination image is W tiled and multisampled, then the thread
1068 * must be dispatched once per sample, not once per pixel. This is
1069 * necessary because after conversion between W and Y tiling, there's no
1070 * guarantee that all samples corresponding to a single pixel will still
1073 assert(key
->persample_msaa_dispatch
);
1077 /* We are blending, which means we won't have an opportunity to
1078 * translate the tiling and sample count for the texture surface. So
1079 * the surface state for the texture must be configured with the correct
1080 * tiling and sample count.
1082 assert(!key
->src_tiled_w
);
1083 assert(key
->tex_samples
== key
->src_samples
);
1084 assert(key
->tex_layout
== key
->src_layout
);
1085 assert(key
->tex_samples
> 0);
1088 if (key
->persample_msaa_dispatch
) {
1089 /* It only makes sense to do persample dispatch if the render target is
1090 * configured as multisampled.
1092 assert(key
->rt_samples
> 0);
1095 /* Make sure layout is consistent with sample count */
1096 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1097 (key
->tex_samples
<= 1));
1098 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1099 (key
->rt_samples
<= 1));
1100 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1101 (key
->src_samples
<= 1));
1102 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1103 (key
->dst_samples
<= 1));
1106 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1108 struct brw_blorp_blit_vars v
;
1109 brw_blorp_blit_vars_init(&b
, &v
, key
);
1111 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1113 /* Render target and texture hardware don't support W tiling until Gen8. */
1114 const bool rt_tiled_w
= false;
1115 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1117 /* The address that data will be written to is determined by the
1118 * coordinates supplied to the WM thread and the tiling and sample count of
1119 * the render target, according to the formula:
1121 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1123 * If the actual tiling and sample count of the destination surface are not
1124 * the same as the configuration of the render target, then these
1125 * coordinates are wrong and we have to adjust them to compensate for the
1128 if (rt_tiled_w
!= key
->dst_tiled_w
||
1129 key
->rt_samples
!= key
->dst_samples
||
1130 key
->rt_layout
!= key
->dst_layout
) {
1131 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1133 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1134 if (rt_tiled_w
!= key
->dst_tiled_w
)
1135 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1136 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1137 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1141 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1143 * That is: X, Y and S now contain the true coordinates and sample index of
1144 * the data that the WM thread should output.
1146 * If we need to kill pixels that are outside the destination rectangle,
1147 * now is the time to do it.
1149 if (key
->use_kill
) {
1150 assert(!(key
->blend
&& key
->blit_scaled
));
1151 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1154 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f(&b
, dst_pos
), &v
);
1155 if (dst_pos
->num_components
== 3) {
1156 /* The sample coordinate is an integer that we want left alone but
1157 * blorp_blit_apply_transform() blindly applies the transform to all
1158 * three coordinates. Grab the original sample index.
1160 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1161 nir_channel(&b
, src_pos
, 1),
1162 nir_channel(&b
, dst_pos
, 2));
1165 /* If the source image is not multisampled, then we want to fetch sample
1166 * number 0, because that's the only sample there is.
1168 if (key
->src_samples
== 1)
1169 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1171 /* X, Y, and S are now the coordinates of the pixel in the source image
1172 * that we want to texture from. Exception: if we are blending, then S is
1173 * irrelevant, because we are going to fetch all samples.
1175 if (key
->blend
&& !key
->blit_scaled
) {
1176 /* Resolves (effecively) use texelFetch, so we need integers and we
1177 * don't care about the sample index if we got one.
1179 src_pos
= nir_f2i(&b
, nir_channels(&b
, src_pos
, 0x3));
1181 if (devinfo
->gen
== 6) {
1182 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1183 * blending we need with a single linear-interpolated texture lookup
1184 * at the center of the sample. The texture coordinates to be odd
1185 * integers so that they correspond to the center of a 2x2 block
1186 * representing the four samples that maxe up a pixel. So we need
1187 * to multiply our X and Y coordinates each by 2 and then add 1.
1189 src_pos
= nir_ishl(&b
, src_pos
, nir_imm_int(&b
, 1));
1190 src_pos
= nir_iadd(&b
, src_pos
, nir_imm_int(&b
, 1));
1191 src_pos
= nir_i2f(&b
, src_pos
);
1192 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1194 /* Gen7+ hardware doesn't automaticaly blend. */
1195 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1197 key
->texture_data_type
);
1199 } else if (key
->blend
&& key
->blit_scaled
) {
1200 assert(!key
->use_kill
);
1201 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1203 if (key
->bilinear_filter
) {
1204 color
= blorp_nir_tex(&b
, &v
, src_pos
, key
->texture_data_type
);
1206 /* We're going to use texelFetch, so we need integers */
1207 if (src_pos
->num_components
== 2) {
1208 src_pos
= nir_f2i(&b
, src_pos
);
1210 assert(src_pos
->num_components
== 3);
1211 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i(&b
, src_pos
), 0),
1212 nir_channel(&b
, nir_f2i(&b
, src_pos
), 1),
1213 nir_channel(&b
, src_pos
, 2));
1216 /* We aren't blending, which means we just want to fetch a single
1217 * sample from the source surface. The address that we want to fetch
1218 * from is related to the X, Y and S values according to the formula:
1220 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1222 * If the actual tiling and sample count of the source surface are
1223 * not the same as the configuration of the texture, then we need to
1224 * adjust the coordinates to compensate for the difference.
1226 if (tex_tiled_w
!= key
->src_tiled_w
||
1227 key
->tex_samples
!= key
->src_samples
||
1228 key
->tex_layout
!= key
->src_layout
) {
1229 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1231 /* Now (X, Y, S) = detile(src_tiling, offset) */
1232 if (tex_tiled_w
!= key
->src_tiled_w
)
1233 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1234 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1235 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1239 if (key
->need_src_offset
)
1240 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1242 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1244 * In other words: X, Y, and S now contain values which, when passed to
1245 * the texturing unit, will cause data to be read from the correct
1246 * memory location. So we can fetch the texel now.
1248 if (key
->src_samples
== 1) {
1249 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1251 nir_ssa_def
*mcs
= NULL
;
1252 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1253 mcs
= blorp_nir_txf_ms_mcs(&b
, &v
, src_pos
);
1255 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1260 if (key
->dst_bpc
!= key
->src_bpc
)
1261 color
= bit_cast_color(&b
, color
, key
);
1264 /* The destination image is bound as a red texture three times as wide
1265 * as the actual image. Our shader is effectively running one color
1266 * component at a time. We need to pick off the appropriate component
1267 * from the source color and write that to destination red.
1269 assert(dst_pos
->num_components
== 2);
1271 nir_umod(&b
, nir_channel(&b
, dst_pos
, 0), nir_imm_int(&b
, 3));
1273 nir_ssa_def
*color_component
=
1274 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1275 nir_channel(&b
, color
, 0),
1276 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1277 nir_channel(&b
, color
, 1),
1278 nir_channel(&b
, color
, 2)));
1280 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1281 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1284 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1290 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1291 struct blorp_params
*params
,
1292 const struct brw_blorp_blit_prog_key
*prog_key
)
1294 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1295 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1298 void *mem_ctx
= ralloc_context(NULL
);
1300 const unsigned *program
;
1301 unsigned program_size
;
1302 struct brw_wm_prog_data prog_data
;
1304 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1305 nir
->info
->name
= ralloc_strdup(nir
, "BLORP-blit");
1307 struct brw_wm_prog_key wm_key
;
1308 brw_blorp_init_wm_prog_key(&wm_key
);
1309 wm_key
.tex
.compressed_multisample_layout_mask
=
1310 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1311 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1312 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1314 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1315 &prog_data
, &program_size
);
1317 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1318 program
, program_size
,
1319 &prog_data
.base
, sizeof(prog_data
),
1320 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1322 ralloc_free(mem_ctx
);
1326 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1327 GLfloat src0
, GLfloat src1
,
1328 GLfloat dst0
, GLfloat dst1
,
1331 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1333 /* When not mirroring a coordinate (say, X), we need:
1334 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1336 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1338 * blorp program uses "round toward zero" to convert the
1339 * transformed floating point coordinates to integer coordinates,
1340 * whereas the behaviour we actually want is "round to nearest",
1341 * so 0.5 provides the necessary correction.
1343 xform
->multiplier
= scale
;
1344 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1346 /* When mirroring X we need:
1347 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1349 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1351 xform
->multiplier
= -scale
;
1352 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1357 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1358 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1360 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1361 struct isl_extent2d px_size_sa
=
1362 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1363 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1364 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1365 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1366 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1368 *tile_x_px
= info
->tile_x_sa
;
1369 *tile_y_px
= info
->tile_y_sa
;
1374 surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1375 struct brw_blorp_surface_info
*info
)
1377 /* Just bail if we have nothing to do. */
1378 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1379 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1380 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1383 /* If this gets triggered then we've gotten here twice which. This
1384 * shouldn't happen thanks to the above early return.
1386 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1388 uint32_t layer
= 0, z
= 0;
1389 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1390 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1392 layer
= info
->view
.base_array_layer
;
1394 uint32_t x_offset_sa
, y_offset_sa
;
1395 isl_surf_get_image_offset_sa(&info
->surf
, info
->view
.base_level
,
1396 layer
, z
, &x_offset_sa
, &y_offset_sa
);
1398 uint32_t byte_offset
;
1399 isl_tiling_get_intratile_offset_sa(isl_dev
, info
->surf
.tiling
,
1400 info
->surf
.format
, info
->surf
.row_pitch
,
1401 x_offset_sa
, y_offset_sa
,
1403 &info
->tile_x_sa
, &info
->tile_y_sa
);
1404 info
->addr
.offset
+= byte_offset
;
1406 const uint32_t slice_width_px
=
1407 minify(info
->surf
.logical_level0_px
.width
, info
->view
.base_level
);
1408 const uint32_t slice_height_px
=
1409 minify(info
->surf
.logical_level0_px
.height
, info
->view
.base_level
);
1411 uint32_t tile_x_px
, tile_y_px
;
1412 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1414 struct isl_surf_init_info init_info
= {
1415 .dim
= ISL_SURF_DIM_2D
,
1416 .format
= info
->surf
.format
,
1417 .width
= slice_width_px
+ tile_x_px
,
1418 .height
= slice_height_px
+ tile_y_px
,
1422 .samples
= info
->surf
.samples
,
1423 .min_pitch
= info
->surf
.row_pitch
,
1424 .usage
= info
->surf
.usage
,
1425 .tiling_flags
= 1 << info
->surf
.tiling
,
1428 isl_surf_init_s(isl_dev
, &info
->surf
, &init_info
);
1429 assert(info
->surf
.row_pitch
== init_info
.min_pitch
);
1431 /* The view is also different now. */
1432 info
->view
.base_level
= 0;
1433 info
->view
.levels
= 1;
1434 info
->view
.base_array_layer
= 0;
1435 info
->view
.array_len
= 1;
1440 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1441 struct brw_blorp_surface_info
*info
)
1443 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1445 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1446 surf_convert_to_single_slice(isl_dev
, info
);
1448 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1449 info
->surf
.samples
= 1;
1450 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1454 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1455 struct brw_blorp_surface_info
*info
)
1457 assert(info
->surf
.tiling
== ISL_TILING_W
);
1459 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1460 surf_convert_to_single_slice(isl_dev
, info
);
1462 /* On gen7+, we don't have interleaved multisampling for color render
1463 * targets so we have to fake it.
1465 * TODO: Are we sure we don't also need to fake it on gen6?
1467 if (isl_dev
->info
->gen
> 6 &&
1468 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1469 surf_fake_interleaved_msaa(isl_dev
, info
);
1472 if (isl_dev
->info
->gen
== 6) {
1473 /* Gen6 stencil buffers have a very large alignment coming in from the
1474 * miptree. It's out-of-bounds for what the surface state can handle.
1475 * Since we have a single layer and level, it doesn't really matter as
1476 * long as we don't pass a bogus value into isl_surf_fill_state().
1478 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1481 /* Now that we've converted everything to a simple 2-D surface with only
1482 * one miplevel, we can go about retiling it.
1484 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1485 info
->surf
.tiling
= ISL_TILING_Y0
;
1486 info
->surf
.logical_level0_px
.width
=
1487 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1488 info
->surf
.logical_level0_px
.height
=
1489 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1490 info
->tile_x_sa
*= 2;
1491 info
->tile_y_sa
/= 2;
1495 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1497 /* The current code doesn't support offsets into the aux buffers. This
1498 * should be possible, but we need to make sure the offset is page
1499 * aligned for both the surface and the aux buffer surface. Generally
1500 * this mean using the page aligned offset for the aux buffer.
1502 * Currently the cases where we must split the blit are limited to cases
1503 * where we don't have a aux buffer.
1505 if (surf
->aux_addr
.buffer
!= NULL
)
1508 /* We can't support splitting the blit for gen <= 7, because the qpitch
1509 * size is calculated by the hardware based on the surface height for
1510 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1512 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1519 can_shrink_surfaces(const struct blorp_params
*params
)
1522 can_shrink_surface(¶ms
->src
) &&
1523 can_shrink_surface(¶ms
->dst
);
1527 get_max_surface_size(const struct gen_device_info
*devinfo
,
1528 const struct blorp_params
*params
)
1530 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1531 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1532 return max
>> 4; /* A smaller restriction when debug is enabled */
1538 double src0
, src1
, dst0
, dst1
;
1543 struct blt_axis x
, y
;
1547 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1548 struct brw_blorp_surface_info
*info
,
1549 uint32_t *x
, uint32_t *width
)
1551 surf_convert_to_single_slice(isl_dev
, info
);
1553 info
->surf
.logical_level0_px
.width
*= 3;
1554 info
->surf
.phys_level0_sa
.width
*= 3;
1558 enum isl_format red_format
;
1559 switch (info
->view
.format
) {
1560 case ISL_FORMAT_R8G8B8_UNORM
:
1561 red_format
= ISL_FORMAT_R8_UNORM
;
1563 case ISL_FORMAT_R8G8B8_UINT
:
1564 red_format
= ISL_FORMAT_R8_UINT
;
1566 case ISL_FORMAT_R16G16B16_UNORM
:
1567 red_format
= ISL_FORMAT_R16_UNORM
;
1569 case ISL_FORMAT_R16G16B16_UINT
:
1570 red_format
= ISL_FORMAT_R16_UINT
;
1572 case ISL_FORMAT_R32G32B32_UINT
:
1573 red_format
= ISL_FORMAT_R32_UINT
;
1576 unreachable("Invalid RGB copy destination format");
1578 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1579 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1580 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1581 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1583 info
->surf
.format
= info
->view
.format
= red_format
;
1587 fake_dest_rgb_with_red(const struct isl_device
*dev
,
1588 struct blorp_params
*params
,
1589 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1590 struct blt_coords
*coords
)
1592 /* Handle RGB destinations for blorp_copy */
1593 const struct isl_format_layout
*dst_fmtl
=
1594 isl_format_get_layout(params
->dst
.surf
.format
);
1596 if (dst_fmtl
->bpb
% 3 == 0) {
1597 uint32_t dst_x
= coords
->x
.dst0
;
1598 uint32_t dst_width
= coords
->x
.dst1
- dst_x
;
1599 surf_fake_rgb_with_red(dev
, ¶ms
->dst
,
1600 &dst_x
, &dst_width
);
1601 coords
->x
.dst0
= dst_x
;
1602 coords
->x
.dst1
= dst_x
+ dst_width
;
1603 wm_prog_key
->dst_rgb
= true;
1604 wm_prog_key
->need_dst_offset
= true;
1608 enum blit_shrink_status
{
1610 BLIT_WIDTH_SHRINK
= 1,
1611 BLIT_HEIGHT_SHRINK
= 2,
1614 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1615 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1616 * returned, then the blit was successful.
1618 static enum blit_shrink_status
1619 try_blorp_blit(struct blorp_batch
*batch
,
1620 struct blorp_params
*params
,
1621 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1622 struct blt_coords
*coords
)
1624 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1626 fake_dest_rgb_with_red(batch
->blorp
->isl_dev
, params
, wm_prog_key
, coords
);
1628 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1629 wm_prog_key
->texture_data_type
= nir_type_int
;
1630 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1631 wm_prog_key
->texture_data_type
= nir_type_uint
;
1633 wm_prog_key
->texture_data_type
= nir_type_float
;
1636 /* src_samples and dst_samples are the true sample counts */
1637 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1638 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1640 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1642 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1645 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1646 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1648 /* Round floating point values to nearest integer to avoid "off by one texel"
1649 * kind of errors when blitting.
1651 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1652 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1653 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1654 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1656 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1657 coords
->x
.src0
, coords
->x
.src1
,
1658 coords
->x
.dst0
, coords
->x
.dst1
,
1660 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1661 coords
->y
.src0
, coords
->y
.src1
,
1662 coords
->y
.dst0
, coords
->y
.dst1
,
1665 if (devinfo
->gen
> 6 &&
1666 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1667 assert(params
->dst
.surf
.samples
> 1);
1669 /* We must expand the rectangle we send through the rendering pipeline,
1670 * to account for the fact that we are mapping the destination region as
1671 * single-sampled when it is in fact multisampled. We must also align
1672 * it to a multiple of the multisampling pattern, because the
1673 * differences between multisampled and single-sampled surface formats
1674 * will mean that pixels are scrambled within the multisampling pattern.
1675 * TODO: what if this makes the coordinates too large?
1677 * Note: this only works if the destination surface uses the IMS layout.
1678 * If it's UMS, then we have no choice but to set up the rendering
1679 * pipeline as multisampled.
1681 struct isl_extent2d px_size_sa
=
1682 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1683 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1684 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1685 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1686 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1688 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1690 wm_prog_key
->use_kill
= true;
1691 wm_prog_key
->need_dst_offset
= true;
1694 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1695 /* We must modify the rectangle we send through the rendering pipeline
1696 * (and the size and x/y offset of the destination surface), to account
1697 * for the fact that we are mapping it as Y-tiled when it is in fact
1700 * Both Y tiling and W tiling can be understood as organizations of
1701 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1702 * is different, but the layout of the 32-byte sub-tiles within the 4k
1703 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1704 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1705 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1707 * Therefore, to account for the layout differences within the 32-byte
1708 * sub-tiles, we must expand the rectangle so the X coordinates of its
1709 * edges are multiples of 8 (the W sub-tile width), and its Y
1710 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1711 * Then we need to scale the X and Y coordinates of the rectangle to
1712 * account for the differences in aspect ratio between the Y and W
1713 * sub-tiles. We need to modify the layer width and height similarly.
1715 * A correction needs to be applied when MSAA is in use: since
1716 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1717 * we need to align the Y coordinates to multiples of 8, so that when
1718 * they are divided by two they are still multiples of 4.
1720 * Note: Since the x/y offset of the surface will be applied using the
1721 * SURFACE_STATE command packet, it will be invisible to the swizzling
1722 * code in the shader; therefore it needs to be in a multiple of the
1723 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1724 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1725 * buffer), and the miplevel alignment used for stencil buffers is 8
1726 * pixels horizontally and either 4 or 8 pixels vertically (see
1727 * intel_horizontal_texture_alignment_unit() and
1728 * intel_vertical_texture_alignment_unit()).
1730 * Note: Also, since the SURFACE_STATE command packet can only apply
1731 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1732 * vertically, it is important that the offsets will be multiples of
1733 * these sizes after they are converted into Y-tiled coordinates.
1734 * Fortunately they will be, since we know from above that the offsets
1735 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1736 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1738 * TODO: what if this makes the coordinates (or the texture size) too
1741 const unsigned x_align
= 8;
1742 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1743 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1744 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1745 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1746 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1748 /* Retile the surface to Y-tiled */
1749 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1751 wm_prog_key
->dst_tiled_w
= true;
1752 wm_prog_key
->use_kill
= true;
1753 wm_prog_key
->need_dst_offset
= true;
1755 if (params
->dst
.surf
.samples
> 1) {
1756 /* If the destination surface is a W-tiled multisampled stencil
1757 * buffer that we're mapping as Y tiled, then we need to arrange for
1758 * the WM program to run once per sample rather than once per pixel,
1759 * because the memory layout of related samples doesn't match between
1762 wm_prog_key
->persample_msaa_dispatch
= true;
1766 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1767 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1768 * Broadwell adds support for sampling from stencil.
1770 * See the comments above concerning x/y offset alignment for the
1771 * destination surface.
1773 * TODO: what if this makes the texture size too large?
1775 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1777 wm_prog_key
->src_tiled_w
= true;
1778 wm_prog_key
->need_src_offset
= true;
1781 /* tex_samples and rt_samples are the sample counts that are set up in
1784 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1785 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1787 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1788 * use to access the source and destination surfaces.
1790 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1791 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1793 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1794 /* We are blitting from a multisample buffer to a multisample buffer, so
1795 * we must preserve samples within a pixel. This means we have to
1796 * arrange for the WM program to run once per sample rather than once
1799 wm_prog_key
->persample_msaa_dispatch
= true;
1802 params
->num_samples
= params
->dst
.surf
.samples
;
1804 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
1805 assert(wm_prog_key
->need_src_offset
);
1806 surf_get_intratile_offset_px(¶ms
->src
,
1807 ¶ms
->wm_inputs
.src_offset
.x
,
1808 ¶ms
->wm_inputs
.src_offset
.y
);
1811 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
1812 assert(wm_prog_key
->need_dst_offset
);
1813 surf_get_intratile_offset_px(¶ms
->dst
,
1814 ¶ms
->wm_inputs
.dst_offset
.x
,
1815 ¶ms
->wm_inputs
.dst_offset
.y
);
1816 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
1817 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
1818 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
1819 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
1822 /* For some texture types, we need to pass the layer through the sampler. */
1823 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
1825 brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
);
1827 unsigned result
= 0;
1828 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
1829 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
1830 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
1831 result
|= BLIT_WIDTH_SHRINK
;
1832 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
1833 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
1834 result
|= BLIT_HEIGHT_SHRINK
;
1837 batch
->blorp
->exec(batch
, params
);
1843 /* Adjust split blit source coordinates for the current destination
1847 adjust_split_source_coords(const struct blt_axis
*orig
,
1848 struct blt_axis
*split_coords
,
1851 /* When scale is greater than 0, then we are growing from the start, so
1852 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
1853 * source range shrinks from the end. In that case src0 is adjusted by
1854 * delta1, and src1 is adjusted by delta0.
1856 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
1857 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
1858 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
1859 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
1862 static const struct isl_extent2d
1863 get_px_size_sa(const struct isl_surf
*surf
)
1865 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
1867 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
1870 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
1874 shrink_surface_params(const struct isl_device
*dev
,
1875 struct brw_blorp_surface_info
*info
,
1876 double *x0
, double *x1
, double *y0
, double *y1
)
1878 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
1879 struct isl_extent2d px_size_sa
;
1882 surf_convert_to_single_slice(dev
, info
);
1884 px_size_sa
= get_px_size_sa(&info
->surf
);
1886 /* Because this gets called after we lower compressed images, the tile
1887 * offsets may be non-zero and we need to incorporate them in our
1890 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
1891 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
1892 isl_tiling_get_intratile_offset_sa(dev
, info
->surf
.tiling
,
1893 info
->surf
.format
, info
->surf
.row_pitch
,
1894 x_offset_sa
, y_offset_sa
,
1896 &info
->tile_x_sa
, &info
->tile_y_sa
);
1898 info
->addr
.offset
+= byte_offset
;
1900 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
1903 info
->tile_x_sa
= 0;
1905 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
1908 info
->tile_y_sa
= 0;
1910 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
1911 info
->surf
.logical_level0_px
.width
= size
;
1912 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
1914 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
1915 info
->surf
.logical_level0_px
.height
= size
;
1916 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
1920 shrink_surfaces(const struct isl_device
*dev
,
1921 struct blorp_params
*params
,
1922 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1923 struct blt_coords
*coords
)
1925 /* Shrink source surface */
1926 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
1927 &coords
->y
.src0
, &coords
->y
.src1
);
1928 wm_prog_key
->need_src_offset
= false;
1930 /* Shrink destination surface */
1931 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
1932 &coords
->y
.dst0
, &coords
->y
.dst1
);
1933 wm_prog_key
->need_dst_offset
= false;
1937 do_blorp_blit(struct blorp_batch
*batch
,
1938 const struct blorp_params
*orig_params
,
1939 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1940 const struct blt_coords
*orig
)
1942 struct blorp_params params
;
1943 struct blt_coords blit_coords
;
1944 struct blt_coords split_coords
= *orig
;
1945 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
1946 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
1947 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
1948 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
1954 bool x_done
, y_done
;
1955 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
1957 params
= *orig_params
;
1958 blit_coords
= split_coords
;
1960 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
1962 enum blit_shrink_status result
=
1963 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
1965 if (result
& BLIT_WIDTH_SHRINK
) {
1968 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
1969 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
1971 if (result
& BLIT_HEIGHT_SHRINK
) {
1974 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
1975 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
1979 assert(can_shrink_surfaces(orig_params
));
1984 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
1985 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
1988 } else if (y_done
) {
1989 split_coords
.x
.dst0
+= w
;
1990 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
1991 split_coords
.y
.dst0
= orig
->y
.dst0
;
1992 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
1993 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
1995 split_coords
.y
.dst0
+= h
;
1996 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
1997 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2003 blorp_blit(struct blorp_batch
*batch
,
2004 const struct blorp_surf
*src_surf
,
2005 unsigned src_level
, unsigned src_layer
,
2006 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2007 const struct blorp_surf
*dst_surf
,
2008 unsigned dst_level
, unsigned dst_layer
,
2009 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2010 float src_x0
, float src_y0
,
2011 float src_x1
, float src_y1
,
2012 float dst_x0
, float dst_y0
,
2013 float dst_x1
, float dst_y1
,
2014 GLenum filter
, bool mirror_x
, bool mirror_y
)
2016 struct blorp_params params
;
2017 blorp_params_init(¶ms
);
2019 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2020 src_layer
, src_format
, false);
2021 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2022 dst_layer
, dst_format
, true);
2024 params
.src
.view
.swizzle
= src_swizzle
;
2025 params
.dst
.view
.swizzle
= dst_swizzle
;
2027 struct brw_blorp_blit_prog_key wm_prog_key
= {
2028 .shader_type
= BLORP_SHADER_TYPE_BLIT
2031 /* Scaled blitting or not. */
2032 wm_prog_key
.blit_scaled
=
2033 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2034 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2036 /* Scaling factors used for bilinear filtering in multisample scaled
2039 if (params
.src
.surf
.samples
== 16)
2040 wm_prog_key
.x_scale
= 4.0f
;
2042 wm_prog_key
.x_scale
= 2.0f
;
2043 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2045 if (filter
== GL_LINEAR
&&
2046 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1)
2047 wm_prog_key
.bilinear_filter
= true;
2049 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
2050 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
2051 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
2052 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
2053 /* We are downsampling a non-integer color buffer, so blend.
2055 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
2057 * "If the source formats are integer types or stencil values, a
2058 * single sample's value is selected for each pixel."
2060 * This implies we should not blend in that case.
2062 wm_prog_key
.blend
= true;
2065 params
.wm_inputs
.rect_grid
.x1
=
2066 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2067 wm_prog_key
.x_scale
- 1.0f
;
2068 params
.wm_inputs
.rect_grid
.y1
=
2069 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2070 wm_prog_key
.y_scale
- 1.0f
;
2072 struct blt_coords coords
= {
2089 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2092 static enum isl_format
2093 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2095 /* The choice of UNORM and UINT formats is very intentional here. Most
2096 * of the time, we want to use a UINT format to avoid any rounding error
2097 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2098 * (It's the only format allowed in conjunction with W-tiling.) Also we
2099 * intentionally use the 4-channel formats whenever we can. This is so
2100 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2101 * even though one of them is 3/4 the size of the other. The choice of
2102 * UNORM vs. UINT is also very intentional because we don't have 8 or
2103 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2104 * Fortunately, the only time we should ever use two different formats in
2105 * the table below is for RGB -> RGBA blits and so we will never have any
2106 * UNORM/UINT mismatch.
2108 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2110 case 8: return ISL_FORMAT_R8_UINT
;
2111 case 16: return ISL_FORMAT_R8G8_UINT
;
2112 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2113 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2114 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2115 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2116 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2117 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2119 unreachable("Unknown format bpb");
2123 case 8: return ISL_FORMAT_R8_UINT
;
2124 case 16: return ISL_FORMAT_R8G8_UINT
;
2125 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2126 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2127 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2128 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2129 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2130 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2132 unreachable("Unknown format bpb");
2137 /** Returns a UINT format that is CCS-compatible with the given format
2139 * The PRM's say absolutely nothing about how render compression works. The
2140 * only thing they provide is a list of formats on which it is and is not
2141 * supported. Empirical testing indicates that the compression is only based
2142 * on the bit-layout of the format and the channel encoding doesn't matter.
2143 * So, while texture views don't work in general, you can create a view as
2144 * long as the bit-layout of the formats are the same.
2146 * Fortunately, for every render compression capable format, the UINT format
2147 * with the same bit layout also supports render compression. This means that
2148 * we only need to handle UINT formats for copy operations. In order to do
2149 * copies between formats with different bit layouts, we attach both with a
2150 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2151 * operation between the two bit layouts.
2153 static enum isl_format
2154 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2156 switch (fmtl
->format
) {
2157 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2158 case ISL_FORMAT_R32G32B32A32_SINT
:
2159 case ISL_FORMAT_R32G32B32A32_UINT
:
2160 case ISL_FORMAT_R32G32B32A32_UNORM
:
2161 case ISL_FORMAT_R32G32B32A32_SNORM
:
2162 return ISL_FORMAT_R32G32B32A32_UINT
;
2164 case ISL_FORMAT_R16G16B16A16_UNORM
:
2165 case ISL_FORMAT_R16G16B16A16_SNORM
:
2166 case ISL_FORMAT_R16G16B16A16_SINT
:
2167 case ISL_FORMAT_R16G16B16A16_UINT
:
2168 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2169 case ISL_FORMAT_R16G16B16X16_UNORM
:
2170 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2171 return ISL_FORMAT_R16G16B16A16_UINT
;
2173 case ISL_FORMAT_R32G32_FLOAT
:
2174 case ISL_FORMAT_R32G32_SINT
:
2175 case ISL_FORMAT_R32G32_UINT
:
2176 case ISL_FORMAT_R32G32_UNORM
:
2177 case ISL_FORMAT_R32G32_SNORM
:
2178 return ISL_FORMAT_R32G32_UINT
;
2180 case ISL_FORMAT_B8G8R8A8_UNORM
:
2181 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2182 case ISL_FORMAT_R8G8B8A8_UNORM
:
2183 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2184 case ISL_FORMAT_R8G8B8A8_SNORM
:
2185 case ISL_FORMAT_R8G8B8A8_SINT
:
2186 case ISL_FORMAT_R8G8B8A8_UINT
:
2187 case ISL_FORMAT_B8G8R8X8_UNORM
:
2188 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2189 case ISL_FORMAT_R8G8B8X8_UNORM
:
2190 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2191 return ISL_FORMAT_R8G8B8A8_UINT
;
2193 case ISL_FORMAT_R16G16_UNORM
:
2194 case ISL_FORMAT_R16G16_SNORM
:
2195 case ISL_FORMAT_R16G16_SINT
:
2196 case ISL_FORMAT_R16G16_UINT
:
2197 case ISL_FORMAT_R16G16_FLOAT
:
2198 return ISL_FORMAT_R16G16_UINT
;
2200 case ISL_FORMAT_R32_SINT
:
2201 case ISL_FORMAT_R32_UINT
:
2202 case ISL_FORMAT_R32_FLOAT
:
2203 case ISL_FORMAT_R32_UNORM
:
2204 case ISL_FORMAT_R32_SNORM
:
2205 return ISL_FORMAT_R32_UINT
;
2208 unreachable("Not a compressible format");
2212 /* Takes an isl_color_value and returns a color value that is the original
2213 * color value only bit-casted to a UINT format. This value, together with
2214 * the format from get_ccs_compatible_uint_format, will yield the same bit
2215 * value as the original color and format.
2217 static union isl_color_value
2218 bitcast_color_value_to_uint(union isl_color_value color
,
2219 const struct isl_format_layout
*fmtl
)
2221 /* All CCS formats have the same number of bits in each channel */
2222 const struct isl_channel_layout
*chan
= &fmtl
->channels
.r
;
2224 union isl_color_value bits
;
2225 switch (chan
->type
) {
2228 /* Hardware will ignore the high bits so there's no need to cast */
2233 for (unsigned i
= 0; i
< 4; i
++)
2234 bits
.u32
[i
] = _mesa_float_to_unorm(color
.f32
[i
], chan
->bits
);
2238 for (unsigned i
= 0; i
< 4; i
++)
2239 bits
.i32
[i
] = _mesa_float_to_snorm(color
.f32
[i
], chan
->bits
);
2243 switch (chan
->bits
) {
2245 for (unsigned i
= 0; i
< 4; i
++)
2246 bits
.u32
[i
] = _mesa_float_to_half(color
.f32
[i
]);
2254 unreachable("Invalid float format size");
2259 unreachable("Invalid channel type");
2262 switch (fmtl
->format
) {
2263 case ISL_FORMAT_B8G8R8A8_UNORM
:
2264 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2265 case ISL_FORMAT_B8G8R8X8_UNORM
:
2266 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
: {
2267 /* If it's a BGRA format, we need to swap blue and red */
2268 uint32_t tmp
= bits
.u32
[0];
2269 bits
.u32
[0] = bits
.u32
[2];
2275 break; /* Nothing to do */
2282 surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2283 struct brw_blorp_surface_info
*info
,
2284 uint32_t *x
, uint32_t *y
,
2285 uint32_t *width
, uint32_t *height
)
2287 const struct isl_format_layout
*fmtl
=
2288 isl_format_get_layout(info
->surf
.format
);
2290 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2292 /* This is a compressed surface. We need to convert it to a single
2293 * slice (because compressed layouts don't perfectly match uncompressed
2294 * ones with the same bpb) and divide x, y, width, and height by the
2297 surf_convert_to_single_slice(isl_dev
, info
);
2299 if (width
|| height
) {
2301 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2302 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2303 assert(*width
% fmtl
->bw
== 0 ||
2304 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2305 assert(*height
% fmtl
->bh
== 0 ||
2306 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2308 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2309 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2312 assert(*x
% fmtl
->bw
== 0);
2313 assert(*y
% fmtl
->bh
== 0);
2317 info
->surf
.logical_level0_px
.width
=
2318 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
2319 info
->surf
.logical_level0_px
.height
=
2320 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
2322 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
2323 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
2324 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2325 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2327 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2328 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2329 info
->tile_x_sa
/= fmtl
->bw
;
2330 info
->tile_y_sa
/= fmtl
->bh
;
2332 /* It's now an uncompressed surface so we need an uncompressed format */
2333 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2337 blorp_copy(struct blorp_batch
*batch
,
2338 const struct blorp_surf
*src_surf
,
2339 unsigned src_level
, unsigned src_layer
,
2340 const struct blorp_surf
*dst_surf
,
2341 unsigned dst_level
, unsigned dst_layer
,
2342 uint32_t src_x
, uint32_t src_y
,
2343 uint32_t dst_x
, uint32_t dst_y
,
2344 uint32_t src_width
, uint32_t src_height
)
2346 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2347 struct blorp_params params
;
2349 if (src_width
== 0 || src_height
== 0)
2352 blorp_params_init(¶ms
);
2353 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2354 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2355 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2356 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2358 struct brw_blorp_blit_prog_key wm_prog_key
= {
2359 .shader_type
= BLORP_SHADER_TYPE_BLIT
2362 const struct isl_format_layout
*src_fmtl
=
2363 isl_format_get_layout(params
.src
.surf
.format
);
2364 const struct isl_format_layout
*dst_fmtl
=
2365 isl_format_get_layout(params
.dst
.surf
.format
);
2367 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2368 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2369 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2370 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2371 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2372 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2374 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2375 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2376 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2377 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2378 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2379 params
.src
.view
.format
= params
.dst
.view
.format
;
2381 params
.src
.view
.format
=
2382 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2384 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2385 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2386 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2387 params
.dst
.view
.format
= params
.src
.view
.format
;
2389 params
.dst
.view
.format
=
2390 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2393 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2394 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2397 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2398 params
.src
.clear_color
=
2399 bitcast_color_value_to_uint(params
.src
.clear_color
, src_fmtl
);
2402 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2403 params
.dst
.clear_color
=
2404 bitcast_color_value_to_uint(params
.dst
.clear_color
, dst_fmtl
);
2407 wm_prog_key
.src_bpc
=
2408 isl_format_get_layout(params
.src
.view
.format
)->channels
.r
.bits
;
2409 wm_prog_key
.dst_bpc
=
2410 isl_format_get_layout(params
.dst
.view
.format
)->channels
.r
.bits
;
2412 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2413 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2414 &src_x
, &src_y
, &src_width
, &src_height
);
2415 wm_prog_key
.need_src_offset
= true;
2418 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2419 surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2420 &dst_x
, &dst_y
, NULL
, NULL
);
2421 wm_prog_key
.need_dst_offset
= true;
2424 /* Once both surfaces are stompped to uncompressed as needed, the
2425 * destination size is the same as the source size.
2427 uint32_t dst_width
= src_width
;
2428 uint32_t dst_height
= src_height
;
2430 struct blt_coords coords
= {
2433 .src1
= src_x
+ src_width
,
2435 .dst1
= dst_x
+ dst_width
,
2440 .src1
= src_y
+ src_height
,
2442 .dst1
= dst_y
+ dst_height
,
2447 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);