2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "blorp_nir_builder.h"
25 #include "compiler/nir/nir_format_convert.h"
27 #include "blorp_priv.h"
29 #include "util/format_rgb9e5.h"
30 /* header-only include needed for _mesa_unorm_to_float and friends. */
31 #include "mesa/main/format_utils.h"
32 #include "util/u_math.h"
34 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 static const bool split_blorp_blit_debug
= false;
39 * Enum to specify the order of arguments in a sampler message
41 enum sampler_message_arg
43 SAMPLER_MESSAGE_ARG_U_FLOAT
,
44 SAMPLER_MESSAGE_ARG_V_FLOAT
,
45 SAMPLER_MESSAGE_ARG_U_INT
,
46 SAMPLER_MESSAGE_ARG_V_INT
,
47 SAMPLER_MESSAGE_ARG_R_INT
,
48 SAMPLER_MESSAGE_ARG_SI_INT
,
49 SAMPLER_MESSAGE_ARG_MCS_INT
,
50 SAMPLER_MESSAGE_ARG_ZERO_INT
,
53 struct brw_blorp_blit_vars
{
54 /* Input values from brw_blorp_wm_inputs */
55 nir_variable
*v_discard_rect
;
56 nir_variable
*v_rect_grid
;
57 nir_variable
*v_coord_transform
;
58 nir_variable
*v_src_z
;
59 nir_variable
*v_src_offset
;
60 nir_variable
*v_dst_offset
;
61 nir_variable
*v_src_inv_size
;
64 nir_variable
*color_out
;
68 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
69 const struct brw_blorp_blit_prog_key
*key
)
71 #define LOAD_INPUT(name, type)\
72 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
74 LOAD_INPUT(discard_rect
, glsl_vec4_type())
75 LOAD_INPUT(rect_grid
, glsl_vec4_type())
76 LOAD_INPUT(coord_transform
, glsl_vec4_type())
77 LOAD_INPUT(src_z
, glsl_uint_type())
78 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
79 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
80 LOAD_INPUT(src_inv_size
, glsl_vector_type(GLSL_TYPE_FLOAT
, 2))
84 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
85 glsl_vec4_type(), "gl_FragColor");
86 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
90 blorp_blit_get_frag_coords(nir_builder
*b
,
91 const struct brw_blorp_blit_prog_key
*key
,
92 struct brw_blorp_blit_vars
*v
)
94 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_frag_coord(b
));
96 /* Account for destination surface intratile offset
98 * Transformation parameters giving translation from destination to source
99 * coordinates don't take into account possible intra-tile destination
100 * offset. Therefore it has to be first subtracted from the incoming
101 * coordinates. Vertices are set up based on coordinates containing the
104 if (key
->need_dst_offset
)
105 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
107 if (key
->persample_msaa_dispatch
) {
108 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
109 nir_load_sample_id(b
));
111 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
116 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
120 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
121 struct brw_blorp_blit_vars
*v
)
123 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
125 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
126 nir_channel(b
, coord_transform
, 3));
127 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
128 nir_channel(b
, coord_transform
, 2));
130 return nir_fadd(b
, nir_fmul(b
, src_pos
, mul
), offset
);
134 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
135 struct brw_blorp_blit_vars
*v
)
137 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
138 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
139 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
140 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
141 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
142 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
144 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
145 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
146 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
147 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
149 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
151 nir_intrinsic_instr
*discard
=
152 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
153 discard
->src
[0] = nir_src_for_ssa(oob
);
154 nir_builder_instr_insert(b
, &discard
->instr
);
157 static nir_tex_instr
*
158 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
159 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
160 nir_alu_type dst_type
)
162 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
166 tex
->dest_type
= dst_type
;
167 tex
->is_array
= false;
168 tex
->is_shadow
= false;
170 /* Blorp only has one texture and it's bound at unit 0 */
171 tex
->texture_index
= 0;
172 tex
->sampler_index
= 0;
174 /* To properly handle 3-D and 2-D array textures, we pull the Z component
175 * from an input. TODO: This is a bit magic; we should probably make this
176 * more explicit in the future.
178 assert(pos
->num_components
>= 2);
179 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
180 nir_load_var(b
, v
->v_src_z
));
182 tex
->src
[0].src_type
= nir_tex_src_coord
;
183 tex
->src
[0].src
= nir_src_for_ssa(pos
);
184 tex
->coord_components
= 3;
186 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
192 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
193 const struct brw_blorp_blit_prog_key
*key
, nir_ssa_def
*pos
)
195 if (key
->need_src_offset
)
196 pos
= nir_fadd(b
, pos
, nir_i2f32(b
, nir_load_var(b
, v
->v_src_offset
)));
198 /* If the sampler requires normalized coordinates, we need to compensate. */
199 if (key
->src_coords_normalized
)
200 pos
= nir_fmul(b
, pos
, nir_load_var(b
, v
->v_src_inv_size
));
203 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2,
204 key
->texture_data_type
);
206 assert(pos
->num_components
== 2);
207 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
208 tex
->src
[1].src_type
= nir_tex_src_lod
;
209 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
211 nir_builder_instr_insert(b
, &tex
->instr
);
213 return &tex
->dest
.ssa
;
217 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
218 nir_ssa_def
*pos
, nir_alu_type dst_type
)
221 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
223 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
224 tex
->src
[1].src_type
= nir_tex_src_lod
;
225 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
227 nir_builder_instr_insert(b
, &tex
->instr
);
229 return &tex
->dest
.ssa
;
233 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
234 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
237 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
238 mcs
!= NULL
? 3 : 2, dst_type
);
240 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
242 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
243 if (pos
->num_components
== 2) {
244 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
246 assert(pos
->num_components
== 3);
247 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
251 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
252 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
255 nir_builder_instr_insert(b
, &tex
->instr
);
257 return &tex
->dest
.ssa
;
261 blorp_blit_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
265 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
266 pos
, 1, nir_type_int
);
268 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
270 nir_builder_instr_insert(b
, &tex
->instr
);
272 return &tex
->dest
.ssa
;
276 * Emit code to compensate for the difference between Y and W tiling.
278 * This code modifies the X and Y coordinates according to the formula:
280 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
282 * (See brw_blorp_build_nir_shader).
284 static inline nir_ssa_def
*
285 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
287 assert(pos
->num_components
== 2);
288 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
289 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
291 /* Given X and Y coordinates that describe an address using Y tiling,
292 * translate to the X and Y coordinates that describe the same address
295 * If we break down the low order bits of X and Y, using a
296 * single letter to represent each low-order bit:
298 * X = A << 7 | 0bBCDEFGH
299 * Y = J << 5 | 0bKLMNP (1)
301 * Then we can apply the Y tiling formula to see the memory offset being
304 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
306 * If we apply the W detiling formula to this memory location, that the
307 * corresponding X' and Y' coordinates are:
309 * X' = A << 6 | 0bBCDPFH (3)
310 * Y' = J << 6 | 0bKLMNEG
312 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
313 * we need to make the following computation:
315 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
316 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
318 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
319 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
320 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
321 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
323 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
324 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
325 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
326 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
328 return nir_vec2(b
, x_W
, y_W
);
332 * Emit code to compensate for the difference between Y and W tiling.
334 * This code modifies the X and Y coordinates according to the formula:
336 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
338 * (See brw_blorp_build_nir_shader).
340 static inline nir_ssa_def
*
341 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
343 assert(pos
->num_components
== 2);
344 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
345 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
347 /* Applying the same logic as above, but in reverse, we obtain the
350 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
351 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
353 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
354 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
355 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
356 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
357 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
359 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
360 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
361 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
363 return nir_vec2(b
, x_Y
, y_Y
);
367 * Emit code to compensate for the difference between MSAA and non-MSAA
370 * This code modifies the X and Y coordinates according to the formula:
372 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
374 * (See brw_blorp_blit_program).
376 static inline nir_ssa_def
*
377 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
378 unsigned num_samples
, enum isl_msaa_layout layout
)
380 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
383 case ISL_MSAA_LAYOUT_NONE
:
384 assert(pos
->num_components
== 2);
386 case ISL_MSAA_LAYOUT_ARRAY
:
387 /* No translation needed */
389 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
390 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
391 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
392 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
393 nir_channel(b
, pos
, 2);
395 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
396 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
397 switch (num_samples
) {
400 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
401 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
404 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
405 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
406 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
408 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
409 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
410 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
411 if (num_samples
== 2) {
414 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
415 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
416 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
421 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
422 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
424 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
426 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
427 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
428 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
429 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
430 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
431 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
432 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
436 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
437 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
439 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
442 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
443 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
444 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
445 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
446 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
447 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
448 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
449 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
453 unreachable("Invalid number of samples for IMS layout");
456 return nir_vec2(b
, x_out
, y_out
);
460 unreachable("Invalid MSAA layout");
465 * Emit code to compensate for the difference between MSAA and non-MSAA
468 * This code modifies the X and Y coordinates according to the formula:
470 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
472 * (See brw_blorp_blit_program).
474 static inline nir_ssa_def
*
475 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
476 unsigned num_samples
, enum isl_msaa_layout layout
)
478 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
481 case ISL_MSAA_LAYOUT_NONE
:
482 /* No translation necessary, and S should already be zero. */
483 assert(pos
->num_components
== 2);
485 case ISL_MSAA_LAYOUT_ARRAY
:
486 /* No translation necessary. */
488 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
489 assert(pos
->num_components
== 2);
491 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
492 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
494 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
495 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
496 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
497 switch (num_samples
) {
500 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
501 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
502 * S = (X & 0b10) >> 1
504 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
505 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
506 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
507 * S = (Y & 0b10) | (X & 0b10) >> 1
509 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
510 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
511 if (num_samples
== 2) {
513 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
515 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
516 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
517 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
518 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
523 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
524 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
525 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
526 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
528 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
529 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
530 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
531 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
532 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
533 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
534 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
538 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
539 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
540 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
541 * S = (Y & 0b100) << 1 | (X & 0b100) |
542 * (Y & 0b10) | (X & 0b10) >> 1
544 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
545 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
546 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
547 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
548 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
549 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
550 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
551 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
555 unreachable("Invalid number of samples for IMS layout");
558 return nir_vec3(b
, x_out
, y_out
, s_out
);
562 unreachable("Invalid MSAA layout");
567 * Count the number of trailing 1 bits in the given value. For example:
569 * count_trailing_one_bits(0) == 0
570 * count_trailing_one_bits(7) == 3
571 * count_trailing_one_bits(11) == 2
573 static inline int count_trailing_one_bits(unsigned value
)
575 #ifdef HAVE___BUILTIN_CTZ
576 return __builtin_ctz(~value
);
578 return util_bitcount(value
& ~(value
+ 1));
583 blorp_nir_combine_samples(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
584 nir_ssa_def
*pos
, unsigned tex_samples
,
585 enum isl_aux_usage tex_aux_usage
,
586 nir_alu_type dst_type
,
587 enum blorp_filter filter
)
589 /* If non-null, this is the outer-most if statement */
590 nir_if
*outer_if
= NULL
;
592 nir_variable
*color
=
593 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
595 nir_ssa_def
*mcs
= NULL
;
596 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
597 mcs
= blorp_blit_txf_ms_mcs(b
, v
, pos
);
601 case BLORP_FILTER_AVERAGE
:
602 assert(dst_type
== nir_type_float
);
603 combine_op
= nir_op_fadd
;
606 case BLORP_FILTER_MIN_SAMPLE
:
608 case nir_type_int
: combine_op
= nir_op_imin
; break;
609 case nir_type_uint
: combine_op
= nir_op_umin
; break;
610 case nir_type_float
: combine_op
= nir_op_fmin
; break;
611 default: unreachable("Invalid dst_type");
615 case BLORP_FILTER_MAX_SAMPLE
:
617 case nir_type_int
: combine_op
= nir_op_imax
; break;
618 case nir_type_uint
: combine_op
= nir_op_umax
; break;
619 case nir_type_float
: combine_op
= nir_op_fmax
; break;
620 default: unreachable("Invalid dst_type");
625 unreachable("Invalid filter");
628 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
630 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
632 * This ensures that when all samples have the same value, no numerical
633 * precision is lost, since each addition operation always adds two equal
634 * values, and summing two equal floating point values does not lose
637 * We perform this computation by treating the texture_data array as a
638 * stack and performing the following operations:
640 * - push sample 0 onto stack
641 * - push sample 1 onto stack
642 * - add top two stack entries
643 * - push sample 2 onto stack
644 * - push sample 3 onto stack
645 * - add top two stack entries
646 * - add top two stack entries
647 * - divide top stack entry by 4
649 * Note that after pushing sample i onto the stack, the number of add
650 * operations we do is equal to the number of trailing 1 bits in i. This
651 * works provided the total number of samples is a power of two, which it
652 * always is for i965.
654 * For integer formats, we replace the add operations with average
655 * operations and skip the final division.
657 nir_ssa_def
*texture_data
[5];
658 unsigned stack_depth
= 0;
659 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
660 assert(stack_depth
== util_bitcount(i
)); /* Loop invariant */
662 /* Push sample i onto the stack */
663 assert(stack_depth
< ARRAY_SIZE(texture_data
));
665 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
666 nir_channel(b
, pos
, 1),
668 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
670 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
671 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
672 * suggests an optimization:
674 * "A simple optimization with probable large return in
675 * performance is to compare the MCS value to zero (indicating
676 * all samples are on sample slice 0), and sample only from
677 * sample slice 0 using ld2dss if MCS is zero."
679 * Note that in the case where the MCS value is zero, sampling from
680 * sample slice 0 using ld2dss and sampling from sample 0 using
681 * ld2dms are equivalent (since all samples are on sample slice 0).
682 * Since we have already sampled from sample 0, all we need to do is
683 * skip the remaining fetches and averaging if MCS is zero.
685 * It's also trivial to detect when the MCS has the magic clear color
686 * value. In this case, the txf we did on sample 0 will return the
687 * clear color and we can skip the remaining fetches just like we do
690 nir_ssa_def
*mcs_zero
=
691 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
692 if (tex_samples
== 16) {
693 mcs_zero
= nir_iand(b
, mcs_zero
,
694 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
696 nir_ssa_def
*mcs_clear
=
697 blorp_nir_mcs_is_clear_color(b
, mcs
, tex_samples
);
699 nir_if
*if_stmt
= nir_if_create(b
->shader
);
700 if_stmt
->condition
= nir_src_for_ssa(nir_ior(b
, mcs_zero
, mcs_clear
));
701 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
703 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
704 nir_store_var(b
, color
, texture_data
[0], 0xf);
706 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
710 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
711 assert(stack_depth
>= 2);
714 texture_data
[stack_depth
- 1] =
715 nir_build_alu(b
, combine_op
,
716 texture_data
[stack_depth
- 1],
717 texture_data
[stack_depth
],
722 /* We should have just 1 sample on the stack now. */
723 assert(stack_depth
== 1);
725 if (filter
== BLORP_FILTER_AVERAGE
) {
726 assert(dst_type
== nir_type_float
);
727 texture_data
[0] = nir_fmul(b
, texture_data
[0],
728 nir_imm_float(b
, 1.0 / tex_samples
));
731 nir_store_var(b
, color
, texture_data
[0], 0xf);
734 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
736 return nir_load_var(b
, color
);
740 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
741 unsigned tex_samples
,
742 const struct brw_blorp_blit_prog_key
*key
,
743 struct brw_blorp_blit_vars
*v
)
745 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
746 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
747 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
749 /* Translate coordinates to lay out the samples in a rectangular grid
750 * roughly corresponding to sample locations.
752 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
753 /* Adjust coordinates so that integers represent pixel centers rather
756 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
757 /* Clamp the X, Y texture coordinates to properly handle the sampling of
758 * texels on texture edges.
760 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
761 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
762 nir_channel(b
, rect_grid
, 1)));
764 /* Store the fractional parts to be used as bilinear interpolation
767 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
768 /* Round the float coordinates down to nearest integer */
769 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
771 nir_ssa_def
*tex_data
[4];
772 for (unsigned i
= 0; i
< 4; ++i
) {
773 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
774 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
775 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
777 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
778 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
780 /* The MCS value we fetch has to match up with the pixel that we're
781 * sampling from. Since we sample from different pixels in each
782 * iteration of this "for" loop, the call to mcs_fetch() should be
783 * here inside the loop after computing the pixel coordinates.
785 nir_ssa_def
*mcs
= NULL
;
786 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
787 mcs
= blorp_blit_txf_ms_mcs(b
, v
, sample_coords_int
);
789 /* Compute sample index and map the sample index to a sample number.
790 * Sample index layout shows the numbering of slots in a rectangular
791 * grid of samples with in a pixel. Sample number layout shows the
792 * rectangular grid of samples roughly corresponding to the real sample
793 * locations with in a pixel.
795 * In the case of 2x MSAA, the layout of sample indices is reversed from
796 * the layout of sample numbers:
798 * sample index layout : --------- sample number layout : ---------
799 * | 0 | 1 | | 1 | 0 |
800 * --------- ---------
802 * In case of 4x MSAA, layout of sample indices matches the layout of
810 * In case of 8x MSAA the two layouts don't match.
811 * sample index layout : --------- sample number layout : ---------
812 * | 0 | 1 | | 3 | 7 |
813 * --------- ---------
814 * | 2 | 3 | | 5 | 0 |
815 * --------- ---------
816 * | 4 | 5 | | 1 | 2 |
817 * --------- ---------
818 * | 6 | 7 | | 4 | 6 |
819 * --------- ---------
821 * Fortunately, this can be done fairly easily as:
822 * S' = (0x17306425 >> (S * 4)) & 0xf
824 * In the case of 16x MSAA the two layouts don't match.
825 * Sample index layout: Sample number layout:
826 * --------------------- ---------------------
827 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
828 * --------------------- ---------------------
829 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
830 * --------------------- ---------------------
831 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
832 * --------------------- ---------------------
833 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
834 * --------------------- ---------------------
836 * This is equivalent to
837 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
839 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
840 nir_ssa_def
*sample
=
841 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
842 key
->x_scale
* key
->y_scale
));
843 sample
= nir_f2i32(b
, sample
);
845 if (tex_samples
== 2) {
846 sample
= nir_isub(b
, nir_imm_int(b
, 1), sample
);
847 } else if (tex_samples
== 8) {
848 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
849 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
850 nir_imm_int(b
, 0xf));
851 } else if (tex_samples
== 16) {
852 nir_ssa_def
*sample_low
=
853 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
854 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
855 nir_imm_int(b
, 0xf));
856 nir_ssa_def
*sample_high
=
857 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
858 nir_ishl(b
, nir_iadd(b
, sample
,
861 nir_imm_int(b
, 0xf));
863 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
864 sample_low
, sample_high
);
866 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
867 nir_channel(b
, sample_coords_int
, 1),
869 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
872 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
873 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
874 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
875 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
879 /** Perform a color bit-cast operation
881 * For copy operations involving CCS, we may need to use different formats for
882 * the source and destination surfaces. The two formats must both be UINT
883 * formats and must have the same size but may have different bit layouts.
884 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
885 * to R16G16_UINT. This function generates code to shuffle bits around to get
886 * us from one to the other.
889 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
890 const struct brw_blorp_blit_prog_key
*key
)
892 assert(key
->texture_data_type
== nir_type_uint
);
894 if (key
->src_format
== key
->dst_format
)
897 const struct isl_format_layout
*src_fmtl
=
898 isl_format_get_layout(key
->src_format
);
899 const struct isl_format_layout
*dst_fmtl
=
900 isl_format_get_layout(key
->dst_format
);
902 /* They must be uint formats with the same bit size */
903 assert(src_fmtl
->bpb
== dst_fmtl
->bpb
);
904 assert(src_fmtl
->channels
.r
.type
== ISL_UINT
);
905 assert(dst_fmtl
->channels
.r
.type
== ISL_UINT
);
907 /* They must be in regular color formats (no luminance or alpha) */
908 assert(src_fmtl
->channels
.r
.bits
> 0);
909 assert(dst_fmtl
->channels
.r
.bits
> 0);
911 /* They must be in RGBA order (possibly with channels missing) */
912 assert(src_fmtl
->channels
.r
.start_bit
== 0);
913 assert(dst_fmtl
->channels
.r
.start_bit
== 0);
915 if (src_fmtl
->bpb
<= 32) {
916 const unsigned src_channels
=
917 isl_format_get_num_channels(key
->src_format
);
918 const unsigned src_bits
[4] = {
919 src_fmtl
->channels
.r
.bits
,
920 src_fmtl
->channels
.g
.bits
,
921 src_fmtl
->channels
.b
.bits
,
922 src_fmtl
->channels
.a
.bits
,
924 const unsigned dst_channels
=
925 isl_format_get_num_channels(key
->dst_format
);
926 const unsigned dst_bits
[4] = {
927 dst_fmtl
->channels
.r
.bits
,
928 dst_fmtl
->channels
.g
.bits
,
929 dst_fmtl
->channels
.b
.bits
,
930 dst_fmtl
->channels
.a
.bits
,
932 nir_ssa_def
*packed
=
933 nir_format_pack_uint_unmasked(b
, color
, src_bits
, src_channels
);
934 color
= nir_format_unpack_uint(b
, packed
, dst_bits
, dst_channels
);
936 const unsigned src_bpc
= src_fmtl
->channels
.r
.bits
;
937 const unsigned dst_bpc
= dst_fmtl
->channels
.r
.bits
;
939 assert(src_fmtl
->channels
.g
.bits
== 0 ||
940 src_fmtl
->channels
.g
.bits
== src_fmtl
->channels
.r
.bits
);
941 assert(src_fmtl
->channels
.b
.bits
== 0 ||
942 src_fmtl
->channels
.b
.bits
== src_fmtl
->channels
.r
.bits
);
943 assert(src_fmtl
->channels
.a
.bits
== 0 ||
944 src_fmtl
->channels
.a
.bits
== src_fmtl
->channels
.r
.bits
);
945 assert(dst_fmtl
->channels
.g
.bits
== 0 ||
946 dst_fmtl
->channels
.g
.bits
== dst_fmtl
->channels
.r
.bits
);
947 assert(dst_fmtl
->channels
.b
.bits
== 0 ||
948 dst_fmtl
->channels
.b
.bits
== dst_fmtl
->channels
.r
.bits
);
949 assert(dst_fmtl
->channels
.a
.bits
== 0 ||
950 dst_fmtl
->channels
.a
.bits
== dst_fmtl
->channels
.r
.bits
);
952 /* Restrict to only the channels we actually have */
953 const unsigned src_channels
=
954 isl_format_get_num_channels(key
->src_format
);
955 color
= nir_channels(b
, color
, (1 << src_channels
) - 1);
957 color
= nir_format_bitcast_uvec_unmasked(b
, color
, src_bpc
, dst_bpc
);
960 /* Blorp likes to assume that colors are vec4s */
961 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
962 nir_ssa_def
*chans
[4] = { u
, u
, u
, u
};
963 for (unsigned i
= 0; i
< color
->num_components
; i
++)
964 chans
[i
] = nir_channel(b
, color
, i
);
965 return nir_vec4(b
, chans
[0], chans
[1], chans
[2], chans
[3]);
969 select_color_channel(struct nir_builder
*b
, nir_ssa_def
*color
,
970 nir_alu_type data_type
,
971 enum isl_channel_select chan
)
973 if (chan
== ISL_CHANNEL_SELECT_ZERO
) {
974 return nir_imm_int(b
, 0);
975 } else if (chan
== ISL_CHANNEL_SELECT_ONE
) {
979 return nir_imm_int(b
, 1);
981 return nir_imm_float(b
, 1);
983 unreachable("Invalid data type");
986 assert((unsigned)(chan
- ISL_CHANNEL_SELECT_RED
) < 4);
987 return nir_channel(b
, color
, chan
- ISL_CHANNEL_SELECT_RED
);
992 swizzle_color(struct nir_builder
*b
, nir_ssa_def
*color
,
993 struct isl_swizzle swizzle
, nir_alu_type data_type
)
996 select_color_channel(b
, color
, data_type
, swizzle
.r
),
997 select_color_channel(b
, color
, data_type
, swizzle
.g
),
998 select_color_channel(b
, color
, data_type
, swizzle
.b
),
999 select_color_channel(b
, color
, data_type
, swizzle
.a
));
1002 static nir_ssa_def
*
1003 convert_color(struct nir_builder
*b
, nir_ssa_def
*color
,
1004 const struct brw_blorp_blit_prog_key
*key
)
1006 /* All of our color conversions end up generating a single-channel color
1007 * value that we need to write out.
1011 if (key
->dst_format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
1012 /* The destination image is bound as R32_UINT but the data needs to be
1013 * in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and the
1014 * top 8 need to be zero. We can accomplish this by simply multiplying
1015 * by a factor to scale things down.
1017 unsigned factor
= (1 << 24) - 1;
1018 value
= nir_fsat(b
, nir_channel(b
, color
, 0));
1019 value
= nir_f2i32(b
, nir_fmul(b
, value
, nir_imm_float(b
, factor
)));
1020 } else if (key
->dst_format
== ISL_FORMAT_L8_UNORM_SRGB
) {
1021 value
= nir_format_linear_to_srgb(b
, nir_channel(b
, color
, 0));
1022 } else if (key
->dst_format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
) {
1023 value
= nir_format_linear_to_srgb(b
, color
);
1024 } else if (key
->dst_format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
1025 value
= nir_format_pack_r9g9b9e5(b
, color
);
1027 unreachable("Unsupported format conversion");
1030 nir_ssa_def
*out_comps
[4];
1031 for (unsigned i
= 0; i
< 4; i
++) {
1032 if (i
< value
->num_components
)
1033 out_comps
[i
] = nir_channel(b
, value
, i
);
1035 out_comps
[i
] = nir_ssa_undef(b
, 1, 32);
1037 return nir_vec(b
, out_comps
, 4);
1041 * Generator for WM programs used in BLORP blits.
1043 * The bulk of the work done by the WM program is to wrap and unwrap the
1044 * coordinate transformations used by the hardware to store surfaces in
1045 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
1046 * sample index for a multisampled surface) to a memory offset by the
1047 * following formulas:
1049 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
1050 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
1052 * For a single-sampled surface, or for a multisampled surface using
1053 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
1056 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1057 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1058 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1059 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1061 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1062 * embeds the sample number into bit 1 of the X and Y coordinates:
1064 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1065 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1066 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
1067 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1068 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1069 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1070 * S = (Y & 0b10) | (X & 0b10) >> 1
1072 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1073 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
1076 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1077 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
1078 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1079 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1080 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1081 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1082 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1084 * For X tiling, tile() combines together the low-order bits of the X and Y
1085 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
1086 * bytes wide and 8 rows high:
1088 * tile(x_tiled, X, Y, S) = A
1089 * where A = tile_num << 12 | offset
1090 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
1091 * offset = (Y' & 0b111) << 9
1092 * | (X & 0b111111111)
1094 * Y' = Y + S * qpitch
1095 * detile(x_tiled, A) = (X, Y, S)
1096 * where X = X' / cpp
1099 * Y' = (tile_num / tile_pitch) << 3
1100 * | (A & 0b111000000000) >> 9
1101 * X' = (tile_num % tile_pitch) << 9
1102 * | (A & 0b111111111)
1104 * (In all tiling formulas, cpp is the number of bytes occupied by a single
1105 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
1106 * to fill the width of the surface, and qpitch is the spacing (in rows)
1107 * between array slices).
1109 * For Y tiling, tile() combines together the low-order bits of the X and Y
1110 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
1111 * bytes wide and 32 rows high:
1113 * tile(y_tiled, X, Y, S) = A
1114 * where A = tile_num << 12 | offset
1115 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
1116 * offset = (X' & 0b1110000) << 5
1117 * | (Y' & 0b11111) << 4
1120 * Y' = Y + S * qpitch
1121 * detile(y_tiled, A) = (X, Y, S)
1122 * where X = X' / cpp
1125 * Y' = (tile_num / tile_pitch) << 5
1126 * | (A & 0b111110000) >> 4
1127 * X' = (tile_num % tile_pitch) << 7
1128 * | (A & 0b111000000000) >> 5
1131 * For W tiling, tile() combines together the low-order bits of the X and Y
1132 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1133 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1134 * buffers, which always have cpp = 1 and S=0):
1136 * tile(w_tiled, X, Y, S) = A
1137 * where A = tile_num << 12 | offset
1138 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1139 * offset = (X' & 0b111000) << 6
1140 * | (Y' & 0b111100) << 3
1141 * | (X' & 0b100) << 2
1142 * | (Y' & 0b10) << 2
1143 * | (X' & 0b10) << 1
1147 * Y' = Y + S * qpitch
1148 * detile(w_tiled, A) = (X, Y, S)
1149 * where X = X' / cpp = X'
1150 * Y = Y' % qpitch = Y'
1151 * S = Y / qpitch = 0
1152 * Y' = (tile_num / tile_pitch) << 6
1153 * | (A & 0b111100000) >> 3
1154 * | (A & 0b1000) >> 2
1156 * X' = (tile_num % tile_pitch) << 6
1157 * | (A & 0b111000000000) >> 6
1158 * | (A & 0b10000) >> 2
1159 * | (A & 0b100) >> 1
1162 * Finally, for a non-tiled surface, tile() simply combines together the X and
1163 * Y coordinates in the natural way:
1165 * tile(untiled, X, Y, S) = A
1166 * where A = Y * pitch + X'
1168 * Y' = Y + S * qpitch
1169 * detile(untiled, A) = (X, Y, S)
1170 * where X = X' / cpp
1176 * (In these formulas, pitch is the number of bytes occupied by a single row
1180 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1181 const struct brw_blorp_blit_prog_key
*key
)
1183 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1184 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1187 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1188 /* If the destination image is W tiled and multisampled, then the thread
1189 * must be dispatched once per sample, not once per pixel. This is
1190 * necessary because after conversion between W and Y tiling, there's no
1191 * guarantee that all samples corresponding to a single pixel will still
1194 assert(key
->persample_msaa_dispatch
);
1197 if (key
->persample_msaa_dispatch
) {
1198 /* It only makes sense to do persample dispatch if the render target is
1199 * configured as multisampled.
1201 assert(key
->rt_samples
> 0);
1204 /* Make sure layout is consistent with sample count */
1205 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1206 (key
->tex_samples
<= 1));
1207 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1208 (key
->rt_samples
<= 1));
1209 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1210 (key
->src_samples
<= 1));
1211 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1212 (key
->dst_samples
<= 1));
1215 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1217 struct brw_blorp_blit_vars v
;
1218 brw_blorp_blit_vars_init(&b
, &v
, key
);
1220 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1222 /* Render target and texture hardware don't support W tiling until Gen8. */
1223 const bool rt_tiled_w
= false;
1224 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1226 /* The address that data will be written to is determined by the
1227 * coordinates supplied to the WM thread and the tiling and sample count of
1228 * the render target, according to the formula:
1230 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1232 * If the actual tiling and sample count of the destination surface are not
1233 * the same as the configuration of the render target, then these
1234 * coordinates are wrong and we have to adjust them to compensate for the
1237 if (rt_tiled_w
!= key
->dst_tiled_w
||
1238 key
->rt_samples
!= key
->dst_samples
||
1239 key
->rt_layout
!= key
->dst_layout
) {
1240 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1242 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1243 if (rt_tiled_w
!= key
->dst_tiled_w
)
1244 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1245 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1246 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1250 nir_ssa_def
*comp
= NULL
;
1252 /* The destination image is bound as a red texture three times as wide
1253 * as the actual image. Our shader is effectively running one color
1254 * component at a time. We need to save off the component and adjust
1255 * the destination position.
1257 assert(dst_pos
->num_components
== 2);
1258 nir_ssa_def
*dst_x
= nir_channel(&b
, dst_pos
, 0);
1259 comp
= nir_umod(&b
, dst_x
, nir_imm_int(&b
, 3));
1260 dst_pos
= nir_vec2(&b
, nir_idiv(&b
, dst_x
, nir_imm_int(&b
, 3)),
1261 nir_channel(&b
, dst_pos
, 1));
1264 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1266 * That is: X, Y and S now contain the true coordinates and sample index of
1267 * the data that the WM thread should output.
1269 * If we need to kill pixels that are outside the destination rectangle,
1270 * now is the time to do it.
1273 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1275 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1276 if (dst_pos
->num_components
== 3) {
1277 /* The sample coordinate is an integer that we want left alone but
1278 * blorp_blit_apply_transform() blindly applies the transform to all
1279 * three coordinates. Grab the original sample index.
1281 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1282 nir_channel(&b
, src_pos
, 1),
1283 nir_channel(&b
, dst_pos
, 2));
1286 /* If the source image is not multisampled, then we want to fetch sample
1287 * number 0, because that's the only sample there is.
1289 if (key
->src_samples
== 1)
1290 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1292 /* X, Y, and S are now the coordinates of the pixel in the source image
1293 * that we want to texture from. Exception: if we are blending, then S is
1294 * irrelevant, because we are going to fetch all samples.
1296 switch (key
->filter
) {
1297 case BLORP_FILTER_NONE
:
1298 case BLORP_FILTER_NEAREST
:
1299 case BLORP_FILTER_SAMPLE_0
:
1300 /* We're going to use texelFetch, so we need integers */
1301 if (src_pos
->num_components
== 2) {
1302 src_pos
= nir_f2i32(&b
, src_pos
);
1304 assert(src_pos
->num_components
== 3);
1305 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1306 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1307 nir_channel(&b
, src_pos
, 2));
1310 /* We aren't blending, which means we just want to fetch a single
1311 * sample from the source surface. The address that we want to fetch
1312 * from is related to the X, Y and S values according to the formula:
1314 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1316 * If the actual tiling and sample count of the source surface are
1317 * not the same as the configuration of the texture, then we need to
1318 * adjust the coordinates to compensate for the difference.
1320 if (tex_tiled_w
!= key
->src_tiled_w
||
1321 key
->tex_samples
!= key
->src_samples
||
1322 key
->tex_layout
!= key
->src_layout
) {
1323 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1325 /* Now (X, Y, S) = detile(src_tiling, offset) */
1326 if (tex_tiled_w
!= key
->src_tiled_w
)
1327 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1328 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1329 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1333 if (key
->need_src_offset
)
1334 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1336 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1338 * In other words: X, Y, and S now contain values which, when passed to
1339 * the texturing unit, will cause data to be read from the correct
1340 * memory location. So we can fetch the texel now.
1342 if (key
->src_samples
== 1) {
1343 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1345 nir_ssa_def
*mcs
= NULL
;
1346 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1347 mcs
= blorp_blit_txf_ms_mcs(&b
, &v
, src_pos
);
1349 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1353 case BLORP_FILTER_BILINEAR
:
1354 assert(!key
->src_tiled_w
);
1355 assert(key
->tex_samples
== key
->src_samples
);
1356 assert(key
->tex_layout
== key
->src_layout
);
1358 if (key
->src_samples
== 1) {
1359 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1361 assert(!key
->use_kill
);
1362 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
,
1367 case BLORP_FILTER_AVERAGE
:
1368 case BLORP_FILTER_MIN_SAMPLE
:
1369 case BLORP_FILTER_MAX_SAMPLE
:
1370 assert(!key
->src_tiled_w
);
1371 assert(key
->tex_samples
== key
->src_samples
);
1372 assert(key
->tex_layout
== key
->src_layout
);
1374 /* Resolves (effecively) use texelFetch, so we need integers and we
1375 * don't care about the sample index if we got one.
1377 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1379 if (devinfo
->gen
== 6) {
1380 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1381 * blending we need with a single linear-interpolated texture lookup
1382 * at the center of the sample. The texture coordinates to be odd
1383 * integers so that they correspond to the center of a 2x2 block
1384 * representing the four samples that maxe up a pixel. So we need
1385 * to multiply our X and Y coordinates each by 2 and then add 1.
1387 assert(key
->src_coords_normalized
);
1388 assert(key
->filter
== BLORP_FILTER_AVERAGE
);
1389 src_pos
= nir_fadd(&b
,
1390 nir_i2f32(&b
, src_pos
),
1391 nir_imm_float(&b
, 0.5f
));
1392 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1394 /* Gen7+ hardware doesn't automaticaly blend. */
1395 color
= blorp_nir_combine_samples(&b
, &v
, src_pos
, key
->src_samples
,
1397 key
->texture_data_type
,
1403 unreachable("Invalid blorp filter");
1406 if (!isl_swizzle_is_identity(key
->src_swizzle
)) {
1407 color
= swizzle_color(&b
, color
, key
->src_swizzle
,
1408 key
->texture_data_type
);
1411 if (!isl_swizzle_is_identity(key
->dst_swizzle
)) {
1412 color
= swizzle_color(&b
, color
, isl_swizzle_invert(key
->dst_swizzle
),
1416 if (key
->format_bit_cast
) {
1417 assert(isl_swizzle_is_identity(key
->src_swizzle
));
1418 assert(isl_swizzle_is_identity(key
->dst_swizzle
));
1419 color
= bit_cast_color(&b
, color
, key
);
1420 } else if (key
->dst_format
) {
1421 color
= convert_color(&b
, color
, key
);
1422 } else if (key
->uint32_to_sint
) {
1423 /* Normally the hardware will take care of converting values from/to
1424 * the source and destination formats. But a few cases need help.
1426 * The Skylake PRM, volume 07, page 658 has a programming note:
1428 * "When using SINT or UINT rendertarget surface formats, Blending
1429 * must be DISABLED. The Pre-Blend Color Clamp Enable and Color
1430 * Clamp Range fields are ignored, and an implied clamp to the
1431 * rendertarget surface format is performed."
1433 * For UINT to SINT blits, our sample operation gives us a uint32_t,
1434 * but our render target write expects a signed int32_t number. If we
1435 * simply passed the value along, the hardware would interpret a value
1436 * with bit 31 set as a negative value, clamping it to the largest
1437 * negative number the destination format could represent. But the
1438 * actual source value is a positive number, so we want to clamp it
1439 * to INT_MAX. To fix this, we explicitly take min(color, INT_MAX).
1441 color
= nir_umin(&b
, color
, nir_imm_int(&b
, INT32_MAX
));
1442 } else if (key
->sint32_to_uint
) {
1443 /* Similar to above, but clamping negative numbers to zero. */
1444 color
= nir_imax(&b
, color
, nir_imm_int(&b
, 0));
1448 /* The destination image is bound as a red texture three times as wide
1449 * as the actual image. Our shader is effectively running one color
1450 * component at a time. We need to pick off the appropriate component
1451 * from the source color and write that to destination red.
1453 assert(dst_pos
->num_components
== 2);
1455 nir_ssa_def
*color_component
=
1456 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1457 nir_channel(&b
, color
, 0),
1458 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1459 nir_channel(&b
, color
, 1),
1460 nir_channel(&b
, color
, 2)));
1462 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1463 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1466 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1472 brw_blorp_get_blit_kernel(struct blorp_batch
*batch
,
1473 struct blorp_params
*params
,
1474 const struct brw_blorp_blit_prog_key
*prog_key
)
1476 struct blorp_context
*blorp
= batch
->blorp
;
1478 if (blorp
->lookup_shader(batch
, prog_key
, sizeof(*prog_key
),
1479 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1482 void *mem_ctx
= ralloc_context(NULL
);
1484 const unsigned *program
;
1485 struct brw_wm_prog_data prog_data
;
1487 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1488 nir
->info
.name
= ralloc_strdup(nir
, "BLORP-blit");
1490 struct brw_wm_prog_key wm_key
;
1491 brw_blorp_init_wm_prog_key(&wm_key
);
1492 wm_key
.base
.tex
.compressed_multisample_layout_mask
=
1493 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1494 wm_key
.base
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1495 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1497 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1501 blorp
->upload_shader(batch
, prog_key
, sizeof(*prog_key
),
1502 program
, prog_data
.base
.program_size
,
1503 &prog_data
.base
, sizeof(prog_data
),
1504 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1506 ralloc_free(mem_ctx
);
1511 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1512 GLfloat src0
, GLfloat src1
,
1513 GLfloat dst0
, GLfloat dst1
,
1516 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1518 /* When not mirroring a coordinate (say, X), we need:
1519 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1521 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1523 * blorp program uses "round toward zero" to convert the
1524 * transformed floating point coordinates to integer coordinates,
1525 * whereas the behaviour we actually want is "round to nearest",
1526 * so 0.5 provides the necessary correction.
1528 xform
->multiplier
= scale
;
1529 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1531 /* When mirroring X we need:
1532 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1534 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1536 xform
->multiplier
= -scale
;
1537 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1542 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1543 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1545 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1546 struct isl_extent2d px_size_sa
=
1547 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1548 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1549 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1550 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1551 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1553 *tile_x_px
= info
->tile_x_sa
;
1554 *tile_y_px
= info
->tile_y_sa
;
1559 blorp_surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1560 struct brw_blorp_surface_info
*info
)
1564 /* It would be insane to try and do this on a compressed surface */
1565 assert(info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1567 /* Just bail if we have nothing to do. */
1568 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1569 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1570 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1573 /* If this gets triggered then we've gotten here twice which. This
1574 * shouldn't happen thanks to the above early return.
1576 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1578 uint32_t layer
= 0, z
= 0;
1579 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1580 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1582 layer
= info
->view
.base_array_layer
;
1584 uint32_t byte_offset
;
1585 isl_surf_get_image_surf(isl_dev
, &info
->surf
,
1586 info
->view
.base_level
, layer
, z
,
1588 &byte_offset
, &info
->tile_x_sa
, &info
->tile_y_sa
);
1589 info
->addr
.offset
+= byte_offset
;
1591 uint32_t tile_x_px
, tile_y_px
;
1592 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1594 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we place
1595 * the image at the tile boundary and offset our sampling or rendering.
1596 * For this reason, we need to grow the image by the offset to ensure that
1597 * the hardware doesn't think we've gone past the edge.
1599 info
->surf
.logical_level0_px
.w
+= tile_x_px
;
1600 info
->surf
.logical_level0_px
.h
+= tile_y_px
;
1601 info
->surf
.phys_level0_sa
.w
+= info
->tile_x_sa
;
1602 info
->surf
.phys_level0_sa
.h
+= info
->tile_y_sa
;
1604 /* The view is also different now. */
1605 info
->view
.base_level
= 0;
1606 info
->view
.levels
= 1;
1607 info
->view
.base_array_layer
= 0;
1608 info
->view
.array_len
= 1;
1613 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1614 struct brw_blorp_surface_info
*info
)
1616 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1618 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1619 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1621 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1622 info
->surf
.samples
= 1;
1623 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1627 blorp_surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1628 struct brw_blorp_surface_info
*info
)
1630 assert(info
->surf
.tiling
== ISL_TILING_W
);
1632 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1633 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1635 /* On gen7+, we don't have interleaved multisampling for color render
1636 * targets so we have to fake it.
1638 * TODO: Are we sure we don't also need to fake it on gen6?
1640 if (isl_dev
->info
->gen
> 6 &&
1641 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1642 surf_fake_interleaved_msaa(isl_dev
, info
);
1645 if (isl_dev
->info
->gen
== 6) {
1646 /* Gen6 stencil buffers have a very large alignment coming in from the
1647 * miptree. It's out-of-bounds for what the surface state can handle.
1648 * Since we have a single layer and level, it doesn't really matter as
1649 * long as we don't pass a bogus value into isl_surf_fill_state().
1651 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1654 /* Now that we've converted everything to a simple 2-D surface with only
1655 * one miplevel, we can go about retiling it.
1657 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1658 info
->surf
.tiling
= ISL_TILING_Y0
;
1659 info
->surf
.logical_level0_px
.width
=
1660 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1661 info
->surf
.logical_level0_px
.height
=
1662 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1663 info
->tile_x_sa
*= 2;
1664 info
->tile_y_sa
/= 2;
1668 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1670 /* The current code doesn't support offsets into the aux buffers. This
1671 * should be possible, but we need to make sure the offset is page
1672 * aligned for both the surface and the aux buffer surface. Generally
1673 * this mean using the page aligned offset for the aux buffer.
1675 * Currently the cases where we must split the blit are limited to cases
1676 * where we don't have a aux buffer.
1678 if (surf
->aux_addr
.buffer
!= NULL
)
1681 /* We can't support splitting the blit for gen <= 7, because the qpitch
1682 * size is calculated by the hardware based on the surface height for
1683 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1685 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1692 can_shrink_surfaces(const struct blorp_params
*params
)
1695 can_shrink_surface(¶ms
->src
) &&
1696 can_shrink_surface(¶ms
->dst
);
1700 get_max_surface_size(const struct gen_device_info
*devinfo
,
1701 const struct blorp_params
*params
)
1703 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1704 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1705 return max
>> 4; /* A smaller restriction when debug is enabled */
1711 double src0
, src1
, dst0
, dst1
;
1716 struct blt_axis x
, y
;
1719 static enum isl_format
1720 get_red_format_for_rgb_format(enum isl_format format
)
1722 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1724 switch (fmtl
->channels
.r
.bits
) {
1726 switch (fmtl
->channels
.r
.type
) {
1728 return ISL_FORMAT_R8_UNORM
;
1730 return ISL_FORMAT_R8_SNORM
;
1732 return ISL_FORMAT_R8_UINT
;
1734 return ISL_FORMAT_R8_SINT
;
1736 unreachable("Invalid 8-bit RGB channel type");
1739 switch (fmtl
->channels
.r
.type
) {
1741 return ISL_FORMAT_R16_UNORM
;
1743 return ISL_FORMAT_R16_SNORM
;
1745 return ISL_FORMAT_R16_FLOAT
;
1747 return ISL_FORMAT_R16_UINT
;
1749 return ISL_FORMAT_R16_SINT
;
1751 unreachable("Invalid 8-bit RGB channel type");
1754 switch (fmtl
->channels
.r
.type
) {
1756 return ISL_FORMAT_R32_FLOAT
;
1758 return ISL_FORMAT_R32_UINT
;
1760 return ISL_FORMAT_R32_SINT
;
1762 unreachable("Invalid 8-bit RGB channel type");
1765 unreachable("Invalid number of red channel bits");
1770 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1771 struct brw_blorp_surface_info
*info
)
1773 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1775 info
->surf
.logical_level0_px
.width
*= 3;
1776 info
->surf
.phys_level0_sa
.width
*= 3;
1777 info
->tile_x_sa
*= 3;
1779 enum isl_format red_format
=
1780 get_red_format_for_rgb_format(info
->view
.format
);
1782 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1783 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1784 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1785 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1787 info
->surf
.format
= info
->view
.format
= red_format
;
1790 enum blit_shrink_status
{
1792 BLIT_WIDTH_SHRINK
= 1,
1793 BLIT_HEIGHT_SHRINK
= 2,
1796 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1797 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1798 * returned, then the blit was successful.
1800 static enum blit_shrink_status
1801 try_blorp_blit(struct blorp_batch
*batch
,
1802 struct blorp_params
*params
,
1803 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1804 struct blt_coords
*coords
)
1806 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1808 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1809 wm_prog_key
->texture_data_type
= nir_type_int
;
1810 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1811 wm_prog_key
->texture_data_type
= nir_type_uint
;
1813 wm_prog_key
->texture_data_type
= nir_type_float
;
1816 /* src_samples and dst_samples are the true sample counts */
1817 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1818 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1820 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1822 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1825 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1826 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1828 /* Round floating point values to nearest integer to avoid "off by one texel"
1829 * kind of errors when blitting.
1831 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1832 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1833 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1834 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1836 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1837 coords
->x
.src0
, coords
->x
.src1
,
1838 coords
->x
.dst0
, coords
->x
.dst1
,
1840 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1841 coords
->y
.src0
, coords
->y
.src1
,
1842 coords
->y
.dst0
, coords
->y
.dst1
,
1846 if (devinfo
->gen
== 4) {
1847 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
1848 * Convert them to a single slice on gen4.
1850 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1851 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1852 wm_prog_key
->need_dst_offset
= true;
1855 if (params
->src
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1856 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->src
);
1857 wm_prog_key
->need_src_offset
= true;
1861 if (devinfo
->gen
> 6 &&
1862 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1863 assert(params
->dst
.surf
.samples
> 1);
1865 /* We must expand the rectangle we send through the rendering pipeline,
1866 * to account for the fact that we are mapping the destination region as
1867 * single-sampled when it is in fact multisampled. We must also align
1868 * it to a multiple of the multisampling pattern, because the
1869 * differences between multisampled and single-sampled surface formats
1870 * will mean that pixels are scrambled within the multisampling pattern.
1871 * TODO: what if this makes the coordinates too large?
1873 * Note: this only works if the destination surface uses the IMS layout.
1874 * If it's UMS, then we have no choice but to set up the rendering
1875 * pipeline as multisampled.
1877 struct isl_extent2d px_size_sa
=
1878 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1879 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1880 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1881 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1882 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1884 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1886 wm_prog_key
->use_kill
= true;
1887 wm_prog_key
->need_dst_offset
= true;
1890 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1891 /* We must modify the rectangle we send through the rendering pipeline
1892 * (and the size and x/y offset of the destination surface), to account
1893 * for the fact that we are mapping it as Y-tiled when it is in fact
1896 * Both Y tiling and W tiling can be understood as organizations of
1897 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1898 * is different, but the layout of the 32-byte sub-tiles within the 4k
1899 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1900 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1901 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1903 * Therefore, to account for the layout differences within the 32-byte
1904 * sub-tiles, we must expand the rectangle so the X coordinates of its
1905 * edges are multiples of 8 (the W sub-tile width), and its Y
1906 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1907 * Then we need to scale the X and Y coordinates of the rectangle to
1908 * account for the differences in aspect ratio between the Y and W
1909 * sub-tiles. We need to modify the layer width and height similarly.
1911 * A correction needs to be applied when MSAA is in use: since
1912 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1913 * we need to align the Y coordinates to multiples of 8, so that when
1914 * they are divided by two they are still multiples of 4.
1916 * Note: Since the x/y offset of the surface will be applied using the
1917 * SURFACE_STATE command packet, it will be invisible to the swizzling
1918 * code in the shader; therefore it needs to be in a multiple of the
1919 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1920 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1921 * buffer), and the miplevel alignment used for stencil buffers is 8
1922 * pixels horizontally and either 4 or 8 pixels vertically (see
1923 * intel_horizontal_texture_alignment_unit() and
1924 * intel_vertical_texture_alignment_unit()).
1926 * Note: Also, since the SURFACE_STATE command packet can only apply
1927 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1928 * vertically, it is important that the offsets will be multiples of
1929 * these sizes after they are converted into Y-tiled coordinates.
1930 * Fortunately they will be, since we know from above that the offsets
1931 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1932 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1934 * TODO: what if this makes the coordinates (or the texture size) too
1937 const unsigned x_align
= 8;
1938 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1939 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1940 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1941 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1942 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1944 /* Retile the surface to Y-tiled */
1945 blorp_surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1947 wm_prog_key
->dst_tiled_w
= true;
1948 wm_prog_key
->use_kill
= true;
1949 wm_prog_key
->need_dst_offset
= true;
1951 if (params
->dst
.surf
.samples
> 1) {
1952 /* If the destination surface is a W-tiled multisampled stencil
1953 * buffer that we're mapping as Y tiled, then we need to arrange for
1954 * the WM program to run once per sample rather than once per pixel,
1955 * because the memory layout of related samples doesn't match between
1958 wm_prog_key
->persample_msaa_dispatch
= true;
1962 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1963 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1964 * Broadwell adds support for sampling from stencil.
1966 * See the comments above concerning x/y offset alignment for the
1967 * destination surface.
1969 * TODO: what if this makes the texture size too large?
1971 blorp_surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1973 wm_prog_key
->src_tiled_w
= true;
1974 wm_prog_key
->need_src_offset
= true;
1977 /* tex_samples and rt_samples are the sample counts that are set up in
1980 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1981 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1983 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1984 * use to access the source and destination surfaces.
1986 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1987 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1989 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1990 /* We are blitting from a multisample buffer to a multisample buffer, so
1991 * we must preserve samples within a pixel. This means we have to
1992 * arrange for the WM program to run once per sample rather than once
1995 wm_prog_key
->persample_msaa_dispatch
= true;
1998 params
->num_samples
= params
->dst
.surf
.samples
;
2000 if ((wm_prog_key
->filter
== BLORP_FILTER_AVERAGE
||
2001 wm_prog_key
->filter
== BLORP_FILTER_BILINEAR
) &&
2002 batch
->blorp
->isl_dev
->info
->gen
<= 6) {
2003 /* Gen4-5 don't support non-normalized texture coordinates */
2004 wm_prog_key
->src_coords_normalized
= true;
2005 params
->wm_inputs
.src_inv_size
[0] =
2006 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.width
,
2007 params
->src
.view
.base_level
);
2008 params
->wm_inputs
.src_inv_size
[1] =
2009 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.height
,
2010 params
->src
.view
.base_level
);
2013 if (isl_format_get_layout(params
->dst
.view
.format
)->bpb
% 3 == 0) {
2014 /* We can't render to RGB formats natively because they aren't a
2015 * power-of-two size. Instead, we fake them by using a red format
2016 * with the same channel type and size and emitting shader code to
2017 * only write one channel at a time.
2022 /* If it happens to be sRGB, we need to force a conversion */
2023 if (params
->dst
.view
.format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
)
2024 wm_prog_key
->dst_format
= ISL_FORMAT_R8G8B8_UNORM_SRGB
;
2026 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
->dst
);
2028 wm_prog_key
->dst_rgb
= true;
2029 wm_prog_key
->need_dst_offset
= true;
2030 } else if (isl_format_is_rgbx(params
->dst
.view
.format
)) {
2031 /* We can handle RGBX formats easily enough by treating them as RGBA */
2032 params
->dst
.view
.format
=
2033 isl_format_rgbx_to_rgba(params
->dst
.view
.format
);
2034 } else if (params
->dst
.view
.format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
2035 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2036 params
->dst
.view
.format
= ISL_FORMAT_R32_UINT
;
2037 } else if (params
->dst
.view
.format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
2038 params
->dst
.view
.swizzle
=
2039 isl_swizzle_compose(params
->dst
.view
.swizzle
,
2040 ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
));
2041 params
->dst
.view
.format
= ISL_FORMAT_B4G4R4A4_UNORM
;
2042 } else if (params
->dst
.view
.format
== ISL_FORMAT_L8_UNORM_SRGB
) {
2043 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2044 params
->dst
.view
.format
= ISL_FORMAT_R8_UNORM
;
2045 } else if (params
->dst
.view
.format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
2046 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
2047 params
->dst
.view
.format
= ISL_FORMAT_R32_UINT
;
2050 if (devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
2051 !isl_swizzle_is_identity(params
->src
.view
.swizzle
)) {
2052 wm_prog_key
->src_swizzle
= params
->src
.view
.swizzle
;
2053 params
->src
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
2055 wm_prog_key
->src_swizzle
= ISL_SWIZZLE_IDENTITY
;
2058 if (!isl_swizzle_supports_rendering(devinfo
, params
->dst
.view
.swizzle
)) {
2059 wm_prog_key
->dst_swizzle
= params
->dst
.view
.swizzle
;
2060 params
->dst
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
2062 wm_prog_key
->dst_swizzle
= ISL_SWIZZLE_IDENTITY
;
2065 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
2066 assert(wm_prog_key
->need_src_offset
);
2067 surf_get_intratile_offset_px(¶ms
->src
,
2068 ¶ms
->wm_inputs
.src_offset
.x
,
2069 ¶ms
->wm_inputs
.src_offset
.y
);
2072 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
2073 assert(wm_prog_key
->need_dst_offset
);
2074 surf_get_intratile_offset_px(¶ms
->dst
,
2075 ¶ms
->wm_inputs
.dst_offset
.x
,
2076 ¶ms
->wm_inputs
.dst_offset
.y
);
2077 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
2078 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
2079 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
2080 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
2083 /* For some texture types, we need to pass the layer through the sampler. */
2084 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
2086 if (!brw_blorp_get_blit_kernel(batch
, params
, wm_prog_key
))
2089 if (!blorp_ensure_sf_program(batch
, params
))
2092 unsigned result
= 0;
2093 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
2094 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
2095 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
2096 result
|= BLIT_WIDTH_SHRINK
;
2097 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
2098 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
2099 result
|= BLIT_HEIGHT_SHRINK
;
2102 batch
->blorp
->exec(batch
, params
);
2108 /* Adjust split blit source coordinates for the current destination
2112 adjust_split_source_coords(const struct blt_axis
*orig
,
2113 struct blt_axis
*split_coords
,
2116 /* When scale is greater than 0, then we are growing from the start, so
2117 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
2118 * source range shrinks from the end. In that case src0 is adjusted by
2119 * delta1, and src1 is adjusted by delta0.
2121 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
2122 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
2123 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
2124 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
2127 static struct isl_extent2d
2128 get_px_size_sa(const struct isl_surf
*surf
)
2130 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
2132 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
2135 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
2139 shrink_surface_params(const struct isl_device
*dev
,
2140 struct brw_blorp_surface_info
*info
,
2141 double *x0
, double *x1
, double *y0
, double *y1
)
2143 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
2144 struct isl_extent2d px_size_sa
;
2147 blorp_surf_convert_to_single_slice(dev
, info
);
2149 px_size_sa
= get_px_size_sa(&info
->surf
);
2151 /* Because this gets called after we lower compressed images, the tile
2152 * offsets may be non-zero and we need to incorporate them in our
2155 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
2156 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
2157 isl_tiling_get_intratile_offset_sa(info
->surf
.tiling
,
2158 info
->surf
.format
, info
->surf
.row_pitch_B
,
2159 x_offset_sa
, y_offset_sa
,
2161 &info
->tile_x_sa
, &info
->tile_y_sa
);
2163 info
->addr
.offset
+= byte_offset
;
2165 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
2168 info
->tile_x_sa
= 0;
2170 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
2173 info
->tile_y_sa
= 0;
2175 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
2176 info
->surf
.logical_level0_px
.width
= size
;
2177 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
2179 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
2180 info
->surf
.logical_level0_px
.height
= size
;
2181 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
2185 shrink_surfaces(const struct isl_device
*dev
,
2186 struct blorp_params
*params
,
2187 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2188 struct blt_coords
*coords
)
2190 /* Shrink source surface */
2191 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
2192 &coords
->y
.src0
, &coords
->y
.src1
);
2193 wm_prog_key
->need_src_offset
= false;
2195 /* Shrink destination surface */
2196 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
2197 &coords
->y
.dst0
, &coords
->y
.dst1
);
2198 wm_prog_key
->need_dst_offset
= false;
2202 do_blorp_blit(struct blorp_batch
*batch
,
2203 const struct blorp_params
*orig_params
,
2204 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2205 const struct blt_coords
*orig
)
2207 struct blorp_params params
;
2208 struct blt_coords blit_coords
;
2209 struct blt_coords split_coords
= *orig
;
2210 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
2211 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
2212 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
2213 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
2219 bool x_done
, y_done
;
2220 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
2222 params
= *orig_params
;
2223 blit_coords
= split_coords
;
2225 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
2227 enum blit_shrink_status result
=
2228 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
2230 if (result
& BLIT_WIDTH_SHRINK
) {
2233 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2234 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2236 if (result
& BLIT_HEIGHT_SHRINK
) {
2239 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2240 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2244 assert(can_shrink_surfaces(orig_params
));
2249 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
2250 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
2253 } else if (y_done
) {
2254 split_coords
.x
.dst0
+= w
;
2255 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2256 split_coords
.y
.dst0
= orig
->y
.dst0
;
2257 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2258 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2260 split_coords
.y
.dst0
+= h
;
2261 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2262 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2268 blorp_blit(struct blorp_batch
*batch
,
2269 const struct blorp_surf
*src_surf
,
2270 unsigned src_level
, unsigned src_layer
,
2271 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2272 const struct blorp_surf
*dst_surf
,
2273 unsigned dst_level
, unsigned dst_layer
,
2274 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2275 float src_x0
, float src_y0
,
2276 float src_x1
, float src_y1
,
2277 float dst_x0
, float dst_y0
,
2278 float dst_x1
, float dst_y1
,
2279 enum blorp_filter filter
,
2280 bool mirror_x
, bool mirror_y
)
2282 struct blorp_params params
;
2283 blorp_params_init(¶ms
);
2285 /* We cannot handle combined depth and stencil. */
2286 if (src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2287 assert(src_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2288 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2289 assert(dst_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2291 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
2292 assert(src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
);
2293 /* Prior to Broadwell, we can't render to R8_UINT */
2294 if (batch
->blorp
->isl_dev
->info
->gen
< 8) {
2295 src_format
= ISL_FORMAT_R8_UNORM
;
2296 dst_format
= ISL_FORMAT_R8_UNORM
;
2300 /* ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as a render target,
2301 * which requires shader math to render to it. Blitting Z24X8 to Z24X8
2302 * is fairly common though, so we'd like to avoid it. Since we don't need
2303 * to blend depth values, we can simply pick a renderable format with the
2304 * right number of bits-per-pixel, like 8-bit BGRA.
2306 if (dst_surf
->surf
->format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
&&
2307 src_surf
->surf
->format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
2308 src_format
= dst_format
= ISL_FORMAT_B8G8R8A8_UNORM
;
2311 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2312 src_layer
, src_format
, false);
2313 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2314 dst_layer
, dst_format
, true);
2316 params
.src
.view
.swizzle
= src_swizzle
;
2317 params
.dst
.view
.swizzle
= dst_swizzle
;
2319 const struct isl_format_layout
*src_fmtl
=
2320 isl_format_get_layout(params
.src
.view
.format
);
2322 struct brw_blorp_blit_prog_key wm_prog_key
= {
2323 .shader_type
= BLORP_SHADER_TYPE_BLIT
,
2325 .sint32_to_uint
= src_fmtl
->channels
.r
.bits
== 32 &&
2326 isl_format_has_sint_channel(params
.src
.view
.format
) &&
2327 isl_format_has_uint_channel(params
.dst
.view
.format
),
2328 .uint32_to_sint
= src_fmtl
->channels
.r
.bits
== 32 &&
2329 isl_format_has_uint_channel(params
.src
.view
.format
) &&
2330 isl_format_has_sint_channel(params
.dst
.view
.format
),
2333 /* Scaling factors used for bilinear filtering in multisample scaled
2336 if (params
.src
.surf
.samples
== 16)
2337 wm_prog_key
.x_scale
= 4.0f
;
2339 wm_prog_key
.x_scale
= 2.0f
;
2340 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2342 params
.wm_inputs
.rect_grid
.x1
=
2343 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2344 wm_prog_key
.x_scale
- 1.0f
;
2345 params
.wm_inputs
.rect_grid
.y1
=
2346 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2347 wm_prog_key
.y_scale
- 1.0f
;
2349 struct blt_coords coords
= {
2366 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2369 static enum isl_format
2370 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2372 /* The choice of UNORM and UINT formats is very intentional here. Most
2373 * of the time, we want to use a UINT format to avoid any rounding error
2374 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2375 * (It's the only format allowed in conjunction with W-tiling.) Also we
2376 * intentionally use the 4-channel formats whenever we can. This is so
2377 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2378 * even though one of them is 3/4 the size of the other. The choice of
2379 * UNORM vs. UINT is also very intentional because we don't have 8 or
2380 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2381 * Fortunately, the only time we should ever use two different formats in
2382 * the table below is for RGB -> RGBA blits and so we will never have any
2383 * UNORM/UINT mismatch.
2385 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2387 case 8: return ISL_FORMAT_R8_UINT
;
2388 case 16: return ISL_FORMAT_R8G8_UINT
;
2389 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2390 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2391 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2392 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2393 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2394 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2396 unreachable("Unknown format bpb");
2400 case 8: return ISL_FORMAT_R8_UINT
;
2401 case 16: return ISL_FORMAT_R8G8_UINT
;
2402 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2403 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2404 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2405 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2406 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2407 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2409 unreachable("Unknown format bpb");
2414 /** Returns a UINT format that is CCS-compatible with the given format
2416 * The PRM's say absolutely nothing about how render compression works. The
2417 * only thing they provide is a list of formats on which it is and is not
2418 * supported. Empirical testing indicates that the compression is only based
2419 * on the bit-layout of the format and the channel encoding doesn't matter.
2420 * So, while texture views don't work in general, you can create a view as
2421 * long as the bit-layout of the formats are the same.
2423 * Fortunately, for every render compression capable format, the UINT format
2424 * with the same bit layout also supports render compression. This means that
2425 * we only need to handle UINT formats for copy operations. In order to do
2426 * copies between formats with different bit layouts, we attach both with a
2427 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2428 * operation between the two bit layouts.
2430 static enum isl_format
2431 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2433 switch (fmtl
->format
) {
2434 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2435 case ISL_FORMAT_R32G32B32A32_SINT
:
2436 case ISL_FORMAT_R32G32B32A32_UINT
:
2437 case ISL_FORMAT_R32G32B32A32_UNORM
:
2438 case ISL_FORMAT_R32G32B32A32_SNORM
:
2439 case ISL_FORMAT_R32G32B32X32_FLOAT
:
2440 return ISL_FORMAT_R32G32B32A32_UINT
;
2442 case ISL_FORMAT_R16G16B16A16_UNORM
:
2443 case ISL_FORMAT_R16G16B16A16_SNORM
:
2444 case ISL_FORMAT_R16G16B16A16_SINT
:
2445 case ISL_FORMAT_R16G16B16A16_UINT
:
2446 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2447 case ISL_FORMAT_R16G16B16X16_UNORM
:
2448 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2449 return ISL_FORMAT_R16G16B16A16_UINT
;
2451 case ISL_FORMAT_R32G32_FLOAT
:
2452 case ISL_FORMAT_R32G32_SINT
:
2453 case ISL_FORMAT_R32G32_UINT
:
2454 case ISL_FORMAT_R32G32_UNORM
:
2455 case ISL_FORMAT_R32G32_SNORM
:
2456 return ISL_FORMAT_R32G32_UINT
;
2458 case ISL_FORMAT_B8G8R8A8_UNORM
:
2459 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2460 case ISL_FORMAT_R8G8B8A8_UNORM
:
2461 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2462 case ISL_FORMAT_R8G8B8A8_SNORM
:
2463 case ISL_FORMAT_R8G8B8A8_SINT
:
2464 case ISL_FORMAT_R8G8B8A8_UINT
:
2465 case ISL_FORMAT_B8G8R8X8_UNORM
:
2466 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2467 case ISL_FORMAT_R8G8B8X8_UNORM
:
2468 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2469 return ISL_FORMAT_R8G8B8A8_UINT
;
2471 case ISL_FORMAT_R16G16_UNORM
:
2472 case ISL_FORMAT_R16G16_SNORM
:
2473 case ISL_FORMAT_R16G16_SINT
:
2474 case ISL_FORMAT_R16G16_UINT
:
2475 case ISL_FORMAT_R16G16_FLOAT
:
2476 return ISL_FORMAT_R16G16_UINT
;
2478 case ISL_FORMAT_R32_SINT
:
2479 case ISL_FORMAT_R32_UINT
:
2480 case ISL_FORMAT_R32_FLOAT
:
2481 case ISL_FORMAT_R32_UNORM
:
2482 case ISL_FORMAT_R32_SNORM
:
2483 return ISL_FORMAT_R32_UINT
;
2485 case ISL_FORMAT_B10G10R10A2_UNORM
:
2486 case ISL_FORMAT_B10G10R10A2_UNORM_SRGB
:
2487 case ISL_FORMAT_R10G10B10A2_UNORM
:
2488 case ISL_FORMAT_R10G10B10A2_UINT
:
2489 return ISL_FORMAT_R10G10B10A2_UINT
;
2492 unreachable("Not a compressible format");
2497 blorp_surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2498 struct brw_blorp_surface_info
*info
,
2499 uint32_t *x
, uint32_t *y
,
2500 uint32_t *width
, uint32_t *height
)
2502 const struct isl_format_layout
*fmtl
=
2503 isl_format_get_layout(info
->surf
.format
);
2505 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2507 /* This is a compressed surface. We need to convert it to a single
2508 * slice (because compressed layouts don't perfectly match uncompressed
2509 * ones with the same bpb) and divide x, y, width, and height by the
2512 blorp_surf_convert_to_single_slice(isl_dev
, info
);
2514 if (width
&& height
) {
2516 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2517 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2518 assert(*width
% fmtl
->bw
== 0 ||
2519 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2520 assert(*height
% fmtl
->bh
== 0 ||
2521 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2523 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2524 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2528 assert(*x
% fmtl
->bw
== 0);
2529 assert(*y
% fmtl
->bh
== 0);
2534 info
->surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&info
->surf
);
2535 info
->surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&info
->surf
);
2537 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2538 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2539 info
->tile_x_sa
/= fmtl
->bw
;
2540 info
->tile_y_sa
/= fmtl
->bh
;
2542 /* It's now an uncompressed surface so we need an uncompressed format */
2543 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2547 blorp_copy(struct blorp_batch
*batch
,
2548 const struct blorp_surf
*src_surf
,
2549 unsigned src_level
, unsigned src_layer
,
2550 const struct blorp_surf
*dst_surf
,
2551 unsigned dst_level
, unsigned dst_layer
,
2552 uint32_t src_x
, uint32_t src_y
,
2553 uint32_t dst_x
, uint32_t dst_y
,
2554 uint32_t src_width
, uint32_t src_height
)
2556 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2557 struct blorp_params params
;
2559 if (src_width
== 0 || src_height
== 0)
2562 blorp_params_init(¶ms
);
2563 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2564 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2565 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2566 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2568 struct brw_blorp_blit_prog_key wm_prog_key
= {
2569 .shader_type
= BLORP_SHADER_TYPE_BLIT
,
2570 .filter
= BLORP_FILTER_NONE
,
2571 .need_src_offset
= src_surf
->tile_x_sa
|| src_surf
->tile_y_sa
,
2572 .need_dst_offset
= dst_surf
->tile_x_sa
|| dst_surf
->tile_y_sa
,
2575 const struct isl_format_layout
*src_fmtl
=
2576 isl_format_get_layout(params
.src
.surf
.format
);
2577 const struct isl_format_layout
*dst_fmtl
=
2578 isl_format_get_layout(params
.dst
.surf
.format
);
2580 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2581 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2582 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2583 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2584 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2585 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2587 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2588 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2589 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2590 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2591 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2592 params
.src
.view
.format
= params
.dst
.view
.format
;
2594 params
.src
.view
.format
=
2595 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2597 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2598 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2599 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2600 params
.dst
.view
.format
= params
.src
.view
.format
;
2602 params
.dst
.view
.format
=
2603 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2606 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2607 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2610 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2611 /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
2612 * enabled even though CCS_E doesn't technically do sRGB on SKL because
2613 * we stomp everything to UINT anyway. The one thing we have to be
2614 * careful of is clear colors. Because fast clear colors for sRGB on
2615 * gen9 are encoded as the float values between format conversion and
2616 * sRGB curve application, a given clear color float will convert to the
2617 * same bits regardless of whether the format is UNORM or sRGB.
2618 * Therefore, we can handle sRGB without any special cases.
2620 UNUSED
enum isl_format linear_src_format
=
2621 isl_format_srgb_to_linear(src_surf
->surf
->format
);
2622 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2624 params
.src
.view
.format
));
2626 isl_color_value_pack(¶ms
.src
.clear_color
,
2627 linear_src_format
, packed
);
2628 isl_color_value_unpack(¶ms
.src
.clear_color
,
2629 params
.src
.view
.format
, packed
);
2632 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2633 /* See above where we handle linear_src_format */
2634 UNUSED
enum isl_format linear_dst_format
=
2635 isl_format_srgb_to_linear(dst_surf
->surf
->format
);
2636 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2638 params
.dst
.view
.format
));
2640 isl_color_value_pack(¶ms
.dst
.clear_color
,
2641 linear_dst_format
, packed
);
2642 isl_color_value_unpack(¶ms
.dst
.clear_color
,
2643 params
.dst
.view
.format
, packed
);
2646 if (params
.src
.view
.format
!= params
.dst
.view
.format
) {
2647 enum isl_format src_cast_format
= params
.src
.view
.format
;
2648 enum isl_format dst_cast_format
= params
.dst
.view
.format
;
2650 /* The BLORP bitcast code gets confused by RGB formats. Just treat them
2651 * as RGBA and then everything will be happy. This is perfectly safe
2652 * because BLORP likes to treat things as if they have vec4 colors all
2655 if (isl_format_is_rgb(src_cast_format
))
2656 src_cast_format
= isl_format_rgb_to_rgba(src_cast_format
);
2657 if (isl_format_is_rgb(dst_cast_format
))
2658 dst_cast_format
= isl_format_rgb_to_rgba(dst_cast_format
);
2660 if (src_cast_format
!= dst_cast_format
) {
2661 wm_prog_key
.format_bit_cast
= true;
2662 wm_prog_key
.src_format
= src_cast_format
;
2663 wm_prog_key
.dst_format
= dst_cast_format
;
2667 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2668 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2670 &src_width
, &src_height
);
2671 wm_prog_key
.need_src_offset
= true;
2674 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2675 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2676 &dst_x
, &dst_y
, NULL
, NULL
);
2677 wm_prog_key
.need_dst_offset
= true;
2680 /* Once both surfaces are stompped to uncompressed as needed, the
2681 * destination size is the same as the source size.
2683 uint32_t dst_width
= src_width
;
2684 uint32_t dst_height
= src_height
;
2686 struct blt_coords coords
= {
2689 .src1
= src_x
+ src_width
,
2691 .dst1
= dst_x
+ dst_width
,
2696 .src1
= src_y
+ src_height
,
2698 .dst1
= dst_y
+ dst_height
,
2703 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2706 static enum isl_format
2707 isl_format_for_size(unsigned size_B
)
2710 case 1: return ISL_FORMAT_R8_UINT
;
2711 case 2: return ISL_FORMAT_R8G8_UINT
;
2712 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
2713 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
2714 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
2716 unreachable("Not a power-of-two format size");
2721 * Returns the greatest common divisor of a and b that is a power of two.
2724 gcd_pow2_u64(uint64_t a
, uint64_t b
)
2726 assert(a
> 0 || b
> 0);
2728 unsigned a_log2
= ffsll(a
) - 1;
2729 unsigned b_log2
= ffsll(b
) - 1;
2731 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
2732 * case, the MIN2() will take the other one. If both are 0 then we will
2733 * hit the assert above.
2735 return 1 << MIN2(a_log2
, b_log2
);
2739 do_buffer_copy(struct blorp_batch
*batch
,
2740 struct blorp_address
*src
,
2741 struct blorp_address
*dst
,
2742 int width
, int height
, int block_size
)
2744 /* The actual format we pick doesn't matter as blorp will throw it away.
2745 * The only thing that actually matters is the size.
2747 enum isl_format format
= isl_format_for_size(block_size
);
2750 struct isl_surf surf
;
2751 ok
= isl_surf_init(batch
->blorp
->isl_dev
, &surf
,
2752 .dim
= ISL_SURF_DIM_2D
,
2760 .row_pitch_B
= width
* block_size
,
2761 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
2762 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
2763 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
2766 struct blorp_surf src_blorp_surf
= {
2771 struct blorp_surf dst_blorp_surf
= {
2776 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
2777 0, 0, 0, 0, width
, height
);
2781 blorp_buffer_copy(struct blorp_batch
*batch
,
2782 struct blorp_address src
,
2783 struct blorp_address dst
,
2786 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
2787 uint64_t copy_size
= size
;
2789 /* This is maximum possible width/height our HW can handle */
2790 uint64_t max_surface_dim
= 1 << (devinfo
->gen
>= 7 ? 14 : 13);
2792 /* First, we compute the biggest format that can be used with the
2793 * given offsets and size.
2796 bs
= gcd_pow2_u64(bs
, src
.offset
);
2797 bs
= gcd_pow2_u64(bs
, dst
.offset
);
2798 bs
= gcd_pow2_u64(bs
, size
);
2800 /* First, we make a bunch of max-sized copies */
2801 uint64_t max_copy_size
= max_surface_dim
* max_surface_dim
* bs
;
2802 while (copy_size
>= max_copy_size
) {
2803 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, max_surface_dim
, bs
);
2804 copy_size
-= max_copy_size
;
2805 src
.offset
+= max_copy_size
;
2806 dst
.offset
+= max_copy_size
;
2809 /* Now make a max-width copy */
2810 uint64_t height
= copy_size
/ (max_surface_dim
* bs
);
2811 assert(height
< max_surface_dim
);
2813 uint64_t rect_copy_size
= height
* max_surface_dim
* bs
;
2814 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, height
, bs
);
2815 copy_size
-= rect_copy_size
;
2816 src
.offset
+= rect_copy_size
;
2817 dst
.offset
+= rect_copy_size
;
2820 /* Finally, make a small copy to finish it off */
2821 if (copy_size
!= 0) {
2822 do_buffer_copy(batch
, &src
, &dst
, copy_size
/ bs
, 1, bs
);