2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/ralloc.h"
26 #include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
27 #include "util/format_rgb9e5.h"
29 #include "blorp_priv.h"
30 #include "brw_defines.h"
32 #include "compiler/nir/nir_builder.h"
34 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 struct brw_blorp_const_color_prog_key
38 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_CLEAR */
39 bool use_simd16_replicated_data
;
44 blorp_params_get_clear_kernel(struct blorp_context
*blorp
,
45 struct blorp_params
*params
,
46 bool use_replicated_data
)
48 const struct brw_blorp_const_color_prog_key blorp_key
= {
49 .shader_type
= BLORP_SHADER_TYPE_CLEAR
,
50 .use_simd16_replicated_data
= use_replicated_data
,
53 if (blorp
->lookup_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
54 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
57 void *mem_ctx
= ralloc_context(NULL
);
60 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
61 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, "BLORP-clear");
63 nir_variable
*v_color
= nir_variable_create(b
.shader
, nir_var_shader_in
,
64 glsl_vec4_type(), "v_color");
65 v_color
->data
.location
= VARYING_SLOT_VAR0
;
66 v_color
->data
.interpolation
= INTERP_MODE_FLAT
;
68 nir_variable
*frag_color
= nir_variable_create(b
.shader
, nir_var_shader_out
,
71 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
73 nir_copy_var(&b
, frag_color
, v_color
);
75 struct brw_wm_prog_key wm_key
;
76 brw_blorp_init_wm_prog_key(&wm_key
);
78 struct brw_wm_prog_data prog_data
;
79 unsigned program_size
;
80 const unsigned *program
=
81 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, use_replicated_data
,
82 &prog_data
, &program_size
);
84 blorp
->upload_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
85 program
, program_size
,
86 &prog_data
.base
, sizeof(prog_data
),
87 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
92 /* The x0, y0, x1, and y1 parameters must already be populated with the render
93 * area of the framebuffer to be cleared.
96 get_fast_clear_rect(const struct isl_device
*dev
,
97 const struct isl_surf
*aux_surf
,
98 unsigned *x0
, unsigned *y0
,
99 unsigned *x1
, unsigned *y1
)
101 unsigned int x_align
, y_align
;
102 unsigned int x_scaledown
, y_scaledown
;
104 /* Only single sampled surfaces need to (and actually can) be resolved. */
105 if (aux_surf
->usage
== ISL_SURF_USAGE_CCS_BIT
) {
106 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
107 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
109 * Clear pass must have a clear rectangle that must follow
110 * alignment rules in terms of pixels and lines as shown in the
111 * table below. Further, the clear-rectangle height and width
112 * must be multiple of the following dimensions. If the height
113 * and width of the render target being cleared do not meet these
114 * requirements, an MCS buffer can be created such that it
115 * follows the requirement and covers the RT.
117 * The alignment size in the table that follows is related to the
118 * alignment size that is baked into the CCS surface format but with X
119 * alignment multiplied by 16 and Y alignment multiplied by 32.
121 x_align
= isl_format_get_layout(aux_surf
->format
)->bw
;
122 y_align
= isl_format_get_layout(aux_surf
->format
)->bh
;
126 /* SKL+ line alignment requirement for Y-tiled are half those of the prior
129 if (dev
->info
->gen
>= 9)
134 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
135 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
137 * In order to optimize the performance MCS buffer (when bound to
138 * 1X RT) clear similarly to MCS buffer clear for MSRT case,
139 * clear rect is required to be scaled by the following factors
140 * in the horizontal and vertical directions:
142 * The X and Y scale down factors in the table that follows are each
143 * equal to half the alignment value computed above.
145 x_scaledown
= x_align
/ 2;
146 y_scaledown
= y_align
/ 2;
148 /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
149 * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
150 * Clear of Non-MultiSampled Render Target Restrictions":
152 * Clear rectangle must be aligned to two times the number of
153 * pixels in the table shown below due to 16x16 hashing across the
159 assert(aux_surf
->usage
== ISL_SURF_USAGE_MCS_BIT
);
161 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
162 * Target(s)", beneath the "MSAA Compression" bullet (p326):
164 * Clear pass for this case requires that scaled down primitive
165 * is sent down with upper left co-ordinate to coincide with
166 * actual rectangle being cleared. For MSAA, clear rectangle’s
167 * height and width need to as show in the following table in
168 * terms of (width,height) of the RT.
170 * MSAA Width of Clear Rect Height of Clear Rect
171 * 2X Ceil(1/8*width) Ceil(1/2*height)
172 * 4X Ceil(1/8*width) Ceil(1/2*height)
173 * 8X Ceil(1/2*width) Ceil(1/2*height)
174 * 16X width Ceil(1/2*height)
176 * The text "with upper left co-ordinate to coincide with actual
177 * rectangle being cleared" is a little confusing--it seems to imply
178 * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
179 * feed the pipeline using the rectangle (x,y) to
180 * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
181 * the number of samples. Experiments indicate that this is not
182 * quite correct; actually, what the hardware appears to do is to
183 * align whatever rectangle is sent down the pipeline to the nearest
184 * multiple of 2x2 blocks, and then scale it up by a factor of N
185 * horizontally and 2 vertically. So the resulting alignment is 4
186 * vertically and either 4 or 16 horizontally, and the scaledown
187 * factor is 2 vertically and either 2 or 8 horizontally.
189 switch (aux_surf
->format
) {
190 case ISL_FORMAT_MCS_2X
:
191 case ISL_FORMAT_MCS_4X
:
194 case ISL_FORMAT_MCS_8X
:
197 case ISL_FORMAT_MCS_16X
:
201 unreachable("Unexpected MCS format for fast clear");
204 x_align
= x_scaledown
* 2;
205 y_align
= y_scaledown
* 2;
208 *x0
= ROUND_DOWN_TO(*x0
, x_align
) / x_scaledown
;
209 *y0
= ROUND_DOWN_TO(*y0
, y_align
) / y_scaledown
;
210 *x1
= ALIGN(*x1
, x_align
) / x_scaledown
;
211 *y1
= ALIGN(*y1
, y_align
) / y_scaledown
;
215 blorp_fast_clear(struct blorp_batch
*batch
,
216 const struct blorp_surf
*surf
, enum isl_format format
,
217 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
218 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
220 struct blorp_params params
;
221 blorp_params_init(¶ms
);
222 params
.num_layers
= num_layers
;
229 memset(¶ms
.wm_inputs
, 0xff, 4*sizeof(float));
230 params
.fast_clear_op
= BLORP_FAST_CLEAR_OP_CLEAR
;
232 get_fast_clear_rect(batch
->blorp
->isl_dev
, surf
->aux_surf
,
233 ¶ms
.x0
, ¶ms
.y0
, ¶ms
.x1
, ¶ms
.y1
);
235 blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, true);
237 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
238 start_layer
, format
, true);
239 params
.num_samples
= params
.dst
.surf
.samples
;
241 batch
->blorp
->exec(batch
, ¶ms
);
246 blorp_clear(struct blorp_batch
*batch
,
247 const struct blorp_surf
*surf
,
248 enum isl_format format
, struct isl_swizzle swizzle
,
249 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
250 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
251 union isl_color_value clear_color
,
252 const bool color_write_disable
[4])
254 struct blorp_params params
;
255 blorp_params_init(¶ms
);
262 if (format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
263 clear_color
.u32
[0] = float3_to_rgb9e5(clear_color
.f32
);
264 format
= ISL_FORMAT_R32_UINT
;
267 memcpy(¶ms
.wm_inputs
, clear_color
.f32
, sizeof(float) * 4);
269 bool use_simd16_replicated_data
= true;
271 /* From the SNB PRM (Vol4_Part1):
273 * "Replicated data (Message Type = 111) is only supported when
274 * accessing tiled memory. Using this Message Type to access linear
275 * (untiled) memory is UNDEFINED."
277 if (surf
->surf
->tiling
== ISL_TILING_LINEAR
)
278 use_simd16_replicated_data
= false;
280 /* Constant color writes ignore everyting in blend and color calculator
281 * state. This is not documented.
283 if (color_write_disable
) {
284 for (unsigned i
= 0; i
< 4; i
++) {
285 params
.color_write_disable
[i
] = color_write_disable
[i
];
286 if (color_write_disable
[i
])
287 use_simd16_replicated_data
= false;
291 blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
,
292 use_simd16_replicated_data
);
294 while (num_layers
> 0) {
295 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
296 start_layer
, format
, true);
297 params
.dst
.view
.swizzle
= swizzle
;
299 params
.num_samples
= params
.dst
.surf
.samples
;
301 /* We may be restricted on the number of layers we can bind at any one
302 * time. In particular, Sandy Bridge has a maximum number of layers of
303 * 512 but a maximum 3D texture size is much larger.
305 params
.num_layers
= MIN2(params
.dst
.view
.array_len
, num_layers
);
306 batch
->blorp
->exec(batch
, ¶ms
);
308 start_layer
+= params
.num_layers
;
309 num_layers
-= params
.num_layers
;
314 blorp_clear_depth_stencil(struct blorp_batch
*batch
,
315 const struct blorp_surf
*depth
,
316 const struct blorp_surf
*stencil
,
317 uint32_t level
, uint32_t start_layer
,
319 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
320 bool clear_depth
, float depth_value
,
321 uint8_t stencil_mask
, uint8_t stencil_value
)
323 struct blorp_params params
;
324 blorp_params_init(¶ms
);
331 while (num_layers
> 0) {
332 params
.num_layers
= num_layers
;
335 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
337 ISL_FORMAT_UNSUPPORTED
, true);
338 params
.stencil_mask
= stencil_mask
;
339 params
.stencil_ref
= stencil_value
;
341 params
.dst
.surf
.samples
= params
.stencil
.surf
.samples
;
342 params
.dst
.surf
.logical_level0_px
=
343 params
.stencil
.surf
.logical_level0_px
;
344 params
.dst
.view
= params
.depth
.view
;
346 params
.num_samples
= params
.stencil
.surf
.samples
;
348 /* We may be restricted on the number of layers we can bind at any
349 * one time. In particular, Sandy Bridge has a maximum number of
350 * layers of 512 but a maximum 3D texture size is much larger.
352 if (params
.stencil
.view
.array_len
< params
.num_layers
)
353 params
.num_layers
= params
.stencil
.view
.array_len
;
357 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
359 ISL_FORMAT_UNSUPPORTED
, true);
360 params
.z
= depth_value
;
361 params
.depth_format
=
362 isl_format_get_depth_format(depth
->surf
->format
, false);
364 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
365 params
.dst
.surf
.logical_level0_px
=
366 params
.depth
.surf
.logical_level0_px
;
367 params
.dst
.view
= params
.depth
.view
;
369 params
.num_samples
= params
.depth
.surf
.samples
;
371 /* We may be restricted on the number of layers we can bind at any
372 * one time. In particular, Sandy Bridge has a maximum number of
373 * layers of 512 but a maximum 3D texture size is much larger.
375 if (params
.depth
.view
.array_len
< params
.num_layers
)
376 params
.num_layers
= params
.depth
.view
.array_len
;
379 batch
->blorp
->exec(batch
, ¶ms
);
381 start_layer
+= params
.num_layers
;
382 num_layers
-= params
.num_layers
;
387 blorp_ccs_resolve(struct blorp_batch
*batch
,
388 struct blorp_surf
*surf
, enum isl_format format
)
390 struct blorp_params params
;
391 blorp_params_init(¶ms
);
393 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
,
394 0 /* level */, 0 /* layer */, format
, true);
396 /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
398 * A rectangle primitive must be scaled down by the following factors
399 * with respect to render target being resolved.
401 * The scaledown factors in the table that follows are related to the block
402 * size of the CCS format. For IVB and HSW, we divide by two, for BDW we
403 * multiply by 8 and 16. On Sky Lake, we multiply by 8.
405 const struct isl_format_layout
*aux_fmtl
=
406 isl_format_get_layout(params
.dst
.aux_surf
.format
);
407 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
409 unsigned x_scaledown
, y_scaledown
;
410 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 9) {
411 x_scaledown
= aux_fmtl
->bw
* 8;
412 y_scaledown
= aux_fmtl
->bh
* 8;
413 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
414 x_scaledown
= aux_fmtl
->bw
* 8;
415 y_scaledown
= aux_fmtl
->bh
* 16;
417 x_scaledown
= aux_fmtl
->bw
/ 2;
418 y_scaledown
= aux_fmtl
->bh
/ 2;
420 params
.x0
= params
.y0
= 0;
421 params
.x1
= params
.dst
.aux_surf
.logical_level0_px
.width
;
422 params
.y1
= params
.dst
.aux_surf
.logical_level0_px
.height
;
423 params
.x1
= ALIGN(params
.x1
, x_scaledown
) / x_scaledown
;
424 params
.y1
= ALIGN(params
.y1
, y_scaledown
) / y_scaledown
;
426 if (batch
->blorp
->isl_dev
->info
->gen
>= 9) {
427 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
)
428 params
.fast_clear_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
430 params
.fast_clear_op
= BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
432 /* Broadwell and earlier do not have a partial resolve */
433 params
.fast_clear_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
436 /* Note: there is no need to initialize push constants because it doesn't
437 * matter what data gets dispatched to the render target. However, we must
438 * ensure that the fragment shader delivers the data using the "replicated
442 blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, true);
444 batch
->blorp
->exec(batch
, ¶ms
);