2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/ralloc.h"
26 #include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
27 #include "util/format_rgb9e5.h"
28 #include "util/format_srgb.h"
30 #include "blorp_priv.h"
31 #include "compiler/brw_eu_defines.h"
33 #include "blorp_nir_builder.h"
35 #define FILE_DEBUG_FLAG DEBUG_BLORP
37 struct brw_blorp_const_color_prog_key
39 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_CLEAR */
40 bool use_simd16_replicated_data
;
41 bool clear_rgb_as_red
;
46 blorp_params_get_clear_kernel(struct blorp_batch
*batch
,
47 struct blorp_params
*params
,
48 bool use_replicated_data
,
49 bool clear_rgb_as_red
)
51 struct blorp_context
*blorp
= batch
->blorp
;
53 const struct brw_blorp_const_color_prog_key blorp_key
= {
54 .shader_type
= BLORP_SHADER_TYPE_CLEAR
,
55 .use_simd16_replicated_data
= use_replicated_data
,
56 .clear_rgb_as_red
= clear_rgb_as_red
,
59 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
60 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
63 void *mem_ctx
= ralloc_context(NULL
);
66 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, "BLORP-clear");
68 nir_variable
*v_color
=
69 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
70 nir_ssa_def
*color
= nir_load_var(&b
, v_color
);
72 if (clear_rgb_as_red
) {
73 nir_ssa_def
*pos
= nir_f2i32(&b
, nir_load_frag_coord(&b
));
74 nir_ssa_def
*comp
= nir_umod(&b
, nir_channel(&b
, pos
, 0),
76 nir_ssa_def
*color_component
=
77 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
78 nir_channel(&b
, color
, 0),
79 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
80 nir_channel(&b
, color
, 1),
81 nir_channel(&b
, color
, 2)));
83 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
84 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
87 nir_variable
*frag_color
= nir_variable_create(b
.shader
, nir_var_shader_out
,
90 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
91 nir_store_var(&b
, frag_color
, color
, 0xf);
93 struct brw_wm_prog_key wm_key
;
94 brw_blorp_init_wm_prog_key(&wm_key
);
96 struct brw_wm_prog_data prog_data
;
97 const unsigned *program
=
98 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, use_replicated_data
,
102 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
103 program
, prog_data
.base
.program_size
,
104 &prog_data
.base
, sizeof(prog_data
),
105 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
107 ralloc_free(mem_ctx
);
111 struct layer_offset_vs_key
{
112 enum blorp_shader_type shader_type
;
116 /* In the case of doing attachment clears, we are using a surface state that
117 * is handed to us so we can't set (and don't even know) the base array layer.
118 * In order to do a layered clear in this scenario, we need some way of adding
119 * the base array layer to the instance id. Unfortunately, our hardware has
120 * no real concept of "base instance", so we have to do it manually in a
124 blorp_params_get_layer_offset_vs(struct blorp_batch
*batch
,
125 struct blorp_params
*params
)
127 struct blorp_context
*blorp
= batch
->blorp
;
128 struct layer_offset_vs_key blorp_key
= {
129 .shader_type
= BLORP_SHADER_TYPE_LAYER_OFFSET_VS
,
132 if (params
->wm_prog_data
)
133 blorp_key
.num_inputs
= params
->wm_prog_data
->num_varying_inputs
;
135 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
136 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
))
139 void *mem_ctx
= ralloc_context(NULL
);
142 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_VERTEX
, "BLORP-layer-offset-vs");
144 const struct glsl_type
*uvec4_type
= glsl_vector_type(GLSL_TYPE_UINT
, 4);
146 /* First we deal with the header which has instance and base instance */
147 nir_variable
*a_header
= nir_variable_create(b
.shader
, nir_var_shader_in
,
148 uvec4_type
, "header");
149 a_header
->data
.location
= VERT_ATTRIB_GENERIC0
;
151 nir_variable
*v_layer
= nir_variable_create(b
.shader
, nir_var_shader_out
,
152 glsl_int_type(), "layer_id");
153 v_layer
->data
.location
= VARYING_SLOT_LAYER
;
155 /* Compute the layer id */
156 nir_ssa_def
*header
= nir_load_var(&b
, a_header
);
157 nir_ssa_def
*base_layer
= nir_channel(&b
, header
, 0);
158 nir_ssa_def
*instance
= nir_channel(&b
, header
, 1);
159 nir_store_var(&b
, v_layer
, nir_iadd(&b
, instance
, base_layer
), 0x1);
161 /* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
162 nir_variable
*a_vertex
= nir_variable_create(b
.shader
, nir_var_shader_in
,
163 glsl_vec4_type(), "a_vertex");
164 a_vertex
->data
.location
= VERT_ATTRIB_GENERIC1
;
166 nir_variable
*v_pos
= nir_variable_create(b
.shader
, nir_var_shader_out
,
167 glsl_vec4_type(), "v_pos");
168 v_pos
->data
.location
= VARYING_SLOT_POS
;
170 nir_copy_var(&b
, v_pos
, a_vertex
);
172 /* Then we copy everything else */
173 for (unsigned i
= 0; i
< blorp_key
.num_inputs
; i
++) {
174 nir_variable
*a_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
175 uvec4_type
, "input");
176 a_in
->data
.location
= VERT_ATTRIB_GENERIC2
+ i
;
178 nir_variable
*v_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
179 uvec4_type
, "output");
180 v_out
->data
.location
= VARYING_SLOT_VAR0
+ i
;
182 nir_copy_var(&b
, v_out
, a_in
);
185 struct brw_vs_prog_data vs_prog_data
;
186 memset(&vs_prog_data
, 0, sizeof(vs_prog_data
));
188 const unsigned *program
=
189 blorp_compile_vs(blorp
, mem_ctx
, b
.shader
, &vs_prog_data
);
192 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
193 program
, vs_prog_data
.base
.base
.program_size
,
194 &vs_prog_data
.base
.base
, sizeof(vs_prog_data
),
195 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
);
197 ralloc_free(mem_ctx
);
201 /* The x0, y0, x1, and y1 parameters must already be populated with the render
202 * area of the framebuffer to be cleared.
205 get_fast_clear_rect(const struct isl_device
*dev
,
206 const struct isl_surf
*aux_surf
,
207 unsigned *x0
, unsigned *y0
,
208 unsigned *x1
, unsigned *y1
)
210 unsigned int x_align
, y_align
;
211 unsigned int x_scaledown
, y_scaledown
;
213 /* Only single sampled surfaces need to (and actually can) be resolved. */
214 if (aux_surf
->usage
== ISL_SURF_USAGE_CCS_BIT
) {
215 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
216 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
218 * Clear pass must have a clear rectangle that must follow
219 * alignment rules in terms of pixels and lines as shown in the
220 * table below. Further, the clear-rectangle height and width
221 * must be multiple of the following dimensions. If the height
222 * and width of the render target being cleared do not meet these
223 * requirements, an MCS buffer can be created such that it
224 * follows the requirement and covers the RT.
226 * The alignment size in the table that follows is related to the
227 * alignment size that is baked into the CCS surface format but with X
228 * alignment multiplied by 16 and Y alignment multiplied by 32.
230 x_align
= isl_format_get_layout(aux_surf
->format
)->bw
;
231 y_align
= isl_format_get_layout(aux_surf
->format
)->bh
;
235 /* SKL+ line alignment requirement for Y-tiled are half those of the prior
238 if (dev
->info
->gen
>= 9)
243 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
244 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
246 * In order to optimize the performance MCS buffer (when bound to
247 * 1X RT) clear similarly to MCS buffer clear for MSRT case,
248 * clear rect is required to be scaled by the following factors
249 * in the horizontal and vertical directions:
251 * The X and Y scale down factors in the table that follows are each
252 * equal to half the alignment value computed above.
254 x_scaledown
= x_align
/ 2;
255 y_scaledown
= y_align
/ 2;
257 if (ISL_DEV_IS_HASWELL(dev
)) {
258 /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
259 * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
260 * Clear of Non-MultiSampled Render Target Restrictions":
262 * Clear rectangle must be aligned to two times the number of
263 * pixels in the table shown below due to 16x16 hashing across the
266 * This restriction is only documented to exist on HSW GT3 but
267 * empirical evidence suggests that it's also needed GT2.
273 assert(aux_surf
->usage
== ISL_SURF_USAGE_MCS_BIT
);
275 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
276 * Target(s)", beneath the "MSAA Compression" bullet (p326):
278 * Clear pass for this case requires that scaled down primitive
279 * is sent down with upper left co-ordinate to coincide with
280 * actual rectangle being cleared. For MSAA, clear rectangle’s
281 * height and width need to as show in the following table in
282 * terms of (width,height) of the RT.
284 * MSAA Width of Clear Rect Height of Clear Rect
285 * 2X Ceil(1/8*width) Ceil(1/2*height)
286 * 4X Ceil(1/8*width) Ceil(1/2*height)
287 * 8X Ceil(1/2*width) Ceil(1/2*height)
288 * 16X width Ceil(1/2*height)
290 * The text "with upper left co-ordinate to coincide with actual
291 * rectangle being cleared" is a little confusing--it seems to imply
292 * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
293 * feed the pipeline using the rectangle (x,y) to
294 * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
295 * the number of samples. Experiments indicate that this is not
296 * quite correct; actually, what the hardware appears to do is to
297 * align whatever rectangle is sent down the pipeline to the nearest
298 * multiple of 2x2 blocks, and then scale it up by a factor of N
299 * horizontally and 2 vertically. So the resulting alignment is 4
300 * vertically and either 4 or 16 horizontally, and the scaledown
301 * factor is 2 vertically and either 2 or 8 horizontally.
303 switch (aux_surf
->format
) {
304 case ISL_FORMAT_MCS_2X
:
305 case ISL_FORMAT_MCS_4X
:
308 case ISL_FORMAT_MCS_8X
:
311 case ISL_FORMAT_MCS_16X
:
315 unreachable("Unexpected MCS format for fast clear");
318 x_align
= x_scaledown
* 2;
319 y_align
= y_scaledown
* 2;
322 *x0
= ROUND_DOWN_TO(*x0
, x_align
) / x_scaledown
;
323 *y0
= ROUND_DOWN_TO(*y0
, y_align
) / y_scaledown
;
324 *x1
= ALIGN(*x1
, x_align
) / x_scaledown
;
325 *y1
= ALIGN(*y1
, y_align
) / y_scaledown
;
329 blorp_fast_clear(struct blorp_batch
*batch
,
330 const struct blorp_surf
*surf
, enum isl_format format
,
331 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
332 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
334 /* Ensure that all layers undergoing the clear have an auxiliary buffer. */
335 assert(start_layer
+ num_layers
<=
336 MAX2(surf
->aux_surf
->logical_level0_px
.depth
>> level
,
337 surf
->aux_surf
->logical_level0_px
.array_len
));
339 struct blorp_params params
;
340 blorp_params_init(¶ms
);
341 params
.num_layers
= num_layers
;
348 memset(¶ms
.wm_inputs
.clear_color
, 0xff, 4*sizeof(float));
349 params
.fast_clear_op
= ISL_AUX_OP_FAST_CLEAR
;
351 get_fast_clear_rect(batch
->blorp
->isl_dev
, surf
->aux_surf
,
352 ¶ms
.x0
, ¶ms
.y0
, ¶ms
.x1
, ¶ms
.y1
);
354 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
357 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
358 start_layer
, format
, true);
359 params
.num_samples
= params
.dst
.surf
.samples
;
361 batch
->blorp
->exec(batch
, ¶ms
);
364 union isl_color_value
365 swizzle_color_value(union isl_color_value src
, struct isl_swizzle swizzle
)
367 union isl_color_value dst
= { .u32
= { 0, } };
369 /* We assign colors in ABGR order so that the first one will be taken in
370 * RGBA precedence order. According to the PRM docs for shader channel
371 * select, this matches Haswell hardware behavior.
373 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
374 dst
.u32
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[3];
375 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
376 dst
.u32
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[2];
377 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
378 dst
.u32
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[1];
379 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
380 dst
.u32
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[0];
386 blorp_clear(struct blorp_batch
*batch
,
387 const struct blorp_surf
*surf
,
388 enum isl_format format
, struct isl_swizzle swizzle
,
389 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
390 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
391 union isl_color_value clear_color
,
392 const bool color_write_disable
[4])
394 struct blorp_params params
;
395 blorp_params_init(¶ms
);
397 /* Manually apply the clear destination swizzle. This way swizzled clears
398 * will work for swizzles which we can't normally use for rendering and it
399 * also ensures that they work on pre-Haswell hardware which can't swizlle
402 clear_color
= swizzle_color_value(clear_color
, swizzle
);
403 swizzle
= ISL_SWIZZLE_IDENTITY
;
405 bool clear_rgb_as_red
= false;
406 if (format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
407 clear_color
.u32
[0] = float3_to_rgb9e5(clear_color
.f32
);
408 format
= ISL_FORMAT_R32_UINT
;
409 } else if (format
== ISL_FORMAT_L8_UNORM_SRGB
) {
410 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
411 format
= ISL_FORMAT_R8_UNORM
;
412 } else if (format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
413 /* Broadwell and earlier cannot render to this format so we need to work
414 * around it by swapping the colors around and using B4G4R4A4 instead.
416 const struct isl_swizzle ARGB
= ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
);
417 clear_color
= swizzle_color_value(clear_color
, ARGB
);
418 format
= ISL_FORMAT_B4G4R4A4_UNORM
;
419 } else if (isl_format_get_layout(format
)->bpb
% 3 == 0) {
420 clear_rgb_as_red
= true;
421 if (format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
) {
422 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
423 clear_color
.f32
[1] = util_format_linear_to_srgb_float(clear_color
.f32
[1]);
424 clear_color
.f32
[2] = util_format_linear_to_srgb_float(clear_color
.f32
[2]);
428 memcpy(¶ms
.wm_inputs
.clear_color
, clear_color
.f32
, sizeof(float) * 4);
430 bool use_simd16_replicated_data
= true;
432 /* From the SNB PRM (Vol4_Part1):
434 * "Replicated data (Message Type = 111) is only supported when
435 * accessing tiled memory. Using this Message Type to access linear
436 * (untiled) memory is UNDEFINED."
438 if (surf
->surf
->tiling
== ISL_TILING_LINEAR
)
439 use_simd16_replicated_data
= false;
441 /* Replicated clears don't work yet before gen6 */
442 if (batch
->blorp
->isl_dev
->info
->gen
< 6)
443 use_simd16_replicated_data
= false;
445 /* Constant color writes ignore everyting in blend and color calculator
446 * state. This is not documented.
448 if (color_write_disable
) {
449 for (unsigned i
= 0; i
< 4; i
++) {
450 params
.color_write_disable
[i
] = color_write_disable
[i
];
451 if (color_write_disable
[i
])
452 use_simd16_replicated_data
= false;
456 if (!blorp_params_get_clear_kernel(batch
, ¶ms
,
457 use_simd16_replicated_data
,
461 if (!blorp_ensure_sf_program(batch
, ¶ms
))
464 while (num_layers
> 0) {
465 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
466 start_layer
, format
, true);
467 params
.dst
.view
.swizzle
= swizzle
;
474 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
475 assert(params
.dst
.surf
.samples
== 1);
476 assert(num_layers
== 1);
477 params
.x0
+= params
.dst
.tile_x_sa
;
478 params
.y0
+= params
.dst
.tile_y_sa
;
479 params
.x1
+= params
.dst
.tile_x_sa
;
480 params
.y1
+= params
.dst
.tile_y_sa
;
483 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
484 * Convert them to a single slice on gen4.
486 if (batch
->blorp
->isl_dev
->info
->gen
== 4 &&
487 (params
.dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
)) {
488 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
.dst
);
491 if (clear_rgb_as_red
) {
492 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
.dst
);
497 if (isl_format_is_compressed(params
.dst
.surf
.format
)) {
498 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
499 NULL
, NULL
, NULL
, NULL
);
500 //&dst_x, &dst_y, &dst_w, &dst_h);
503 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
504 /* Either we're on gen4 where there is no multisampling or the
505 * surface is compressed which also implies no multisampling.
506 * Therefore, sa == px and we don't need to do a conversion.
508 assert(params
.dst
.surf
.samples
== 1);
509 params
.x0
+= params
.dst
.tile_x_sa
;
510 params
.y0
+= params
.dst
.tile_y_sa
;
511 params
.x1
+= params
.dst
.tile_x_sa
;
512 params
.y1
+= params
.dst
.tile_y_sa
;
515 params
.num_samples
= params
.dst
.surf
.samples
;
517 /* We may be restricted on the number of layers we can bind at any one
518 * time. In particular, Sandy Bridge has a maximum number of layers of
519 * 512 but a maximum 3D texture size is much larger.
521 params
.num_layers
= MIN2(params
.dst
.view
.array_len
, num_layers
);
523 const unsigned max_image_width
= 16 * 1024;
524 if (params
.dst
.surf
.logical_level0_px
.width
> max_image_width
) {
525 /* Clearing an RGB image as red multiplies the surface width by 3
526 * so it may now be too wide for the hardware surface limits. We
527 * have to break the clear up into pieces in order to clear wide
530 assert(clear_rgb_as_red
);
531 assert(params
.dst
.surf
.dim
== ISL_SURF_DIM_2D
);
532 assert(params
.dst
.surf
.tiling
== ISL_TILING_LINEAR
);
533 assert(params
.dst
.surf
.logical_level0_px
.depth
== 1);
534 assert(params
.dst
.surf
.logical_level0_px
.array_len
== 1);
535 assert(params
.dst
.surf
.levels
== 1);
536 assert(params
.dst
.surf
.samples
== 1);
537 assert(params
.dst
.tile_x_sa
== 0 || params
.dst
.tile_y_sa
== 0);
538 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
);
540 /* max_image_width rounded down to a multiple of 3 */
541 const unsigned max_fake_rgb_width
= (max_image_width
/ 3) * 3;
543 isl_format_get_layout(params
.dst
.surf
.format
)->bpb
/ 8;
545 params
.dst
.surf
.logical_level0_px
.width
= max_fake_rgb_width
;
546 params
.dst
.surf
.phys_level0_sa
.width
= max_fake_rgb_width
;
548 uint32_t orig_x0
= params
.x0
, orig_x1
= params
.x1
;
549 uint64_t orig_offset
= params
.dst
.addr
.offset
;
550 for (uint32_t x
= orig_x0
; x
< orig_x1
; x
+= max_fake_rgb_width
) {
551 /* Offset to the surface. It's easy because we're linear */
552 params
.dst
.addr
.offset
= orig_offset
+ x
* cpp
;
555 params
.x1
= MIN2(orig_x1
- x
, max_image_width
);
557 batch
->blorp
->exec(batch
, ¶ms
);
560 batch
->blorp
->exec(batch
, ¶ms
);
563 start_layer
+= params
.num_layers
;
564 num_layers
-= params
.num_layers
;
569 blorp_clear_depth_stencil(struct blorp_batch
*batch
,
570 const struct blorp_surf
*depth
,
571 const struct blorp_surf
*stencil
,
572 uint32_t level
, uint32_t start_layer
,
574 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
575 bool clear_depth
, float depth_value
,
576 uint8_t stencil_mask
, uint8_t stencil_value
)
578 struct blorp_params params
;
579 blorp_params_init(¶ms
);
586 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) == 6) {
587 /* For some reason, Sandy Bridge gets occlusion queries wrong if we
588 * don't have a shader. In particular, it records samples even though
589 * we disable statistics in 3DSTATE_WM. Give it the usual clear shader
590 * to work around the issue.
592 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, false, false))
596 while (num_layers
> 0) {
597 params
.num_layers
= num_layers
;
600 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
602 ISL_FORMAT_UNSUPPORTED
, true);
603 params
.stencil_mask
= stencil_mask
;
604 params
.stencil_ref
= stencil_value
;
606 params
.dst
.surf
.samples
= params
.stencil
.surf
.samples
;
607 params
.dst
.surf
.logical_level0_px
=
608 params
.stencil
.surf
.logical_level0_px
;
609 params
.dst
.view
= params
.depth
.view
;
611 params
.num_samples
= params
.stencil
.surf
.samples
;
613 /* We may be restricted on the number of layers we can bind at any
614 * one time. In particular, Sandy Bridge has a maximum number of
615 * layers of 512 but a maximum 3D texture size is much larger.
617 if (params
.stencil
.view
.array_len
< params
.num_layers
)
618 params
.num_layers
= params
.stencil
.view
.array_len
;
622 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
624 ISL_FORMAT_UNSUPPORTED
, true);
625 params
.z
= depth_value
;
626 params
.depth_format
=
627 isl_format_get_depth_format(depth
->surf
->format
, false);
629 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
630 params
.dst
.surf
.logical_level0_px
=
631 params
.depth
.surf
.logical_level0_px
;
632 params
.dst
.view
= params
.depth
.view
;
634 params
.num_samples
= params
.depth
.surf
.samples
;
636 /* We may be restricted on the number of layers we can bind at any
637 * one time. In particular, Sandy Bridge has a maximum number of
638 * layers of 512 but a maximum 3D texture size is much larger.
640 if (params
.depth
.view
.array_len
< params
.num_layers
)
641 params
.num_layers
= params
.depth
.view
.array_len
;
644 batch
->blorp
->exec(batch
, ¶ms
);
646 start_layer
+= params
.num_layers
;
647 num_layers
-= params
.num_layers
;
652 blorp_can_hiz_clear_depth(uint8_t gen
, enum isl_format format
,
653 uint32_t num_samples
,
654 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
656 /* This function currently doesn't support any gen prior to gen8 */
659 if (gen
== 8 && format
== ISL_FORMAT_R16_UNORM
) {
660 /* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample
661 * block with the following property: as the number of samples increases,
662 * the number of pixels representable by this block decreases by a factor
663 * of the sample dimensions. Sample dimensions scale following the MSAA
664 * interleaved pattern.
666 * Sample|Sample|Pixel
668 * ===================
675 * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
677 const struct isl_extent2d sa_block_dim
=
678 isl_get_interleaved_msaa_px_size_sa(num_samples
);
679 const uint8_t align_px_w
= 8 / sa_block_dim
.w
;
680 const uint8_t align_px_h
= 4 / sa_block_dim
.h
;
682 /* Fast depth clears clear an entire sample block at a time. As a result,
683 * the rectangle must be aligned to the dimensions of the encompassing
684 * pixel block for a successful operation.
686 * Fast clears can still work if the upper-left corner is aligned and the
687 * bottom-rigtht corner touches the edge of a depth buffer whose extent
688 * is unaligned. This is because each miplevel in the depth buffer is
689 * padded by the Pixel Dim (similar to a standard compressed texture).
690 * In this case, the clear rectangle could be padded by to match the full
691 * depth buffer extent but to support multiple clearing techniques, we
692 * chose to be unaware of the depth buffer's extent and thus don't handle
695 if (x0
% align_px_w
|| y0
% align_px_h
||
696 x1
% align_px_w
|| y1
% align_px_h
)
703 blorp_hiz_clear_depth_stencil(struct blorp_batch
*batch
,
704 const struct blorp_surf
*depth
,
705 const struct blorp_surf
*stencil
,
707 uint32_t start_layer
, uint32_t num_layers
,
708 uint32_t x0
, uint32_t y0
,
709 uint32_t x1
, uint32_t y1
,
710 bool clear_depth
, float depth_value
,
711 bool clear_stencil
, uint8_t stencil_value
)
713 struct blorp_params params
;
714 blorp_params_init(¶ms
);
716 /* This requires WM_HZ_OP which only exists on gen8+ */
717 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8);
719 params
.hiz_op
= ISL_AUX_OP_FAST_CLEAR
;
720 params
.num_layers
= 1;
727 for (uint32_t l
= 0; l
< num_layers
; l
++) {
728 const uint32_t layer
= start_layer
+ l
;
730 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
732 ISL_FORMAT_UNSUPPORTED
, true);
733 params
.stencil_mask
= 0xff;
734 params
.stencil_ref
= stencil_value
;
735 params
.num_samples
= params
.stencil
.surf
.samples
;
739 /* If we're clearing depth, we must have HiZ */
740 assert(depth
&& depth
->aux_usage
== ISL_AUX_USAGE_HIZ
);
742 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
744 ISL_FORMAT_UNSUPPORTED
, true);
745 params
.depth
.clear_color
.f32
[0] = depth_value
;
746 params
.depth_format
=
747 isl_format_get_depth_format(depth
->surf
->format
, false);
748 params
.num_samples
= params
.depth
.surf
.samples
;
751 batch
->blorp
->exec(batch
, ¶ms
);
755 /* Given a depth stencil attachment, this function performs a fast depth clear
756 * on a depth portion and a regular clear on the stencil portion. When
757 * performing a fast depth clear on the depth portion, the HiZ buffer is simply
758 * tagged as cleared so the depth clear value is not actually needed.
761 blorp_gen8_hiz_clear_attachments(struct blorp_batch
*batch
,
762 uint32_t num_samples
,
763 uint32_t x0
, uint32_t y0
,
764 uint32_t x1
, uint32_t y1
,
765 bool clear_depth
, bool clear_stencil
,
766 uint8_t stencil_value
)
768 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
770 struct blorp_params params
;
771 blorp_params_init(¶ms
);
772 params
.num_layers
= 1;
773 params
.hiz_op
= ISL_AUX_OP_FAST_CLEAR
;
778 params
.num_samples
= num_samples
;
779 params
.depth
.enabled
= clear_depth
;
780 params
.stencil
.enabled
= clear_stencil
;
781 params
.stencil_ref
= stencil_value
;
782 batch
->blorp
->exec(batch
, ¶ms
);
785 /** Clear active color/depth/stencili attachments
787 * This function performs a clear operation on the currently bound
788 * color/depth/stencil attachments. It is assumed that any information passed
789 * in here is valid, consistent, and in-bounds relative to the currently
790 * attached depth/stencil. The binding_table_offset parameter is the 32-bit
791 * offset relative to surface state base address where pre-baked binding table
792 * that we are to use lives. If clear_color is false, binding_table_offset
793 * must point to a binding table with one entry which is a valid null surface
794 * that matches the currently bound depth and stencil.
797 blorp_clear_attachments(struct blorp_batch
*batch
,
798 uint32_t binding_table_offset
,
799 enum isl_format depth_format
,
800 uint32_t num_samples
,
801 uint32_t start_layer
, uint32_t num_layers
,
802 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
803 bool clear_color
, union isl_color_value color_value
,
804 bool clear_depth
, float depth_value
,
805 uint8_t stencil_mask
, uint8_t stencil_value
)
807 struct blorp_params params
;
808 blorp_params_init(¶ms
);
810 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
817 params
.use_pre_baked_binding_table
= true;
818 params
.pre_baked_binding_table_offset
= binding_table_offset
;
820 params
.num_layers
= num_layers
;
821 params
.num_samples
= num_samples
;
824 params
.dst
.enabled
= true;
826 memcpy(¶ms
.wm_inputs
.clear_color
, color_value
.f32
, sizeof(float) * 4);
828 /* Unfortunately, without knowing whether or not our destination surface
829 * is tiled or not, we have to assume it may be linear. This means no
830 * SIMD16_REPDATA for us. :-(
832 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, false, false))
837 params
.depth
.enabled
= true;
839 params
.z
= depth_value
;
840 params
.depth_format
= isl_format_get_depth_format(depth_format
, false);
844 params
.stencil
.enabled
= true;
846 params
.stencil_mask
= stencil_mask
;
847 params
.stencil_ref
= stencil_value
;
850 if (!blorp_params_get_layer_offset_vs(batch
, ¶ms
))
853 params
.vs_inputs
.base_layer
= start_layer
;
855 batch
->blorp
->exec(batch
, ¶ms
);
859 blorp_ccs_resolve(struct blorp_batch
*batch
,
860 struct blorp_surf
*surf
, uint32_t level
,
861 uint32_t start_layer
, uint32_t num_layers
,
862 enum isl_format format
,
863 enum isl_aux_op resolve_op
)
865 struct blorp_params params
;
867 blorp_params_init(¶ms
);
868 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
,
869 level
, start_layer
, format
, true);
871 /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
873 * A rectangle primitive must be scaled down by the following factors
874 * with respect to render target being resolved.
876 * The scaledown factors in the table that follows are related to the block
877 * size of the CCS format. For IVB and HSW, we divide by two, for BDW we
878 * multiply by 8 and 16. On Sky Lake, we multiply by 8.
880 const struct isl_format_layout
*aux_fmtl
=
881 isl_format_get_layout(params
.dst
.aux_surf
.format
);
882 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
884 unsigned x_scaledown
, y_scaledown
;
885 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 9) {
886 x_scaledown
= aux_fmtl
->bw
* 8;
887 y_scaledown
= aux_fmtl
->bh
* 8;
888 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
889 x_scaledown
= aux_fmtl
->bw
* 8;
890 y_scaledown
= aux_fmtl
->bh
* 16;
892 x_scaledown
= aux_fmtl
->bw
/ 2;
893 y_scaledown
= aux_fmtl
->bh
/ 2;
895 params
.x0
= params
.y0
= 0;
896 params
.x1
= minify(params
.dst
.aux_surf
.logical_level0_px
.width
, level
);
897 params
.y1
= minify(params
.dst
.aux_surf
.logical_level0_px
.height
, level
);
898 params
.x1
= ALIGN(params
.x1
, x_scaledown
) / x_scaledown
;
899 params
.y1
= ALIGN(params
.y1
, y_scaledown
) / y_scaledown
;
901 if (batch
->blorp
->isl_dev
->info
->gen
>= 10) {
902 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
||
903 resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
||
904 resolve_op
== ISL_AUX_OP_AMBIGUATE
);
905 } else if (batch
->blorp
->isl_dev
->info
->gen
>= 9) {
906 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
||
907 resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
909 /* Broadwell and earlier do not have a partial resolve */
910 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
);
912 params
.fast_clear_op
= resolve_op
;
913 params
.num_layers
= num_layers
;
915 /* Note: there is no need to initialize push constants because it doesn't
916 * matter what data gets dispatched to the render target. However, we must
917 * ensure that the fragment shader delivers the data using the "replicated
921 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
924 batch
->blorp
->exec(batch
, ¶ms
);
928 blorp_nir_bit(nir_builder
*b
, nir_ssa_def
*src
, unsigned bit
)
930 return nir_iand(b
, nir_ushr(b
, src
, nir_imm_int(b
, bit
)),
934 struct blorp_mcs_partial_resolve_key
936 enum blorp_shader_type shader_type
;
937 bool indirect_clear_color
;
939 uint32_t num_samples
;
943 blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch
*batch
,
944 struct blorp_params
*params
)
946 struct blorp_context
*blorp
= batch
->blorp
;
947 const struct blorp_mcs_partial_resolve_key blorp_key
= {
948 .shader_type
= BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE
,
949 .indirect_clear_color
= params
->dst
.clear_color_addr
.buffer
!= NULL
,
950 .int_format
= isl_format_has_int_channel(params
->dst
.view
.format
),
951 .num_samples
= params
->num_samples
,
954 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
955 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
958 void *mem_ctx
= ralloc_context(NULL
);
961 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
,
962 "BLORP-mcs-partial-resolve");
964 nir_variable
*v_color
=
965 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
967 nir_variable
*frag_color
=
968 nir_variable_create(b
.shader
, nir_var_shader_out
,
969 glsl_vec4_type(), "gl_FragColor");
970 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
972 /* Do an MCS fetch and check if it is equal to the magic clear value */
974 blorp_nir_txf_ms_mcs(&b
, nir_f2i32(&b
, nir_load_frag_coord(&b
)),
975 nir_load_layer_id(&b
));
976 nir_ssa_def
*is_clear
=
977 blorp_nir_mcs_is_clear_color(&b
, mcs
, blorp_key
.num_samples
);
979 /* If we aren't the clear value, discard. */
980 nir_intrinsic_instr
*discard
=
981 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_discard_if
);
982 discard
->src
[0] = nir_src_for_ssa(nir_inot(&b
, is_clear
));
983 nir_builder_instr_insert(&b
, &discard
->instr
);
985 nir_ssa_def
*clear_color
= nir_load_var(&b
, v_color
);
986 if (blorp_key
.indirect_clear_color
&& blorp
->isl_dev
->info
->gen
<= 8) {
987 /* Gen7-8 clear colors are stored as single 0/1 bits */
988 clear_color
= nir_vec4(&b
, blorp_nir_bit(&b
, clear_color
, 31),
989 blorp_nir_bit(&b
, clear_color
, 30),
990 blorp_nir_bit(&b
, clear_color
, 29),
991 blorp_nir_bit(&b
, clear_color
, 28));
993 if (!blorp_key
.int_format
)
994 clear_color
= nir_i2f32(&b
, clear_color
);
996 nir_store_var(&b
, frag_color
, clear_color
, 0xf);
998 struct brw_wm_prog_key wm_key
;
999 brw_blorp_init_wm_prog_key(&wm_key
);
1000 wm_key
.base
.tex
.compressed_multisample_layout_mask
= 1;
1001 wm_key
.base
.tex
.msaa_16
= blorp_key
.num_samples
== 16;
1002 wm_key
.multisample_fbo
= true;
1004 struct brw_wm_prog_data prog_data
;
1005 const unsigned *program
=
1006 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, false,
1010 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
1011 program
, prog_data
.base
.program_size
,
1012 &prog_data
.base
, sizeof(prog_data
),
1013 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1015 ralloc_free(mem_ctx
);
1020 blorp_mcs_partial_resolve(struct blorp_batch
*batch
,
1021 struct blorp_surf
*surf
,
1022 enum isl_format format
,
1023 uint32_t start_layer
, uint32_t num_layers
)
1025 struct blorp_params params
;
1026 blorp_params_init(¶ms
);
1028 assert(batch
->blorp
->isl_dev
->info
->gen
>= 7);
1032 params
.x1
= surf
->surf
->logical_level0_px
.width
;
1033 params
.y1
= surf
->surf
->logical_level0_px
.height
;
1035 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, surf
, 0,
1036 start_layer
, format
, false);
1037 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, 0,
1038 start_layer
, format
, true);
1040 params
.num_samples
= params
.dst
.surf
.samples
;
1041 params
.num_layers
= num_layers
;
1042 params
.dst_clear_color_as_input
= surf
->clear_color_addr
.buffer
!= NULL
;
1044 memcpy(¶ms
.wm_inputs
.clear_color
,
1045 surf
->clear_color
.f32
, sizeof(float) * 4);
1047 if (!blorp_params_get_mcs_partial_resolve_kernel(batch
, ¶ms
))
1050 batch
->blorp
->exec(batch
, ¶ms
);
1053 /** Clear a CCS to the "uncompressed" state
1055 * This pass is the CCS equivalent of a "HiZ resolve". It sets the CCS values
1056 * for a given layer/level of a surface to 0x0 which is the "uncompressed"
1057 * state which tells the sampler to go look at the main surface.
1060 blorp_ccs_ambiguate(struct blorp_batch
*batch
,
1061 struct blorp_surf
*surf
,
1062 uint32_t level
, uint32_t layer
)
1064 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 10) {
1065 /* On gen10 and above, we have a hardware resolve op for this */
1066 return blorp_ccs_resolve(batch
, surf
, level
, layer
, 1,
1067 surf
->surf
->format
, ISL_AUX_OP_AMBIGUATE
);
1070 struct blorp_params params
;
1071 blorp_params_init(¶ms
);
1073 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 7);
1075 const struct isl_format_layout
*aux_fmtl
=
1076 isl_format_get_layout(surf
->aux_surf
->format
);
1077 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
1079 params
.dst
= (struct brw_blorp_surface_info
) {
1081 .addr
= surf
->aux_addr
,
1083 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1084 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
1086 .base_array_layer
= 0,
1089 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1094 if (surf
->surf
->dim
== ISL_SURF_DIM_3D
) {
1099 uint32_t offset_B
, x_offset_el
, y_offset_el
;
1100 isl_surf_get_image_offset_el(surf
->aux_surf
, level
, layer
, z
,
1101 &x_offset_el
, &y_offset_el
);
1102 isl_tiling_get_intratile_offset_el(surf
->aux_surf
->tiling
, aux_fmtl
->bpb
,
1103 surf
->aux_surf
->row_pitch_B
,
1104 x_offset_el
, y_offset_el
,
1105 &offset_B
, &x_offset_el
, &y_offset_el
);
1106 params
.dst
.addr
.offset
+= offset_B
;
1108 const uint32_t width_px
=
1109 minify(surf
->aux_surf
->logical_level0_px
.width
, level
);
1110 const uint32_t height_px
=
1111 minify(surf
->aux_surf
->logical_level0_px
.height
, level
);
1112 const uint32_t width_el
= DIV_ROUND_UP(width_px
, aux_fmtl
->bw
);
1113 const uint32_t height_el
= DIV_ROUND_UP(height_px
, aux_fmtl
->bh
);
1115 struct isl_tile_info ccs_tile_info
;
1116 isl_surf_get_tile_info(surf
->aux_surf
, &ccs_tile_info
);
1118 /* We're going to map it as a regular RGBA32_UINT surface. We need to
1119 * downscale a good deal. We start by computing the area on the CCS to
1120 * clear in units of Y-tiled cache lines.
1122 uint32_t x_offset_cl
, y_offset_cl
, width_cl
, height_cl
;
1123 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
1124 /* From the Sky Lake PRM Vol. 12 in the section on planes:
1126 * "The Color Control Surface (CCS) contains the compression status
1127 * of the cache-line pairs. The compression state of the cache-line
1128 * pair is specified by 2 bits in the CCS. Each CCS cache-line
1129 * represents an area on the main surface of 16x16 sets of 128 byte
1130 * Y-tiled cache-line-pairs. CCS is always Y tiled."
1132 * Each 2-bit surface element in the CCS corresponds to a single
1133 * cache-line pair in the main surface. This means that 16x16 el block
1134 * in the CCS maps to a Y-tiled cache line. Fortunately, CCS layouts
1135 * are calculated with a very large alignment so we can round up to a
1136 * whole cache line without worrying about overdraw.
1139 /* On Broadwell and above, a CCS tile is the same as a Y tile when
1140 * viewed at the cache-line granularity. Fortunately, the horizontal
1141 * and vertical alignment requirements of the CCS are such that we can
1142 * align to an entire cache line without worrying about crossing over
1143 * from one LOD to another.
1145 const uint32_t x_el_per_cl
= ccs_tile_info
.logical_extent_el
.w
/ 8;
1146 const uint32_t y_el_per_cl
= ccs_tile_info
.logical_extent_el
.h
/ 8;
1147 assert(surf
->aux_surf
->image_alignment_el
.w
% x_el_per_cl
== 0);
1148 assert(surf
->aux_surf
->image_alignment_el
.h
% y_el_per_cl
== 0);
1150 assert(x_offset_el
% x_el_per_cl
== 0);
1151 assert(y_offset_el
% y_el_per_cl
== 0);
1152 x_offset_cl
= x_offset_el
/ x_el_per_cl
;
1153 y_offset_cl
= y_offset_el
/ y_el_per_cl
;
1154 width_cl
= DIV_ROUND_UP(width_el
, x_el_per_cl
);
1155 height_cl
= DIV_ROUND_UP(height_el
, y_el_per_cl
);
1157 /* On gen7, the CCS tiling is not so nice. However, there we are
1158 * guaranteed that we only have a single level and slice so we don't
1159 * have to worry about it and can just align to a whole tile.
1161 assert(surf
->aux_surf
->logical_level0_px
.depth
== 1);
1162 assert(surf
->aux_surf
->logical_level0_px
.array_len
== 1);
1163 assert(x_offset_el
== 0 && y_offset_el
== 0);
1164 const uint32_t width_tl
=
1165 DIV_ROUND_UP(width_el
, ccs_tile_info
.logical_extent_el
.w
);
1166 const uint32_t height_tl
=
1167 DIV_ROUND_UP(height_el
, ccs_tile_info
.logical_extent_el
.h
);
1170 width_cl
= width_tl
* 8;
1171 height_cl
= height_tl
* 8;
1174 /* We're going to use a RGBA32 format so as to write data as quickly as
1175 * possible. A y-tiled cache line will then be 1x4 px.
1177 const uint32_t x_offset_rgba_px
= x_offset_cl
;
1178 const uint32_t y_offset_rgba_px
= y_offset_cl
* 4;
1179 const uint32_t width_rgba_px
= width_cl
;
1180 const uint32_t height_rgba_px
= height_cl
* 4;
1182 MAYBE_UNUSED
bool ok
=
1183 isl_surf_init(batch
->blorp
->isl_dev
, ¶ms
.dst
.surf
,
1184 .dim
= ISL_SURF_DIM_2D
,
1185 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
1186 .width
= width_rgba_px
+ x_offset_rgba_px
,
1187 .height
= height_rgba_px
+ y_offset_rgba_px
,
1192 .row_pitch_B
= surf
->aux_surf
->row_pitch_B
,
1193 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1194 .tiling_flags
= ISL_TILING_Y0_BIT
);
1197 params
.x0
= x_offset_rgba_px
;
1198 params
.y0
= y_offset_rgba_px
;
1199 params
.x1
= x_offset_rgba_px
+ width_rgba_px
;
1200 params
.y1
= y_offset_rgba_px
+ height_rgba_px
;
1202 /* A CCS value of 0 means "uncompressed." */
1203 memset(¶ms
.wm_inputs
.clear_color
, 0,
1204 sizeof(params
.wm_inputs
.clear_color
));
1206 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
1209 batch
->blorp
->exec(batch
, ¶ms
);