2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/ralloc.h"
26 #include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
27 #include "util/format_rgb9e5.h"
29 #include "blorp_priv.h"
30 #include "brw_defines.h"
32 #include "compiler/nir/nir_builder.h"
34 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 struct brw_blorp_const_color_prog_key
38 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_CLEAR */
39 bool use_simd16_replicated_data
;
44 blorp_params_get_clear_kernel(struct blorp_context
*blorp
,
45 struct blorp_params
*params
,
46 bool use_replicated_data
)
48 const struct brw_blorp_const_color_prog_key blorp_key
= {
49 .shader_type
= BLORP_SHADER_TYPE_CLEAR
,
50 .use_simd16_replicated_data
= use_replicated_data
,
53 if (blorp
->lookup_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
54 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
57 void *mem_ctx
= ralloc_context(NULL
);
60 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
61 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, "BLORP-clear");
63 nir_variable
*v_color
=
64 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
66 nir_variable
*frag_color
= nir_variable_create(b
.shader
, nir_var_shader_out
,
69 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
71 nir_copy_var(&b
, frag_color
, v_color
);
73 struct brw_wm_prog_key wm_key
;
74 brw_blorp_init_wm_prog_key(&wm_key
);
76 struct brw_wm_prog_data prog_data
;
77 unsigned program_size
;
78 const unsigned *program
=
79 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, use_replicated_data
,
80 &prog_data
, &program_size
);
82 blorp
->upload_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
83 program
, program_size
,
84 &prog_data
.base
, sizeof(prog_data
),
85 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
90 struct layer_offset_vs_key
{
91 enum blorp_shader_type shader_type
;
95 /* In the case of doing attachment clears, we are using a surface state that
96 * is handed to us so we can't set (and don't even know) the base array layer.
97 * In order to do a layered clear in this scenario, we need some way of adding
98 * the base array layer to the instance id. Unfortunately, our hardware has
99 * no real concept of "base instance", so we have to do it manually in a
103 blorp_params_get_layer_offset_vs(struct blorp_context
*blorp
,
104 struct blorp_params
*params
)
106 struct layer_offset_vs_key blorp_key
= {
107 .shader_type
= BLORP_SHADER_TYPE_LAYER_OFFSET_VS
,
110 if (params
->wm_prog_data
)
111 blorp_key
.num_inputs
= params
->wm_prog_data
->num_varying_inputs
;
113 if (blorp
->lookup_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
114 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
))
117 void *mem_ctx
= ralloc_context(NULL
);
120 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_VERTEX
, NULL
);
121 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, "BLORP-layer-offset-vs");
123 const struct glsl_type
*uvec4_type
= glsl_vector_type(GLSL_TYPE_UINT
, 4);
125 /* First we deal with the header which has instance and base instance */
126 nir_variable
*a_header
= nir_variable_create(b
.shader
, nir_var_shader_in
,
127 uvec4_type
, "header");
128 a_header
->data
.location
= VERT_ATTRIB_GENERIC0
;
130 nir_variable
*v_layer
= nir_variable_create(b
.shader
, nir_var_shader_out
,
131 glsl_int_type(), "layer_id");
132 v_layer
->data
.location
= VARYING_SLOT_LAYER
;
134 /* Compute the layer id */
135 nir_ssa_def
*header
= nir_load_var(&b
, a_header
);
136 nir_ssa_def
*base_layer
= nir_channel(&b
, header
, 0);
137 nir_ssa_def
*instance
= nir_channel(&b
, header
, 1);
138 nir_store_var(&b
, v_layer
, nir_iadd(&b
, instance
, base_layer
), 0x1);
140 /* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
141 nir_variable
*a_vertex
= nir_variable_create(b
.shader
, nir_var_shader_in
,
142 glsl_vec4_type(), "a_vertex");
143 a_vertex
->data
.location
= VERT_ATTRIB_GENERIC1
;
145 nir_variable
*v_pos
= nir_variable_create(b
.shader
, nir_var_shader_out
,
146 glsl_vec4_type(), "v_pos");
147 v_pos
->data
.location
= VARYING_SLOT_POS
;
149 nir_copy_var(&b
, v_pos
, a_vertex
);
151 /* Then we copy everything else */
152 for (unsigned i
= 0; i
< blorp_key
.num_inputs
; i
++) {
153 nir_variable
*a_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
154 uvec4_type
, "input");
155 a_in
->data
.location
= VERT_ATTRIB_GENERIC2
+ i
;
157 nir_variable
*v_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
158 uvec4_type
, "output");
159 v_out
->data
.location
= VARYING_SLOT_VAR0
+ i
;
161 nir_copy_var(&b
, v_out
, a_in
);
164 struct brw_vs_prog_data vs_prog_data
;
165 memset(&vs_prog_data
, 0, sizeof(vs_prog_data
));
167 unsigned program_size
;
168 const unsigned *program
=
169 blorp_compile_vs(blorp
, mem_ctx
, b
.shader
, &vs_prog_data
, &program_size
);
171 blorp
->upload_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
172 program
, program_size
,
173 &vs_prog_data
.base
.base
, sizeof(vs_prog_data
),
174 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
);
176 ralloc_free(mem_ctx
);
179 /* The x0, y0, x1, and y1 parameters must already be populated with the render
180 * area of the framebuffer to be cleared.
183 get_fast_clear_rect(const struct isl_device
*dev
,
184 const struct isl_surf
*aux_surf
,
185 unsigned *x0
, unsigned *y0
,
186 unsigned *x1
, unsigned *y1
)
188 unsigned int x_align
, y_align
;
189 unsigned int x_scaledown
, y_scaledown
;
191 /* Only single sampled surfaces need to (and actually can) be resolved. */
192 if (aux_surf
->usage
== ISL_SURF_USAGE_CCS_BIT
) {
193 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
194 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
196 * Clear pass must have a clear rectangle that must follow
197 * alignment rules in terms of pixels and lines as shown in the
198 * table below. Further, the clear-rectangle height and width
199 * must be multiple of the following dimensions. If the height
200 * and width of the render target being cleared do not meet these
201 * requirements, an MCS buffer can be created such that it
202 * follows the requirement and covers the RT.
204 * The alignment size in the table that follows is related to the
205 * alignment size that is baked into the CCS surface format but with X
206 * alignment multiplied by 16 and Y alignment multiplied by 32.
208 x_align
= isl_format_get_layout(aux_surf
->format
)->bw
;
209 y_align
= isl_format_get_layout(aux_surf
->format
)->bh
;
213 /* SKL+ line alignment requirement for Y-tiled are half those of the prior
216 if (dev
->info
->gen
>= 9)
221 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
222 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
224 * In order to optimize the performance MCS buffer (when bound to
225 * 1X RT) clear similarly to MCS buffer clear for MSRT case,
226 * clear rect is required to be scaled by the following factors
227 * in the horizontal and vertical directions:
229 * The X and Y scale down factors in the table that follows are each
230 * equal to half the alignment value computed above.
232 x_scaledown
= x_align
/ 2;
233 y_scaledown
= y_align
/ 2;
235 /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
236 * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
237 * Clear of Non-MultiSampled Render Target Restrictions":
239 * Clear rectangle must be aligned to two times the number of
240 * pixels in the table shown below due to 16x16 hashing across the
246 assert(aux_surf
->usage
== ISL_SURF_USAGE_MCS_BIT
);
248 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
249 * Target(s)", beneath the "MSAA Compression" bullet (p326):
251 * Clear pass for this case requires that scaled down primitive
252 * is sent down with upper left co-ordinate to coincide with
253 * actual rectangle being cleared. For MSAA, clear rectangle’s
254 * height and width need to as show in the following table in
255 * terms of (width,height) of the RT.
257 * MSAA Width of Clear Rect Height of Clear Rect
258 * 2X Ceil(1/8*width) Ceil(1/2*height)
259 * 4X Ceil(1/8*width) Ceil(1/2*height)
260 * 8X Ceil(1/2*width) Ceil(1/2*height)
261 * 16X width Ceil(1/2*height)
263 * The text "with upper left co-ordinate to coincide with actual
264 * rectangle being cleared" is a little confusing--it seems to imply
265 * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
266 * feed the pipeline using the rectangle (x,y) to
267 * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
268 * the number of samples. Experiments indicate that this is not
269 * quite correct; actually, what the hardware appears to do is to
270 * align whatever rectangle is sent down the pipeline to the nearest
271 * multiple of 2x2 blocks, and then scale it up by a factor of N
272 * horizontally and 2 vertically. So the resulting alignment is 4
273 * vertically and either 4 or 16 horizontally, and the scaledown
274 * factor is 2 vertically and either 2 or 8 horizontally.
276 switch (aux_surf
->format
) {
277 case ISL_FORMAT_MCS_2X
:
278 case ISL_FORMAT_MCS_4X
:
281 case ISL_FORMAT_MCS_8X
:
284 case ISL_FORMAT_MCS_16X
:
288 unreachable("Unexpected MCS format for fast clear");
291 x_align
= x_scaledown
* 2;
292 y_align
= y_scaledown
* 2;
295 *x0
= ROUND_DOWN_TO(*x0
, x_align
) / x_scaledown
;
296 *y0
= ROUND_DOWN_TO(*y0
, y_align
) / y_scaledown
;
297 *x1
= ALIGN(*x1
, x_align
) / x_scaledown
;
298 *y1
= ALIGN(*y1
, y_align
) / y_scaledown
;
302 blorp_fast_clear(struct blorp_batch
*batch
,
303 const struct blorp_surf
*surf
, enum isl_format format
,
304 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
305 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
307 struct blorp_params params
;
308 blorp_params_init(¶ms
);
309 params
.num_layers
= num_layers
;
316 memset(¶ms
.wm_inputs
.clear_color
, 0xff, 4*sizeof(float));
317 params
.fast_clear_op
= BLORP_FAST_CLEAR_OP_CLEAR
;
319 get_fast_clear_rect(batch
->blorp
->isl_dev
, surf
->aux_surf
,
320 ¶ms
.x0
, ¶ms
.y0
, ¶ms
.x1
, ¶ms
.y1
);
322 blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, true);
324 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
325 start_layer
, format
, true);
326 params
.num_samples
= params
.dst
.surf
.samples
;
328 batch
->blorp
->exec(batch
, ¶ms
);
333 blorp_clear(struct blorp_batch
*batch
,
334 const struct blorp_surf
*surf
,
335 enum isl_format format
, struct isl_swizzle swizzle
,
336 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
337 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
338 union isl_color_value clear_color
,
339 const bool color_write_disable
[4])
341 struct blorp_params params
;
342 blorp_params_init(¶ms
);
349 if (format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
350 clear_color
.u32
[0] = float3_to_rgb9e5(clear_color
.f32
);
351 format
= ISL_FORMAT_R32_UINT
;
354 memcpy(¶ms
.wm_inputs
.clear_color
, clear_color
.f32
, sizeof(float) * 4);
356 bool use_simd16_replicated_data
= true;
358 /* From the SNB PRM (Vol4_Part1):
360 * "Replicated data (Message Type = 111) is only supported when
361 * accessing tiled memory. Using this Message Type to access linear
362 * (untiled) memory is UNDEFINED."
364 if (surf
->surf
->tiling
== ISL_TILING_LINEAR
)
365 use_simd16_replicated_data
= false;
367 /* Constant color writes ignore everyting in blend and color calculator
368 * state. This is not documented.
370 if (color_write_disable
) {
371 for (unsigned i
= 0; i
< 4; i
++) {
372 params
.color_write_disable
[i
] = color_write_disable
[i
];
373 if (color_write_disable
[i
])
374 use_simd16_replicated_data
= false;
378 blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
,
379 use_simd16_replicated_data
);
381 while (num_layers
> 0) {
382 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
383 start_layer
, format
, true);
384 params
.dst
.view
.swizzle
= swizzle
;
386 params
.num_samples
= params
.dst
.surf
.samples
;
388 /* We may be restricted on the number of layers we can bind at any one
389 * time. In particular, Sandy Bridge has a maximum number of layers of
390 * 512 but a maximum 3D texture size is much larger.
392 params
.num_layers
= MIN2(params
.dst
.view
.array_len
, num_layers
);
393 batch
->blorp
->exec(batch
, ¶ms
);
395 start_layer
+= params
.num_layers
;
396 num_layers
-= params
.num_layers
;
401 blorp_clear_depth_stencil(struct blorp_batch
*batch
,
402 const struct blorp_surf
*depth
,
403 const struct blorp_surf
*stencil
,
404 uint32_t level
, uint32_t start_layer
,
406 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
407 bool clear_depth
, float depth_value
,
408 uint8_t stencil_mask
, uint8_t stencil_value
)
410 struct blorp_params params
;
411 blorp_params_init(¶ms
);
418 while (num_layers
> 0) {
419 params
.num_layers
= num_layers
;
422 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
424 ISL_FORMAT_UNSUPPORTED
, true);
425 params
.stencil_mask
= stencil_mask
;
426 params
.stencil_ref
= stencil_value
;
428 params
.dst
.surf
.samples
= params
.stencil
.surf
.samples
;
429 params
.dst
.surf
.logical_level0_px
=
430 params
.stencil
.surf
.logical_level0_px
;
431 params
.dst
.view
= params
.depth
.view
;
433 params
.num_samples
= params
.stencil
.surf
.samples
;
435 /* We may be restricted on the number of layers we can bind at any
436 * one time. In particular, Sandy Bridge has a maximum number of
437 * layers of 512 but a maximum 3D texture size is much larger.
439 if (params
.stencil
.view
.array_len
< params
.num_layers
)
440 params
.num_layers
= params
.stencil
.view
.array_len
;
444 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
446 ISL_FORMAT_UNSUPPORTED
, true);
447 params
.z
= depth_value
;
448 params
.depth_format
=
449 isl_format_get_depth_format(depth
->surf
->format
, false);
451 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
452 params
.dst
.surf
.logical_level0_px
=
453 params
.depth
.surf
.logical_level0_px
;
454 params
.dst
.view
= params
.depth
.view
;
456 params
.num_samples
= params
.depth
.surf
.samples
;
458 /* We may be restricted on the number of layers we can bind at any
459 * one time. In particular, Sandy Bridge has a maximum number of
460 * layers of 512 but a maximum 3D texture size is much larger.
462 if (params
.depth
.view
.array_len
< params
.num_layers
)
463 params
.num_layers
= params
.depth
.view
.array_len
;
466 batch
->blorp
->exec(batch
, ¶ms
);
468 start_layer
+= params
.num_layers
;
469 num_layers
-= params
.num_layers
;
474 blorp_can_hiz_clear_depth(uint8_t gen
, enum isl_format format
,
475 uint32_t num_samples
,
476 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
478 /* This function currently doesn't support any gen prior to gen8 */
481 if (gen
== 8 && format
== ISL_FORMAT_R16_UNORM
) {
482 /* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample
483 * block with the following property: as the number of samples increases,
484 * the number of pixels representable by this block decreases by a factor
485 * of the sample dimensions. Sample dimensions scale following the MSAA
486 * interleaved pattern.
488 * Sample|Sample|Pixel
490 * ===================
497 * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
499 const struct isl_extent2d sa_block_dim
=
500 isl_get_interleaved_msaa_px_size_sa(num_samples
);
501 const uint8_t align_px_w
= 8 / sa_block_dim
.w
;
502 const uint8_t align_px_h
= 4 / sa_block_dim
.h
;
504 /* Fast depth clears clear an entire sample block at a time. As a result,
505 * the rectangle must be aligned to the dimensions of the encompassing
506 * pixel block for a successful operation.
508 * Fast clears can still work if the upper-left corner is aligned and the
509 * bottom-rigtht corner touches the edge of a depth buffer whose extent
510 * is unaligned. This is because each miplevel in the depth buffer is
511 * padded by the Pixel Dim (similar to a standard compressed texture).
512 * In this case, the clear rectangle could be padded by to match the full
513 * depth buffer extent but to support multiple clearing techniques, we
514 * chose to be unaware of the depth buffer's extent and thus don't handle
517 if (x0
% align_px_w
|| y0
% align_px_h
||
518 x1
% align_px_w
|| y1
% align_px_h
)
524 /* Given a depth stencil attachment, this function performs a fast depth clear
525 * on a depth portion and a regular clear on the stencil portion. When
526 * performing a fast depth clear on the depth portion, the HiZ buffer is simply
527 * tagged as cleared so the depth clear value is not actually needed.
530 blorp_gen8_hiz_clear_attachments(struct blorp_batch
*batch
,
531 uint32_t num_samples
,
532 uint32_t x0
, uint32_t y0
,
533 uint32_t x1
, uint32_t y1
,
534 bool clear_depth
, bool clear_stencil
,
535 uint8_t stencil_value
)
537 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
539 struct blorp_params params
;
540 blorp_params_init(¶ms
);
541 params
.num_layers
= 1;
542 params
.hiz_op
= BLORP_HIZ_OP_DEPTH_CLEAR
;
547 params
.num_samples
= num_samples
;
548 params
.depth
.enabled
= clear_depth
;
549 params
.stencil
.enabled
= clear_stencil
;
550 params
.stencil_ref
= stencil_value
;
551 batch
->blorp
->exec(batch
, ¶ms
);
554 /** Clear active color/depth/stencili attachments
556 * This function performs a clear operation on the currently bound
557 * color/depth/stencil attachments. It is assumed that any information passed
558 * in here is valid, consistent, and in-bounds relative to the currently
559 * attached depth/stencil. The binding_table_offset parameter is the 32-bit
560 * offset relative to surface state base address where pre-baked binding table
561 * that we are to use lives. If clear_color is false, binding_table_offset
562 * must point to a binding table with one entry which is a valid null surface
563 * that matches the currently bound depth and stencil.
566 blorp_clear_attachments(struct blorp_batch
*batch
,
567 uint32_t binding_table_offset
,
568 enum isl_format depth_format
,
569 uint32_t num_samples
,
570 uint32_t start_layer
, uint32_t num_layers
,
571 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
572 bool clear_color
, union isl_color_value color_value
,
573 bool clear_depth
, float depth_value
,
574 uint8_t stencil_mask
, uint8_t stencil_value
)
576 struct blorp_params params
;
577 blorp_params_init(¶ms
);
579 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
586 params
.use_pre_baked_binding_table
= true;
587 params
.pre_baked_binding_table_offset
= binding_table_offset
;
589 params
.num_layers
= num_layers
;
590 params
.num_samples
= num_samples
;
593 params
.dst
.enabled
= true;
595 memcpy(¶ms
.wm_inputs
.clear_color
, color_value
.f32
, sizeof(float) * 4);
597 /* Unfortunately, without knowing whether or not our destination surface
598 * is tiled or not, we have to assume it may be linear. This means no
599 * SIMD16_REPDATA for us. :-(
601 blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, false);
605 params
.depth
.enabled
= true;
607 params
.z
= depth_value
;
608 params
.depth_format
= isl_format_get_depth_format(depth_format
, false);
612 params
.stencil
.enabled
= true;
614 params
.stencil_mask
= stencil_mask
;
615 params
.stencil_ref
= stencil_value
;
618 blorp_params_get_layer_offset_vs(batch
->blorp
, ¶ms
);
619 params
.vs_inputs
.base_layer
= start_layer
;
621 batch
->blorp
->exec(batch
, ¶ms
);
625 blorp_ccs_resolve(struct blorp_batch
*batch
,
626 struct blorp_surf
*surf
, uint32_t level
, uint32_t layer
,
627 enum isl_format format
,
628 enum blorp_fast_clear_op resolve_op
)
630 struct blorp_params params
;
631 blorp_params_init(¶ms
);
633 /* Layered and mipmapped fast clear is only available from Gen8 onwards. */
634 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8 ||
635 (level
== 0 && layer
== 0));
637 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
,
638 level
, layer
, format
, true);
640 /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
642 * A rectangle primitive must be scaled down by the following factors
643 * with respect to render target being resolved.
645 * The scaledown factors in the table that follows are related to the block
646 * size of the CCS format. For IVB and HSW, we divide by two, for BDW we
647 * multiply by 8 and 16. On Sky Lake, we multiply by 8.
649 const struct isl_format_layout
*aux_fmtl
=
650 isl_format_get_layout(params
.dst
.aux_surf
.format
);
651 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
653 unsigned x_scaledown
, y_scaledown
;
654 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 9) {
655 x_scaledown
= aux_fmtl
->bw
* 8;
656 y_scaledown
= aux_fmtl
->bh
* 8;
657 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
658 x_scaledown
= aux_fmtl
->bw
* 8;
659 y_scaledown
= aux_fmtl
->bh
* 16;
661 x_scaledown
= aux_fmtl
->bw
/ 2;
662 y_scaledown
= aux_fmtl
->bh
/ 2;
664 params
.x0
= params
.y0
= 0;
665 params
.x1
= minify(params
.dst
.aux_surf
.logical_level0_px
.width
, level
);
666 params
.y1
= minify(params
.dst
.aux_surf
.logical_level0_px
.height
, level
);
667 params
.x1
= ALIGN(params
.x1
, x_scaledown
) / x_scaledown
;
668 params
.y1
= ALIGN(params
.y1
, y_scaledown
) / y_scaledown
;
670 if (batch
->blorp
->isl_dev
->info
->gen
>= 9) {
671 assert(resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_FULL
||
672 resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
);
674 /* Broadwell and earlier do not have a partial resolve */
675 assert(resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_FULL
);
677 params
.fast_clear_op
= resolve_op
;
679 /* Note: there is no need to initialize push constants because it doesn't
680 * matter what data gets dispatched to the render target. However, we must
681 * ensure that the fragment shader delivers the data using the "replicated
685 blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, true);
687 batch
->blorp
->exec(batch
, ¶ms
);