2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/ralloc.h"
26 #include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
27 #include "util/format_rgb9e5.h"
28 #include "util/format_srgb.h"
30 #include "blorp_priv.h"
31 #include "compiler/brw_eu_defines.h"
33 #include "blorp_nir_builder.h"
35 #define FILE_DEBUG_FLAG DEBUG_BLORP
37 struct brw_blorp_const_color_prog_key
39 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_CLEAR */
40 bool use_simd16_replicated_data
;
45 blorp_params_get_clear_kernel(struct blorp_context
*blorp
,
46 struct blorp_params
*params
,
47 bool use_replicated_data
)
49 const struct brw_blorp_const_color_prog_key blorp_key
= {
50 .shader_type
= BLORP_SHADER_TYPE_CLEAR
,
51 .use_simd16_replicated_data
= use_replicated_data
,
54 if (blorp
->lookup_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
55 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
58 void *mem_ctx
= ralloc_context(NULL
);
61 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
62 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "BLORP-clear");
64 nir_variable
*v_color
=
65 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
67 nir_variable
*frag_color
= nir_variable_create(b
.shader
, nir_var_shader_out
,
70 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
72 nir_copy_var(&b
, frag_color
, v_color
);
74 struct brw_wm_prog_key wm_key
;
75 brw_blorp_init_wm_prog_key(&wm_key
);
77 struct brw_wm_prog_data prog_data
;
78 unsigned program_size
;
79 const unsigned *program
=
80 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, use_replicated_data
,
81 &prog_data
, &program_size
);
84 blorp
->upload_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
85 program
, program_size
,
86 &prog_data
.base
, sizeof(prog_data
),
87 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
93 struct layer_offset_vs_key
{
94 enum blorp_shader_type shader_type
;
98 /* In the case of doing attachment clears, we are using a surface state that
99 * is handed to us so we can't set (and don't even know) the base array layer.
100 * In order to do a layered clear in this scenario, we need some way of adding
101 * the base array layer to the instance id. Unfortunately, our hardware has
102 * no real concept of "base instance", so we have to do it manually in a
106 blorp_params_get_layer_offset_vs(struct blorp_context
*blorp
,
107 struct blorp_params
*params
)
109 struct layer_offset_vs_key blorp_key
= {
110 .shader_type
= BLORP_SHADER_TYPE_LAYER_OFFSET_VS
,
113 if (params
->wm_prog_data
)
114 blorp_key
.num_inputs
= params
->wm_prog_data
->num_varying_inputs
;
116 if (blorp
->lookup_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
117 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
))
120 void *mem_ctx
= ralloc_context(NULL
);
123 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_VERTEX
, NULL
);
124 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "BLORP-layer-offset-vs");
126 const struct glsl_type
*uvec4_type
= glsl_vector_type(GLSL_TYPE_UINT
, 4);
128 /* First we deal with the header which has instance and base instance */
129 nir_variable
*a_header
= nir_variable_create(b
.shader
, nir_var_shader_in
,
130 uvec4_type
, "header");
131 a_header
->data
.location
= VERT_ATTRIB_GENERIC0
;
133 nir_variable
*v_layer
= nir_variable_create(b
.shader
, nir_var_shader_out
,
134 glsl_int_type(), "layer_id");
135 v_layer
->data
.location
= VARYING_SLOT_LAYER
;
137 /* Compute the layer id */
138 nir_ssa_def
*header
= nir_load_var(&b
, a_header
);
139 nir_ssa_def
*base_layer
= nir_channel(&b
, header
, 0);
140 nir_ssa_def
*instance
= nir_channel(&b
, header
, 1);
141 nir_store_var(&b
, v_layer
, nir_iadd(&b
, instance
, base_layer
), 0x1);
143 /* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
144 nir_variable
*a_vertex
= nir_variable_create(b
.shader
, nir_var_shader_in
,
145 glsl_vec4_type(), "a_vertex");
146 a_vertex
->data
.location
= VERT_ATTRIB_GENERIC1
;
148 nir_variable
*v_pos
= nir_variable_create(b
.shader
, nir_var_shader_out
,
149 glsl_vec4_type(), "v_pos");
150 v_pos
->data
.location
= VARYING_SLOT_POS
;
152 nir_copy_var(&b
, v_pos
, a_vertex
);
154 /* Then we copy everything else */
155 for (unsigned i
= 0; i
< blorp_key
.num_inputs
; i
++) {
156 nir_variable
*a_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
157 uvec4_type
, "input");
158 a_in
->data
.location
= VERT_ATTRIB_GENERIC2
+ i
;
160 nir_variable
*v_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
161 uvec4_type
, "output");
162 v_out
->data
.location
= VARYING_SLOT_VAR0
+ i
;
164 nir_copy_var(&b
, v_out
, a_in
);
167 struct brw_vs_prog_data vs_prog_data
;
168 memset(&vs_prog_data
, 0, sizeof(vs_prog_data
));
170 unsigned program_size
;
171 const unsigned *program
=
172 blorp_compile_vs(blorp
, mem_ctx
, b
.shader
, &vs_prog_data
, &program_size
);
175 blorp
->upload_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
176 program
, program_size
,
177 &vs_prog_data
.base
.base
, sizeof(vs_prog_data
),
178 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
);
180 ralloc_free(mem_ctx
);
184 /* The x0, y0, x1, and y1 parameters must already be populated with the render
185 * area of the framebuffer to be cleared.
188 get_fast_clear_rect(const struct isl_device
*dev
,
189 const struct isl_surf
*aux_surf
,
190 unsigned *x0
, unsigned *y0
,
191 unsigned *x1
, unsigned *y1
)
193 unsigned int x_align
, y_align
;
194 unsigned int x_scaledown
, y_scaledown
;
196 /* Only single sampled surfaces need to (and actually can) be resolved. */
197 if (aux_surf
->usage
== ISL_SURF_USAGE_CCS_BIT
) {
198 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
199 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
201 * Clear pass must have a clear rectangle that must follow
202 * alignment rules in terms of pixels and lines as shown in the
203 * table below. Further, the clear-rectangle height and width
204 * must be multiple of the following dimensions. If the height
205 * and width of the render target being cleared do not meet these
206 * requirements, an MCS buffer can be created such that it
207 * follows the requirement and covers the RT.
209 * The alignment size in the table that follows is related to the
210 * alignment size that is baked into the CCS surface format but with X
211 * alignment multiplied by 16 and Y alignment multiplied by 32.
213 x_align
= isl_format_get_layout(aux_surf
->format
)->bw
;
214 y_align
= isl_format_get_layout(aux_surf
->format
)->bh
;
218 /* SKL+ line alignment requirement for Y-tiled are half those of the prior
221 if (dev
->info
->gen
>= 9)
226 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
227 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
229 * In order to optimize the performance MCS buffer (when bound to
230 * 1X RT) clear similarly to MCS buffer clear for MSRT case,
231 * clear rect is required to be scaled by the following factors
232 * in the horizontal and vertical directions:
234 * The X and Y scale down factors in the table that follows are each
235 * equal to half the alignment value computed above.
237 x_scaledown
= x_align
/ 2;
238 y_scaledown
= y_align
/ 2;
240 /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
241 * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
242 * Clear of Non-MultiSampled Render Target Restrictions":
244 * Clear rectangle must be aligned to two times the number of
245 * pixels in the table shown below due to 16x16 hashing across the
251 assert(aux_surf
->usage
== ISL_SURF_USAGE_MCS_BIT
);
253 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
254 * Target(s)", beneath the "MSAA Compression" bullet (p326):
256 * Clear pass for this case requires that scaled down primitive
257 * is sent down with upper left co-ordinate to coincide with
258 * actual rectangle being cleared. For MSAA, clear rectangle’s
259 * height and width need to as show in the following table in
260 * terms of (width,height) of the RT.
262 * MSAA Width of Clear Rect Height of Clear Rect
263 * 2X Ceil(1/8*width) Ceil(1/2*height)
264 * 4X Ceil(1/8*width) Ceil(1/2*height)
265 * 8X Ceil(1/2*width) Ceil(1/2*height)
266 * 16X width Ceil(1/2*height)
268 * The text "with upper left co-ordinate to coincide with actual
269 * rectangle being cleared" is a little confusing--it seems to imply
270 * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
271 * feed the pipeline using the rectangle (x,y) to
272 * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
273 * the number of samples. Experiments indicate that this is not
274 * quite correct; actually, what the hardware appears to do is to
275 * align whatever rectangle is sent down the pipeline to the nearest
276 * multiple of 2x2 blocks, and then scale it up by a factor of N
277 * horizontally and 2 vertically. So the resulting alignment is 4
278 * vertically and either 4 or 16 horizontally, and the scaledown
279 * factor is 2 vertically and either 2 or 8 horizontally.
281 switch (aux_surf
->format
) {
282 case ISL_FORMAT_MCS_2X
:
283 case ISL_FORMAT_MCS_4X
:
286 case ISL_FORMAT_MCS_8X
:
289 case ISL_FORMAT_MCS_16X
:
293 unreachable("Unexpected MCS format for fast clear");
296 x_align
= x_scaledown
* 2;
297 y_align
= y_scaledown
* 2;
300 *x0
= ROUND_DOWN_TO(*x0
, x_align
) / x_scaledown
;
301 *y0
= ROUND_DOWN_TO(*y0
, y_align
) / y_scaledown
;
302 *x1
= ALIGN(*x1
, x_align
) / x_scaledown
;
303 *y1
= ALIGN(*y1
, y_align
) / y_scaledown
;
307 blorp_fast_clear(struct blorp_batch
*batch
,
308 const struct blorp_surf
*surf
, enum isl_format format
,
309 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
310 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
312 /* Ensure that all layers undergoing the clear have an auxiliary buffer. */
313 assert(start_layer
+ num_layers
<=
314 MAX2(surf
->aux_surf
->logical_level0_px
.depth
>> level
,
315 surf
->aux_surf
->logical_level0_px
.array_len
));
317 struct blorp_params params
;
318 blorp_params_init(¶ms
);
319 params
.num_layers
= num_layers
;
326 memset(¶ms
.wm_inputs
.clear_color
, 0xff, 4*sizeof(float));
327 params
.fast_clear_op
= BLORP_FAST_CLEAR_OP_CLEAR
;
329 get_fast_clear_rect(batch
->blorp
->isl_dev
, surf
->aux_surf
,
330 ¶ms
.x0
, ¶ms
.y0
, ¶ms
.x1
, ¶ms
.y1
);
332 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, true))
335 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
336 start_layer
, format
, true);
337 params
.num_samples
= params
.dst
.surf
.samples
;
339 batch
->blorp
->exec(batch
, ¶ms
);
342 static union isl_color_value
343 swizzle_color_value(union isl_color_value src
, struct isl_swizzle swizzle
)
345 union isl_color_value dst
= { .u32
= { 0, } };
347 /* We assign colors in ABGR order so that the first one will be taken in
348 * RGBA precedence order. According to the PRM docs for shader channel
349 * select, this matches Haswell hardware behavior.
351 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
352 dst
.u32
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[3];
353 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
354 dst
.u32
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[2];
355 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
356 dst
.u32
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[1];
357 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
358 dst
.u32
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[0];
364 blorp_clear(struct blorp_batch
*batch
,
365 const struct blorp_surf
*surf
,
366 enum isl_format format
, struct isl_swizzle swizzle
,
367 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
368 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
369 union isl_color_value clear_color
,
370 const bool color_write_disable
[4])
372 struct blorp_params params
;
373 blorp_params_init(¶ms
);
375 /* Manually apply the clear destination swizzle. This way swizzled clears
376 * will work for swizzles which we can't normally use for rendering and it
377 * also ensures that they work on pre-Haswell hardware which can't swizlle
380 clear_color
= swizzle_color_value(clear_color
, swizzle
);
381 swizzle
= ISL_SWIZZLE_IDENTITY
;
383 if (format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
384 clear_color
.u32
[0] = float3_to_rgb9e5(clear_color
.f32
);
385 format
= ISL_FORMAT_R32_UINT
;
386 } else if (format
== ISL_FORMAT_L8_UNORM_SRGB
) {
387 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
388 format
= ISL_FORMAT_R8_UNORM
;
389 } else if (format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
390 /* Broadwell and earlier cannot render to this format so we need to work
391 * around it by swapping the colors around and using B4G4R4A4 instead.
393 const struct isl_swizzle ARGB
= ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
);
394 clear_color
= swizzle_color_value(clear_color
, ARGB
);
395 format
= ISL_FORMAT_B4G4R4A4_UNORM
;
398 memcpy(¶ms
.wm_inputs
.clear_color
, clear_color
.f32
, sizeof(float) * 4);
400 bool use_simd16_replicated_data
= true;
402 /* From the SNB PRM (Vol4_Part1):
404 * "Replicated data (Message Type = 111) is only supported when
405 * accessing tiled memory. Using this Message Type to access linear
406 * (untiled) memory is UNDEFINED."
408 if (surf
->surf
->tiling
== ISL_TILING_LINEAR
)
409 use_simd16_replicated_data
= false;
411 /* Replicated clears don't work yet before gen6 */
412 if (batch
->blorp
->isl_dev
->info
->gen
< 6)
413 use_simd16_replicated_data
= false;
415 /* Constant color writes ignore everyting in blend and color calculator
416 * state. This is not documented.
418 if (color_write_disable
) {
419 for (unsigned i
= 0; i
< 4; i
++) {
420 params
.color_write_disable
[i
] = color_write_disable
[i
];
421 if (color_write_disable
[i
])
422 use_simd16_replicated_data
= false;
426 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
,
427 use_simd16_replicated_data
))
430 if (!blorp_ensure_sf_program(batch
->blorp
, ¶ms
))
433 while (num_layers
> 0) {
434 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
435 start_layer
, format
, true);
436 params
.dst
.view
.swizzle
= swizzle
;
443 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
444 * Convert them to a single slice on gen4.
446 if (batch
->blorp
->isl_dev
->info
->gen
== 4 &&
447 (params
.dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
)) {
448 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
.dst
);
451 if (isl_format_is_compressed(params
.dst
.surf
.format
)) {
452 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
453 NULL
, NULL
, NULL
, NULL
);
454 //&dst_x, &dst_y, &dst_w, &dst_h);
457 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
458 /* Either we're on gen4 where there is no multisampling or the
459 * surface is compressed which also implies no multisampling.
460 * Therefore, sa == px and we don't need to do a conversion.
462 assert(params
.dst
.surf
.samples
== 1);
463 params
.x0
+= params
.dst
.tile_x_sa
;
464 params
.y0
+= params
.dst
.tile_y_sa
;
465 params
.x1
+= params
.dst
.tile_x_sa
;
466 params
.y1
+= params
.dst
.tile_y_sa
;
469 params
.num_samples
= params
.dst
.surf
.samples
;
471 /* We may be restricted on the number of layers we can bind at any one
472 * time. In particular, Sandy Bridge has a maximum number of layers of
473 * 512 but a maximum 3D texture size is much larger.
475 params
.num_layers
= MIN2(params
.dst
.view
.array_len
, num_layers
);
476 batch
->blorp
->exec(batch
, ¶ms
);
478 start_layer
+= params
.num_layers
;
479 num_layers
-= params
.num_layers
;
484 blorp_clear_depth_stencil(struct blorp_batch
*batch
,
485 const struct blorp_surf
*depth
,
486 const struct blorp_surf
*stencil
,
487 uint32_t level
, uint32_t start_layer
,
489 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
490 bool clear_depth
, float depth_value
,
491 uint8_t stencil_mask
, uint8_t stencil_value
)
493 struct blorp_params params
;
494 blorp_params_init(¶ms
);
501 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) == 6) {
502 /* For some reason, Sandy Bridge gets occlusion queries wrong if we
503 * don't have a shader. In particular, it records samples even though
504 * we disable statistics in 3DSTATE_WM. Give it the usual clear shader
505 * to work around the issue.
507 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, false))
511 while (num_layers
> 0) {
512 params
.num_layers
= num_layers
;
515 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
517 ISL_FORMAT_UNSUPPORTED
, true);
518 params
.stencil_mask
= stencil_mask
;
519 params
.stencil_ref
= stencil_value
;
521 params
.dst
.surf
.samples
= params
.stencil
.surf
.samples
;
522 params
.dst
.surf
.logical_level0_px
=
523 params
.stencil
.surf
.logical_level0_px
;
524 params
.dst
.view
= params
.depth
.view
;
526 params
.num_samples
= params
.stencil
.surf
.samples
;
528 /* We may be restricted on the number of layers we can bind at any
529 * one time. In particular, Sandy Bridge has a maximum number of
530 * layers of 512 but a maximum 3D texture size is much larger.
532 if (params
.stencil
.view
.array_len
< params
.num_layers
)
533 params
.num_layers
= params
.stencil
.view
.array_len
;
537 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
539 ISL_FORMAT_UNSUPPORTED
, true);
540 params
.z
= depth_value
;
541 params
.depth_format
=
542 isl_format_get_depth_format(depth
->surf
->format
, false);
544 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
545 params
.dst
.surf
.logical_level0_px
=
546 params
.depth
.surf
.logical_level0_px
;
547 params
.dst
.view
= params
.depth
.view
;
549 params
.num_samples
= params
.depth
.surf
.samples
;
551 /* We may be restricted on the number of layers we can bind at any
552 * one time. In particular, Sandy Bridge has a maximum number of
553 * layers of 512 but a maximum 3D texture size is much larger.
555 if (params
.depth
.view
.array_len
< params
.num_layers
)
556 params
.num_layers
= params
.depth
.view
.array_len
;
559 batch
->blorp
->exec(batch
, ¶ms
);
561 start_layer
+= params
.num_layers
;
562 num_layers
-= params
.num_layers
;
567 blorp_can_hiz_clear_depth(uint8_t gen
, enum isl_format format
,
568 uint32_t num_samples
,
569 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
571 /* This function currently doesn't support any gen prior to gen8 */
574 if (gen
== 8 && format
== ISL_FORMAT_R16_UNORM
) {
575 /* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample
576 * block with the following property: as the number of samples increases,
577 * the number of pixels representable by this block decreases by a factor
578 * of the sample dimensions. Sample dimensions scale following the MSAA
579 * interleaved pattern.
581 * Sample|Sample|Pixel
583 * ===================
590 * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
592 const struct isl_extent2d sa_block_dim
=
593 isl_get_interleaved_msaa_px_size_sa(num_samples
);
594 const uint8_t align_px_w
= 8 / sa_block_dim
.w
;
595 const uint8_t align_px_h
= 4 / sa_block_dim
.h
;
597 /* Fast depth clears clear an entire sample block at a time. As a result,
598 * the rectangle must be aligned to the dimensions of the encompassing
599 * pixel block for a successful operation.
601 * Fast clears can still work if the upper-left corner is aligned and the
602 * bottom-rigtht corner touches the edge of a depth buffer whose extent
603 * is unaligned. This is because each miplevel in the depth buffer is
604 * padded by the Pixel Dim (similar to a standard compressed texture).
605 * In this case, the clear rectangle could be padded by to match the full
606 * depth buffer extent but to support multiple clearing techniques, we
607 * chose to be unaware of the depth buffer's extent and thus don't handle
610 if (x0
% align_px_w
|| y0
% align_px_h
||
611 x1
% align_px_w
|| y1
% align_px_h
)
617 /* Given a depth stencil attachment, this function performs a fast depth clear
618 * on a depth portion and a regular clear on the stencil portion. When
619 * performing a fast depth clear on the depth portion, the HiZ buffer is simply
620 * tagged as cleared so the depth clear value is not actually needed.
623 blorp_gen8_hiz_clear_attachments(struct blorp_batch
*batch
,
624 uint32_t num_samples
,
625 uint32_t x0
, uint32_t y0
,
626 uint32_t x1
, uint32_t y1
,
627 bool clear_depth
, bool clear_stencil
,
628 uint8_t stencil_value
)
630 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
632 struct blorp_params params
;
633 blorp_params_init(¶ms
);
634 params
.num_layers
= 1;
635 params
.hiz_op
= BLORP_HIZ_OP_DEPTH_CLEAR
;
640 params
.num_samples
= num_samples
;
641 params
.depth
.enabled
= clear_depth
;
642 params
.stencil
.enabled
= clear_stencil
;
643 params
.stencil_ref
= stencil_value
;
644 batch
->blorp
->exec(batch
, ¶ms
);
647 /** Clear active color/depth/stencili attachments
649 * This function performs a clear operation on the currently bound
650 * color/depth/stencil attachments. It is assumed that any information passed
651 * in here is valid, consistent, and in-bounds relative to the currently
652 * attached depth/stencil. The binding_table_offset parameter is the 32-bit
653 * offset relative to surface state base address where pre-baked binding table
654 * that we are to use lives. If clear_color is false, binding_table_offset
655 * must point to a binding table with one entry which is a valid null surface
656 * that matches the currently bound depth and stencil.
659 blorp_clear_attachments(struct blorp_batch
*batch
,
660 uint32_t binding_table_offset
,
661 enum isl_format depth_format
,
662 uint32_t num_samples
,
663 uint32_t start_layer
, uint32_t num_layers
,
664 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
665 bool clear_color
, union isl_color_value color_value
,
666 bool clear_depth
, float depth_value
,
667 uint8_t stencil_mask
, uint8_t stencil_value
)
669 struct blorp_params params
;
670 blorp_params_init(¶ms
);
672 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
679 params
.use_pre_baked_binding_table
= true;
680 params
.pre_baked_binding_table_offset
= binding_table_offset
;
682 params
.num_layers
= num_layers
;
683 params
.num_samples
= num_samples
;
686 params
.dst
.enabled
= true;
688 memcpy(¶ms
.wm_inputs
.clear_color
, color_value
.f32
, sizeof(float) * 4);
690 /* Unfortunately, without knowing whether or not our destination surface
691 * is tiled or not, we have to assume it may be linear. This means no
692 * SIMD16_REPDATA for us. :-(
694 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, false))
699 params
.depth
.enabled
= true;
701 params
.z
= depth_value
;
702 params
.depth_format
= isl_format_get_depth_format(depth_format
, false);
706 params
.stencil
.enabled
= true;
708 params
.stencil_mask
= stencil_mask
;
709 params
.stencil_ref
= stencil_value
;
712 if (!blorp_params_get_layer_offset_vs(batch
->blorp
, ¶ms
))
715 params
.vs_inputs
.base_layer
= start_layer
;
717 batch
->blorp
->exec(batch
, ¶ms
);
721 prepare_ccs_resolve(struct blorp_batch
* const batch
,
722 struct blorp_params
* const params
,
723 const struct blorp_surf
* const surf
,
724 const uint32_t level
, const uint32_t layer
,
725 const enum isl_format format
,
726 const enum blorp_fast_clear_op resolve_op
)
728 blorp_params_init(params
);
729 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
->dst
, surf
,
730 level
, layer
, format
, true);
732 /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
734 * A rectangle primitive must be scaled down by the following factors
735 * with respect to render target being resolved.
737 * The scaledown factors in the table that follows are related to the block
738 * size of the CCS format. For IVB and HSW, we divide by two, for BDW we
739 * multiply by 8 and 16. On Sky Lake, we multiply by 8.
741 const struct isl_format_layout
*aux_fmtl
=
742 isl_format_get_layout(params
->dst
.aux_surf
.format
);
743 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
745 unsigned x_scaledown
, y_scaledown
;
746 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 9) {
747 x_scaledown
= aux_fmtl
->bw
* 8;
748 y_scaledown
= aux_fmtl
->bh
* 8;
749 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
750 x_scaledown
= aux_fmtl
->bw
* 8;
751 y_scaledown
= aux_fmtl
->bh
* 16;
753 x_scaledown
= aux_fmtl
->bw
/ 2;
754 y_scaledown
= aux_fmtl
->bh
/ 2;
756 params
->x0
= params
->y0
= 0;
757 params
->x1
= minify(params
->dst
.aux_surf
.logical_level0_px
.width
, level
);
758 params
->y1
= minify(params
->dst
.aux_surf
.logical_level0_px
.height
, level
);
759 params
->x1
= ALIGN(params
->x1
, x_scaledown
) / x_scaledown
;
760 params
->y1
= ALIGN(params
->y1
, y_scaledown
) / y_scaledown
;
762 if (batch
->blorp
->isl_dev
->info
->gen
>= 9) {
763 assert(resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_FULL
||
764 resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
);
766 /* Broadwell and earlier do not have a partial resolve */
767 assert(resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_FULL
);
769 params
->fast_clear_op
= resolve_op
;
771 /* Note: there is no need to initialize push constants because it doesn't
772 * matter what data gets dispatched to the render target. However, we must
773 * ensure that the fragment shader delivers the data using the "replicated
777 if (!blorp_params_get_clear_kernel(batch
->blorp
, params
, true))
782 blorp_ccs_resolve(struct blorp_batch
*batch
,
783 struct blorp_surf
*surf
, uint32_t level
, uint32_t layer
,
784 enum isl_format format
,
785 enum blorp_fast_clear_op resolve_op
)
787 struct blorp_params params
;
789 prepare_ccs_resolve(batch
, ¶ms
, surf
, level
, layer
, format
, resolve_op
);
791 batch
->blorp
->exec(batch
, ¶ms
);
795 blorp_ccs_resolve_attachment(struct blorp_batch
*batch
,
796 const uint32_t binding_table_offset
,
797 struct blorp_surf
* const surf
,
798 const uint32_t level
, const uint32_t num_layers
,
799 const enum isl_format format
,
800 const enum blorp_fast_clear_op resolve_op
)
802 struct blorp_params params
;
804 prepare_ccs_resolve(batch
, ¶ms
, surf
, level
, 0, format
, resolve_op
);
805 params
.use_pre_baked_binding_table
= true;
806 params
.pre_baked_binding_table_offset
= binding_table_offset
;
807 params
.num_layers
= num_layers
;
809 batch
->blorp
->exec(batch
, ¶ms
);
812 struct blorp_mcs_partial_resolve_key
814 enum blorp_shader_type shader_type
;
815 uint32_t num_samples
;
819 blorp_params_get_mcs_partial_resolve_kernel(struct blorp_context
*blorp
,
820 struct blorp_params
*params
)
822 const struct blorp_mcs_partial_resolve_key blorp_key
= {
823 .shader_type
= BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE
,
824 .num_samples
= params
->num_samples
,
827 if (blorp
->lookup_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
828 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
831 void *mem_ctx
= ralloc_context(NULL
);
834 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
835 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "BLORP-mcs-partial-resolve");
837 nir_variable
*v_color
=
838 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
840 nir_variable
*frag_color
=
841 nir_variable_create(b
.shader
, nir_var_shader_out
,
842 glsl_vec4_type(), "gl_FragColor");
843 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
845 /* Do an MCS fetch and check if it is equal to the magic clear value */
847 blorp_nir_txf_ms_mcs(&b
, nir_f2i32(&b
, blorp_nir_frag_coord(&b
)),
848 nir_load_layer_id(&b
));
849 nir_ssa_def
*is_clear
=
850 blorp_nir_mcs_is_clear_color(&b
, mcs
, blorp_key
.num_samples
);
852 /* If we aren't the clear value, discard. */
853 nir_intrinsic_instr
*discard
=
854 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_discard_if
);
855 discard
->src
[0] = nir_src_for_ssa(nir_inot(&b
, is_clear
));
856 nir_builder_instr_insert(&b
, &discard
->instr
);
858 nir_copy_var(&b
, frag_color
, v_color
);
860 struct brw_wm_prog_key wm_key
;
861 brw_blorp_init_wm_prog_key(&wm_key
);
862 wm_key
.tex
.compressed_multisample_layout_mask
= 1;
863 wm_key
.tex
.msaa_16
= blorp_key
.num_samples
== 16;
864 wm_key
.multisample_fbo
= true;
866 struct brw_wm_prog_data prog_data
;
867 unsigned program_size
;
868 const unsigned *program
=
869 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, false,
870 &prog_data
, &program_size
);
873 blorp
->upload_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
874 program
, program_size
,
875 &prog_data
.base
, sizeof(prog_data
),
876 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
878 ralloc_free(mem_ctx
);
883 blorp_mcs_partial_resolve(struct blorp_batch
*batch
,
884 struct blorp_surf
*surf
,
885 enum isl_format format
,
886 uint32_t start_layer
, uint32_t num_layers
)
888 struct blorp_params params
;
889 blorp_params_init(¶ms
);
891 assert(batch
->blorp
->isl_dev
->info
->gen
>= 7);
895 params
.x1
= surf
->surf
->logical_level0_px
.width
;
896 params
.y1
= surf
->surf
->logical_level0_px
.height
;
898 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, surf
, 0,
899 start_layer
, format
, false);
900 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, 0,
901 start_layer
, format
, true);
903 params
.num_samples
= params
.dst
.surf
.samples
;
904 params
.num_layers
= num_layers
;
906 memcpy(¶ms
.wm_inputs
.clear_color
,
907 surf
->clear_color
.f32
, sizeof(float) * 4);
909 if (!blorp_params_get_mcs_partial_resolve_kernel(batch
->blorp
, ¶ms
))
912 batch
->blorp
->exec(batch
, ¶ms
);