2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/ralloc.h"
26 #include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
27 #include "util/format_rgb9e5.h"
28 #include "util/format_srgb.h"
30 #include "blorp_priv.h"
31 #include "compiler/brw_eu_defines.h"
33 #include "blorp_nir_builder.h"
35 #define FILE_DEBUG_FLAG DEBUG_BLORP
37 struct brw_blorp_const_color_prog_key
39 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_CLEAR */
40 bool use_simd16_replicated_data
;
41 bool clear_rgb_as_red
;
46 blorp_params_get_clear_kernel(struct blorp_batch
*batch
,
47 struct blorp_params
*params
,
48 bool use_replicated_data
,
49 bool clear_rgb_as_red
)
51 struct blorp_context
*blorp
= batch
->blorp
;
53 const struct brw_blorp_const_color_prog_key blorp_key
= {
54 .shader_type
= BLORP_SHADER_TYPE_CLEAR
,
55 .use_simd16_replicated_data
= use_replicated_data
,
56 .clear_rgb_as_red
= clear_rgb_as_red
,
59 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
60 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
63 void *mem_ctx
= ralloc_context(NULL
);
66 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, "BLORP-clear");
68 nir_variable
*v_color
=
69 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
70 nir_ssa_def
*color
= nir_load_var(&b
, v_color
);
72 if (clear_rgb_as_red
) {
73 nir_variable
*frag_coord
=
74 nir_variable_create(b
.shader
, nir_var_shader_in
,
75 glsl_vec4_type(), "gl_FragCoord");
76 frag_coord
->data
.location
= VARYING_SLOT_POS
;
78 nir_ssa_def
*pos
= nir_f2i32(&b
, nir_load_var(&b
, frag_coord
));
79 nir_ssa_def
*comp
= nir_umod(&b
, nir_channel(&b
, pos
, 0),
81 nir_ssa_def
*color_component
=
82 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
83 nir_channel(&b
, color
, 0),
84 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
85 nir_channel(&b
, color
, 1),
86 nir_channel(&b
, color
, 2)));
88 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
89 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
92 nir_variable
*frag_color
= nir_variable_create(b
.shader
, nir_var_shader_out
,
95 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
96 nir_store_var(&b
, frag_color
, color
, 0xf);
98 struct brw_wm_prog_key wm_key
;
99 brw_blorp_init_wm_prog_key(&wm_key
);
101 struct brw_wm_prog_data prog_data
;
102 const unsigned *program
=
103 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, use_replicated_data
,
107 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
108 program
, prog_data
.base
.program_size
,
109 &prog_data
.base
, sizeof(prog_data
),
110 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
112 ralloc_free(mem_ctx
);
116 struct layer_offset_vs_key
{
117 enum blorp_shader_type shader_type
;
121 /* In the case of doing attachment clears, we are using a surface state that
122 * is handed to us so we can't set (and don't even know) the base array layer.
123 * In order to do a layered clear in this scenario, we need some way of adding
124 * the base array layer to the instance id. Unfortunately, our hardware has
125 * no real concept of "base instance", so we have to do it manually in a
129 blorp_params_get_layer_offset_vs(struct blorp_batch
*batch
,
130 struct blorp_params
*params
)
132 struct blorp_context
*blorp
= batch
->blorp
;
133 struct layer_offset_vs_key blorp_key
= {
134 .shader_type
= BLORP_SHADER_TYPE_LAYER_OFFSET_VS
,
137 if (params
->wm_prog_data
)
138 blorp_key
.num_inputs
= params
->wm_prog_data
->num_varying_inputs
;
140 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
141 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
))
144 void *mem_ctx
= ralloc_context(NULL
);
147 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_VERTEX
, "BLORP-layer-offset-vs");
149 const struct glsl_type
*uvec4_type
= glsl_vector_type(GLSL_TYPE_UINT
, 4);
151 /* First we deal with the header which has instance and base instance */
152 nir_variable
*a_header
= nir_variable_create(b
.shader
, nir_var_shader_in
,
153 uvec4_type
, "header");
154 a_header
->data
.location
= VERT_ATTRIB_GENERIC0
;
156 nir_variable
*v_layer
= nir_variable_create(b
.shader
, nir_var_shader_out
,
157 glsl_int_type(), "layer_id");
158 v_layer
->data
.location
= VARYING_SLOT_LAYER
;
160 /* Compute the layer id */
161 nir_ssa_def
*header
= nir_load_var(&b
, a_header
);
162 nir_ssa_def
*base_layer
= nir_channel(&b
, header
, 0);
163 nir_ssa_def
*instance
= nir_channel(&b
, header
, 1);
164 nir_store_var(&b
, v_layer
, nir_iadd(&b
, instance
, base_layer
), 0x1);
166 /* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
167 nir_variable
*a_vertex
= nir_variable_create(b
.shader
, nir_var_shader_in
,
168 glsl_vec4_type(), "a_vertex");
169 a_vertex
->data
.location
= VERT_ATTRIB_GENERIC1
;
171 nir_variable
*v_pos
= nir_variable_create(b
.shader
, nir_var_shader_out
,
172 glsl_vec4_type(), "v_pos");
173 v_pos
->data
.location
= VARYING_SLOT_POS
;
175 nir_copy_var(&b
, v_pos
, a_vertex
);
177 /* Then we copy everything else */
178 for (unsigned i
= 0; i
< blorp_key
.num_inputs
; i
++) {
179 nir_variable
*a_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
180 uvec4_type
, "input");
181 a_in
->data
.location
= VERT_ATTRIB_GENERIC2
+ i
;
183 nir_variable
*v_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
184 uvec4_type
, "output");
185 v_out
->data
.location
= VARYING_SLOT_VAR0
+ i
;
187 nir_copy_var(&b
, v_out
, a_in
);
190 struct brw_vs_prog_data vs_prog_data
;
191 memset(&vs_prog_data
, 0, sizeof(vs_prog_data
));
193 const unsigned *program
=
194 blorp_compile_vs(blorp
, mem_ctx
, b
.shader
, &vs_prog_data
);
197 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
198 program
, vs_prog_data
.base
.base
.program_size
,
199 &vs_prog_data
.base
.base
, sizeof(vs_prog_data
),
200 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
);
202 ralloc_free(mem_ctx
);
206 /* The x0, y0, x1, and y1 parameters must already be populated with the render
207 * area of the framebuffer to be cleared.
210 get_fast_clear_rect(const struct isl_device
*dev
,
211 const struct isl_surf
*aux_surf
,
212 unsigned *x0
, unsigned *y0
,
213 unsigned *x1
, unsigned *y1
)
215 unsigned int x_align
, y_align
;
216 unsigned int x_scaledown
, y_scaledown
;
218 /* Only single sampled surfaces need to (and actually can) be resolved. */
219 if (aux_surf
->usage
== ISL_SURF_USAGE_CCS_BIT
) {
220 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
221 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
223 * Clear pass must have a clear rectangle that must follow
224 * alignment rules in terms of pixels and lines as shown in the
225 * table below. Further, the clear-rectangle height and width
226 * must be multiple of the following dimensions. If the height
227 * and width of the render target being cleared do not meet these
228 * requirements, an MCS buffer can be created such that it
229 * follows the requirement and covers the RT.
231 * The alignment size in the table that follows is related to the
232 * alignment size that is baked into the CCS surface format but with X
233 * alignment multiplied by 16 and Y alignment multiplied by 32.
235 x_align
= isl_format_get_layout(aux_surf
->format
)->bw
;
236 y_align
= isl_format_get_layout(aux_surf
->format
)->bh
;
240 /* SKL+ line alignment requirement for Y-tiled are half those of the prior
243 if (dev
->info
->gen
>= 9)
248 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
249 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
251 * In order to optimize the performance MCS buffer (when bound to
252 * 1X RT) clear similarly to MCS buffer clear for MSRT case,
253 * clear rect is required to be scaled by the following factors
254 * in the horizontal and vertical directions:
256 * The X and Y scale down factors in the table that follows are each
257 * equal to half the alignment value computed above.
259 x_scaledown
= x_align
/ 2;
260 y_scaledown
= y_align
/ 2;
262 if (ISL_DEV_IS_HASWELL(dev
)) {
263 /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
264 * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
265 * Clear of Non-MultiSampled Render Target Restrictions":
267 * Clear rectangle must be aligned to two times the number of
268 * pixels in the table shown below due to 16x16 hashing across the
271 * This restriction is only documented to exist on HSW GT3 but
272 * empirical evidence suggests that it's also needed GT2.
278 assert(aux_surf
->usage
== ISL_SURF_USAGE_MCS_BIT
);
280 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
281 * Target(s)", beneath the "MSAA Compression" bullet (p326):
283 * Clear pass for this case requires that scaled down primitive
284 * is sent down with upper left co-ordinate to coincide with
285 * actual rectangle being cleared. For MSAA, clear rectangle’s
286 * height and width need to as show in the following table in
287 * terms of (width,height) of the RT.
289 * MSAA Width of Clear Rect Height of Clear Rect
290 * 2X Ceil(1/8*width) Ceil(1/2*height)
291 * 4X Ceil(1/8*width) Ceil(1/2*height)
292 * 8X Ceil(1/2*width) Ceil(1/2*height)
293 * 16X width Ceil(1/2*height)
295 * The text "with upper left co-ordinate to coincide with actual
296 * rectangle being cleared" is a little confusing--it seems to imply
297 * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
298 * feed the pipeline using the rectangle (x,y) to
299 * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
300 * the number of samples. Experiments indicate that this is not
301 * quite correct; actually, what the hardware appears to do is to
302 * align whatever rectangle is sent down the pipeline to the nearest
303 * multiple of 2x2 blocks, and then scale it up by a factor of N
304 * horizontally and 2 vertically. So the resulting alignment is 4
305 * vertically and either 4 or 16 horizontally, and the scaledown
306 * factor is 2 vertically and either 2 or 8 horizontally.
308 switch (aux_surf
->format
) {
309 case ISL_FORMAT_MCS_2X
:
310 case ISL_FORMAT_MCS_4X
:
313 case ISL_FORMAT_MCS_8X
:
316 case ISL_FORMAT_MCS_16X
:
320 unreachable("Unexpected MCS format for fast clear");
323 x_align
= x_scaledown
* 2;
324 y_align
= y_scaledown
* 2;
327 *x0
= ROUND_DOWN_TO(*x0
, x_align
) / x_scaledown
;
328 *y0
= ROUND_DOWN_TO(*y0
, y_align
) / y_scaledown
;
329 *x1
= ALIGN(*x1
, x_align
) / x_scaledown
;
330 *y1
= ALIGN(*y1
, y_align
) / y_scaledown
;
334 blorp_fast_clear(struct blorp_batch
*batch
,
335 const struct blorp_surf
*surf
, enum isl_format format
,
336 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
337 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
339 /* Ensure that all layers undergoing the clear have an auxiliary buffer. */
340 assert(start_layer
+ num_layers
<=
341 MAX2(surf
->aux_surf
->logical_level0_px
.depth
>> level
,
342 surf
->aux_surf
->logical_level0_px
.array_len
));
344 struct blorp_params params
;
345 blorp_params_init(¶ms
);
346 params
.num_layers
= num_layers
;
353 memset(¶ms
.wm_inputs
.clear_color
, 0xff, 4*sizeof(float));
354 params
.fast_clear_op
= ISL_AUX_OP_FAST_CLEAR
;
356 get_fast_clear_rect(batch
->blorp
->isl_dev
, surf
->aux_surf
,
357 ¶ms
.x0
, ¶ms
.y0
, ¶ms
.x1
, ¶ms
.y1
);
359 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
362 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
363 start_layer
, format
, true);
364 params
.num_samples
= params
.dst
.surf
.samples
;
366 batch
->blorp
->exec(batch
, ¶ms
);
369 union isl_color_value
370 swizzle_color_value(union isl_color_value src
, struct isl_swizzle swizzle
)
372 union isl_color_value dst
= { .u32
= { 0, } };
374 /* We assign colors in ABGR order so that the first one will be taken in
375 * RGBA precedence order. According to the PRM docs for shader channel
376 * select, this matches Haswell hardware behavior.
378 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
379 dst
.u32
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[3];
380 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
381 dst
.u32
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[2];
382 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
383 dst
.u32
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[1];
384 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
385 dst
.u32
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[0];
391 blorp_clear(struct blorp_batch
*batch
,
392 const struct blorp_surf
*surf
,
393 enum isl_format format
, struct isl_swizzle swizzle
,
394 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
395 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
396 union isl_color_value clear_color
,
397 const bool color_write_disable
[4])
399 struct blorp_params params
;
400 blorp_params_init(¶ms
);
402 /* Manually apply the clear destination swizzle. This way swizzled clears
403 * will work for swizzles which we can't normally use for rendering and it
404 * also ensures that they work on pre-Haswell hardware which can't swizlle
407 clear_color
= swizzle_color_value(clear_color
, swizzle
);
408 swizzle
= ISL_SWIZZLE_IDENTITY
;
410 bool clear_rgb_as_red
= false;
411 if (format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
412 clear_color
.u32
[0] = float3_to_rgb9e5(clear_color
.f32
);
413 format
= ISL_FORMAT_R32_UINT
;
414 } else if (format
== ISL_FORMAT_L8_UNORM_SRGB
) {
415 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
416 format
= ISL_FORMAT_R8_UNORM
;
417 } else if (format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
418 /* Broadwell and earlier cannot render to this format so we need to work
419 * around it by swapping the colors around and using B4G4R4A4 instead.
421 const struct isl_swizzle ARGB
= ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
);
422 clear_color
= swizzle_color_value(clear_color
, ARGB
);
423 format
= ISL_FORMAT_B4G4R4A4_UNORM
;
424 } else if (isl_format_get_layout(format
)->bpb
% 3 == 0) {
425 clear_rgb_as_red
= true;
426 if (format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
) {
427 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
428 clear_color
.f32
[1] = util_format_linear_to_srgb_float(clear_color
.f32
[1]);
429 clear_color
.f32
[2] = util_format_linear_to_srgb_float(clear_color
.f32
[2]);
433 memcpy(¶ms
.wm_inputs
.clear_color
, clear_color
.f32
, sizeof(float) * 4);
435 bool use_simd16_replicated_data
= true;
437 /* From the SNB PRM (Vol4_Part1):
439 * "Replicated data (Message Type = 111) is only supported when
440 * accessing tiled memory. Using this Message Type to access linear
441 * (untiled) memory is UNDEFINED."
443 if (surf
->surf
->tiling
== ISL_TILING_LINEAR
)
444 use_simd16_replicated_data
= false;
446 /* Replicated clears don't work yet before gen6 */
447 if (batch
->blorp
->isl_dev
->info
->gen
< 6)
448 use_simd16_replicated_data
= false;
450 /* Constant color writes ignore everyting in blend and color calculator
451 * state. This is not documented.
453 if (color_write_disable
) {
454 for (unsigned i
= 0; i
< 4; i
++) {
455 params
.color_write_disable
[i
] = color_write_disable
[i
];
456 if (color_write_disable
[i
])
457 use_simd16_replicated_data
= false;
461 if (!blorp_params_get_clear_kernel(batch
, ¶ms
,
462 use_simd16_replicated_data
,
466 if (!blorp_ensure_sf_program(batch
, ¶ms
))
469 while (num_layers
> 0) {
470 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
471 start_layer
, format
, true);
472 params
.dst
.view
.swizzle
= swizzle
;
479 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
480 assert(params
.dst
.surf
.samples
== 1);
481 assert(num_layers
== 1);
482 params
.x0
+= params
.dst
.tile_x_sa
;
483 params
.y0
+= params
.dst
.tile_y_sa
;
484 params
.x1
+= params
.dst
.tile_x_sa
;
485 params
.y1
+= params
.dst
.tile_y_sa
;
488 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
489 * Convert them to a single slice on gen4.
491 if (batch
->blorp
->isl_dev
->info
->gen
== 4 &&
492 (params
.dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
)) {
493 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
.dst
);
496 if (clear_rgb_as_red
) {
497 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
.dst
);
502 if (isl_format_is_compressed(params
.dst
.surf
.format
)) {
503 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
504 NULL
, NULL
, NULL
, NULL
);
505 //&dst_x, &dst_y, &dst_w, &dst_h);
508 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
509 /* Either we're on gen4 where there is no multisampling or the
510 * surface is compressed which also implies no multisampling.
511 * Therefore, sa == px and we don't need to do a conversion.
513 assert(params
.dst
.surf
.samples
== 1);
514 params
.x0
+= params
.dst
.tile_x_sa
;
515 params
.y0
+= params
.dst
.tile_y_sa
;
516 params
.x1
+= params
.dst
.tile_x_sa
;
517 params
.y1
+= params
.dst
.tile_y_sa
;
520 params
.num_samples
= params
.dst
.surf
.samples
;
522 /* We may be restricted on the number of layers we can bind at any one
523 * time. In particular, Sandy Bridge has a maximum number of layers of
524 * 512 but a maximum 3D texture size is much larger.
526 params
.num_layers
= MIN2(params
.dst
.view
.array_len
, num_layers
);
528 const unsigned max_image_width
= 16 * 1024;
529 if (params
.dst
.surf
.logical_level0_px
.width
> max_image_width
) {
530 /* Clearing an RGB image as red multiplies the surface width by 3
531 * so it may now be too wide for the hardware surface limits. We
532 * have to break the clear up into pieces in order to clear wide
535 assert(clear_rgb_as_red
);
536 assert(params
.dst
.surf
.dim
== ISL_SURF_DIM_2D
);
537 assert(params
.dst
.surf
.tiling
== ISL_TILING_LINEAR
);
538 assert(params
.dst
.surf
.logical_level0_px
.depth
== 1);
539 assert(params
.dst
.surf
.logical_level0_px
.array_len
== 1);
540 assert(params
.dst
.surf
.levels
== 1);
541 assert(params
.dst
.surf
.samples
== 1);
542 assert(params
.dst
.tile_x_sa
== 0 || params
.dst
.tile_y_sa
== 0);
543 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
);
545 /* max_image_width rounded down to a multiple of 3 */
546 const unsigned max_fake_rgb_width
= (max_image_width
/ 3) * 3;
548 isl_format_get_layout(params
.dst
.surf
.format
)->bpb
/ 8;
550 params
.dst
.surf
.logical_level0_px
.width
= max_fake_rgb_width
;
551 params
.dst
.surf
.phys_level0_sa
.width
= max_fake_rgb_width
;
553 uint32_t orig_x0
= params
.x0
, orig_x1
= params
.x1
;
554 uint64_t orig_offset
= params
.dst
.addr
.offset
;
555 for (uint32_t x
= orig_x0
; x
< orig_x1
; x
+= max_fake_rgb_width
) {
556 /* Offset to the surface. It's easy because we're linear */
557 params
.dst
.addr
.offset
= orig_offset
+ x
* cpp
;
560 params
.x1
= MIN2(orig_x1
- x
, max_image_width
);
562 batch
->blorp
->exec(batch
, ¶ms
);
565 batch
->blorp
->exec(batch
, ¶ms
);
568 start_layer
+= params
.num_layers
;
569 num_layers
-= params
.num_layers
;
574 blorp_clear_depth_stencil(struct blorp_batch
*batch
,
575 const struct blorp_surf
*depth
,
576 const struct blorp_surf
*stencil
,
577 uint32_t level
, uint32_t start_layer
,
579 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
580 bool clear_depth
, float depth_value
,
581 uint8_t stencil_mask
, uint8_t stencil_value
)
583 struct blorp_params params
;
584 blorp_params_init(¶ms
);
591 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) == 6) {
592 /* For some reason, Sandy Bridge gets occlusion queries wrong if we
593 * don't have a shader. In particular, it records samples even though
594 * we disable statistics in 3DSTATE_WM. Give it the usual clear shader
595 * to work around the issue.
597 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, false, false))
601 while (num_layers
> 0) {
602 params
.num_layers
= num_layers
;
605 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
607 ISL_FORMAT_UNSUPPORTED
, true);
608 params
.stencil_mask
= stencil_mask
;
609 params
.stencil_ref
= stencil_value
;
611 params
.dst
.surf
.samples
= params
.stencil
.surf
.samples
;
612 params
.dst
.surf
.logical_level0_px
=
613 params
.stencil
.surf
.logical_level0_px
;
614 params
.dst
.view
= params
.depth
.view
;
616 params
.num_samples
= params
.stencil
.surf
.samples
;
618 /* We may be restricted on the number of layers we can bind at any
619 * one time. In particular, Sandy Bridge has a maximum number of
620 * layers of 512 but a maximum 3D texture size is much larger.
622 if (params
.stencil
.view
.array_len
< params
.num_layers
)
623 params
.num_layers
= params
.stencil
.view
.array_len
;
627 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
629 ISL_FORMAT_UNSUPPORTED
, true);
630 params
.z
= depth_value
;
631 params
.depth_format
=
632 isl_format_get_depth_format(depth
->surf
->format
, false);
634 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
635 params
.dst
.surf
.logical_level0_px
=
636 params
.depth
.surf
.logical_level0_px
;
637 params
.dst
.view
= params
.depth
.view
;
639 params
.num_samples
= params
.depth
.surf
.samples
;
641 /* We may be restricted on the number of layers we can bind at any
642 * one time. In particular, Sandy Bridge has a maximum number of
643 * layers of 512 but a maximum 3D texture size is much larger.
645 if (params
.depth
.view
.array_len
< params
.num_layers
)
646 params
.num_layers
= params
.depth
.view
.array_len
;
649 batch
->blorp
->exec(batch
, ¶ms
);
651 start_layer
+= params
.num_layers
;
652 num_layers
-= params
.num_layers
;
657 blorp_can_hiz_clear_depth(uint8_t gen
, enum isl_format format
,
658 uint32_t num_samples
,
659 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
661 /* This function currently doesn't support any gen prior to gen8 */
664 if (gen
== 8 && format
== ISL_FORMAT_R16_UNORM
) {
665 /* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample
666 * block with the following property: as the number of samples increases,
667 * the number of pixels representable by this block decreases by a factor
668 * of the sample dimensions. Sample dimensions scale following the MSAA
669 * interleaved pattern.
671 * Sample|Sample|Pixel
673 * ===================
680 * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
682 const struct isl_extent2d sa_block_dim
=
683 isl_get_interleaved_msaa_px_size_sa(num_samples
);
684 const uint8_t align_px_w
= 8 / sa_block_dim
.w
;
685 const uint8_t align_px_h
= 4 / sa_block_dim
.h
;
687 /* Fast depth clears clear an entire sample block at a time. As a result,
688 * the rectangle must be aligned to the dimensions of the encompassing
689 * pixel block for a successful operation.
691 * Fast clears can still work if the upper-left corner is aligned and the
692 * bottom-rigtht corner touches the edge of a depth buffer whose extent
693 * is unaligned. This is because each miplevel in the depth buffer is
694 * padded by the Pixel Dim (similar to a standard compressed texture).
695 * In this case, the clear rectangle could be padded by to match the full
696 * depth buffer extent but to support multiple clearing techniques, we
697 * chose to be unaware of the depth buffer's extent and thus don't handle
700 if (x0
% align_px_w
|| y0
% align_px_h
||
701 x1
% align_px_w
|| y1
% align_px_h
)
708 blorp_hiz_clear_depth_stencil(struct blorp_batch
*batch
,
709 const struct blorp_surf
*depth
,
710 const struct blorp_surf
*stencil
,
712 uint32_t start_layer
, uint32_t num_layers
,
713 uint32_t x0
, uint32_t y0
,
714 uint32_t x1
, uint32_t y1
,
715 bool clear_depth
, float depth_value
,
716 bool clear_stencil
, uint8_t stencil_value
)
718 struct blorp_params params
;
719 blorp_params_init(¶ms
);
721 /* This requires WM_HZ_OP which only exists on gen8+ */
722 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8);
724 params
.hiz_op
= ISL_AUX_OP_FAST_CLEAR
;
725 params
.num_layers
= 1;
732 for (uint32_t l
= 0; l
< num_layers
; l
++) {
733 const uint32_t layer
= start_layer
+ l
;
735 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
737 ISL_FORMAT_UNSUPPORTED
, true);
738 params
.stencil_mask
= 0xff;
739 params
.stencil_ref
= stencil_value
;
740 params
.num_samples
= params
.stencil
.surf
.samples
;
744 /* If we're clearing depth, we must have HiZ */
745 assert(depth
&& depth
->aux_usage
== ISL_AUX_USAGE_HIZ
);
747 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
749 ISL_FORMAT_UNSUPPORTED
, true);
750 params
.depth
.clear_color
.f32
[0] = depth_value
;
751 params
.depth_format
=
752 isl_format_get_depth_format(depth
->surf
->format
, false);
753 params
.num_samples
= params
.depth
.surf
.samples
;
756 batch
->blorp
->exec(batch
, ¶ms
);
760 /* Given a depth stencil attachment, this function performs a fast depth clear
761 * on a depth portion and a regular clear on the stencil portion. When
762 * performing a fast depth clear on the depth portion, the HiZ buffer is simply
763 * tagged as cleared so the depth clear value is not actually needed.
766 blorp_gen8_hiz_clear_attachments(struct blorp_batch
*batch
,
767 uint32_t num_samples
,
768 uint32_t x0
, uint32_t y0
,
769 uint32_t x1
, uint32_t y1
,
770 bool clear_depth
, bool clear_stencil
,
771 uint8_t stencil_value
)
773 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
775 struct blorp_params params
;
776 blorp_params_init(¶ms
);
777 params
.num_layers
= 1;
778 params
.hiz_op
= ISL_AUX_OP_FAST_CLEAR
;
783 params
.num_samples
= num_samples
;
784 params
.depth
.enabled
= clear_depth
;
785 params
.stencil
.enabled
= clear_stencil
;
786 params
.stencil_ref
= stencil_value
;
787 batch
->blorp
->exec(batch
, ¶ms
);
790 /** Clear active color/depth/stencili attachments
792 * This function performs a clear operation on the currently bound
793 * color/depth/stencil attachments. It is assumed that any information passed
794 * in here is valid, consistent, and in-bounds relative to the currently
795 * attached depth/stencil. The binding_table_offset parameter is the 32-bit
796 * offset relative to surface state base address where pre-baked binding table
797 * that we are to use lives. If clear_color is false, binding_table_offset
798 * must point to a binding table with one entry which is a valid null surface
799 * that matches the currently bound depth and stencil.
802 blorp_clear_attachments(struct blorp_batch
*batch
,
803 uint32_t binding_table_offset
,
804 enum isl_format depth_format
,
805 uint32_t num_samples
,
806 uint32_t start_layer
, uint32_t num_layers
,
807 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
808 bool clear_color
, union isl_color_value color_value
,
809 bool clear_depth
, float depth_value
,
810 uint8_t stencil_mask
, uint8_t stencil_value
)
812 struct blorp_params params
;
813 blorp_params_init(¶ms
);
815 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
822 params
.use_pre_baked_binding_table
= true;
823 params
.pre_baked_binding_table_offset
= binding_table_offset
;
825 params
.num_layers
= num_layers
;
826 params
.num_samples
= num_samples
;
829 params
.dst
.enabled
= true;
831 memcpy(¶ms
.wm_inputs
.clear_color
, color_value
.f32
, sizeof(float) * 4);
833 /* Unfortunately, without knowing whether or not our destination surface
834 * is tiled or not, we have to assume it may be linear. This means no
835 * SIMD16_REPDATA for us. :-(
837 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, false, false))
842 params
.depth
.enabled
= true;
844 params
.z
= depth_value
;
845 params
.depth_format
= isl_format_get_depth_format(depth_format
, false);
849 params
.stencil
.enabled
= true;
851 params
.stencil_mask
= stencil_mask
;
852 params
.stencil_ref
= stencil_value
;
855 if (!blorp_params_get_layer_offset_vs(batch
, ¶ms
))
858 params
.vs_inputs
.base_layer
= start_layer
;
860 batch
->blorp
->exec(batch
, ¶ms
);
864 blorp_ccs_resolve(struct blorp_batch
*batch
,
865 struct blorp_surf
*surf
, uint32_t level
,
866 uint32_t start_layer
, uint32_t num_layers
,
867 enum isl_format format
,
868 enum isl_aux_op resolve_op
)
870 struct blorp_params params
;
872 blorp_params_init(¶ms
);
873 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
,
874 level
, start_layer
, format
, true);
876 /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
878 * A rectangle primitive must be scaled down by the following factors
879 * with respect to render target being resolved.
881 * The scaledown factors in the table that follows are related to the block
882 * size of the CCS format. For IVB and HSW, we divide by two, for BDW we
883 * multiply by 8 and 16. On Sky Lake, we multiply by 8.
885 const struct isl_format_layout
*aux_fmtl
=
886 isl_format_get_layout(params
.dst
.aux_surf
.format
);
887 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
889 unsigned x_scaledown
, y_scaledown
;
890 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 9) {
891 x_scaledown
= aux_fmtl
->bw
* 8;
892 y_scaledown
= aux_fmtl
->bh
* 8;
893 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
894 x_scaledown
= aux_fmtl
->bw
* 8;
895 y_scaledown
= aux_fmtl
->bh
* 16;
897 x_scaledown
= aux_fmtl
->bw
/ 2;
898 y_scaledown
= aux_fmtl
->bh
/ 2;
900 params
.x0
= params
.y0
= 0;
901 params
.x1
= minify(params
.dst
.aux_surf
.logical_level0_px
.width
, level
);
902 params
.y1
= minify(params
.dst
.aux_surf
.logical_level0_px
.height
, level
);
903 params
.x1
= ALIGN(params
.x1
, x_scaledown
) / x_scaledown
;
904 params
.y1
= ALIGN(params
.y1
, y_scaledown
) / y_scaledown
;
906 if (batch
->blorp
->isl_dev
->info
->gen
>= 10) {
907 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
||
908 resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
||
909 resolve_op
== ISL_AUX_OP_AMBIGUATE
);
910 } else if (batch
->blorp
->isl_dev
->info
->gen
>= 9) {
911 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
||
912 resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
914 /* Broadwell and earlier do not have a partial resolve */
915 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
);
917 params
.fast_clear_op
= resolve_op
;
918 params
.num_layers
= num_layers
;
920 /* Note: there is no need to initialize push constants because it doesn't
921 * matter what data gets dispatched to the render target. However, we must
922 * ensure that the fragment shader delivers the data using the "replicated
926 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
929 batch
->blorp
->exec(batch
, ¶ms
);
933 blorp_nir_bit(nir_builder
*b
, nir_ssa_def
*src
, unsigned bit
)
935 return nir_iand(b
, nir_ushr(b
, src
, nir_imm_int(b
, bit
)),
939 struct blorp_mcs_partial_resolve_key
941 enum blorp_shader_type shader_type
;
942 bool indirect_clear_color
;
944 uint32_t num_samples
;
948 blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch
*batch
,
949 struct blorp_params
*params
)
951 struct blorp_context
*blorp
= batch
->blorp
;
952 const struct blorp_mcs_partial_resolve_key blorp_key
= {
953 .shader_type
= BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE
,
954 .indirect_clear_color
= params
->dst
.clear_color_addr
.buffer
!= NULL
,
955 .int_format
= isl_format_has_int_channel(params
->dst
.view
.format
),
956 .num_samples
= params
->num_samples
,
959 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
960 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
963 void *mem_ctx
= ralloc_context(NULL
);
966 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
,
967 "BLORP-mcs-partial-resolve");
969 nir_variable
*v_color
=
970 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
972 nir_variable
*frag_color
=
973 nir_variable_create(b
.shader
, nir_var_shader_out
,
974 glsl_vec4_type(), "gl_FragColor");
975 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
977 /* Do an MCS fetch and check if it is equal to the magic clear value */
979 blorp_nir_txf_ms_mcs(&b
, nir_f2i32(&b
, blorp_nir_frag_coord(&b
)),
980 nir_load_layer_id(&b
));
981 nir_ssa_def
*is_clear
=
982 blorp_nir_mcs_is_clear_color(&b
, mcs
, blorp_key
.num_samples
);
984 /* If we aren't the clear value, discard. */
985 nir_intrinsic_instr
*discard
=
986 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_discard_if
);
987 discard
->src
[0] = nir_src_for_ssa(nir_inot(&b
, is_clear
));
988 nir_builder_instr_insert(&b
, &discard
->instr
);
990 nir_ssa_def
*clear_color
= nir_load_var(&b
, v_color
);
991 if (blorp_key
.indirect_clear_color
&& blorp
->isl_dev
->info
->gen
<= 8) {
992 /* Gen7-8 clear colors are stored as single 0/1 bits */
993 clear_color
= nir_vec4(&b
, blorp_nir_bit(&b
, clear_color
, 31),
994 blorp_nir_bit(&b
, clear_color
, 30),
995 blorp_nir_bit(&b
, clear_color
, 29),
996 blorp_nir_bit(&b
, clear_color
, 28));
998 if (!blorp_key
.int_format
)
999 clear_color
= nir_i2f32(&b
, clear_color
);
1001 nir_store_var(&b
, frag_color
, clear_color
, 0xf);
1003 struct brw_wm_prog_key wm_key
;
1004 brw_blorp_init_wm_prog_key(&wm_key
);
1005 wm_key
.tex
.compressed_multisample_layout_mask
= 1;
1006 wm_key
.tex
.msaa_16
= blorp_key
.num_samples
== 16;
1007 wm_key
.multisample_fbo
= true;
1009 struct brw_wm_prog_data prog_data
;
1010 const unsigned *program
=
1011 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, false,
1015 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
1016 program
, prog_data
.base
.program_size
,
1017 &prog_data
.base
, sizeof(prog_data
),
1018 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1020 ralloc_free(mem_ctx
);
1025 blorp_mcs_partial_resolve(struct blorp_batch
*batch
,
1026 struct blorp_surf
*surf
,
1027 enum isl_format format
,
1028 uint32_t start_layer
, uint32_t num_layers
)
1030 struct blorp_params params
;
1031 blorp_params_init(¶ms
);
1033 assert(batch
->blorp
->isl_dev
->info
->gen
>= 7);
1037 params
.x1
= surf
->surf
->logical_level0_px
.width
;
1038 params
.y1
= surf
->surf
->logical_level0_px
.height
;
1040 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, surf
, 0,
1041 start_layer
, format
, false);
1042 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, 0,
1043 start_layer
, format
, true);
1045 params
.num_samples
= params
.dst
.surf
.samples
;
1046 params
.num_layers
= num_layers
;
1047 params
.dst_clear_color_as_input
= surf
->clear_color_addr
.buffer
!= NULL
;
1049 memcpy(¶ms
.wm_inputs
.clear_color
,
1050 surf
->clear_color
.f32
, sizeof(float) * 4);
1052 if (!blorp_params_get_mcs_partial_resolve_kernel(batch
, ¶ms
))
1055 batch
->blorp
->exec(batch
, ¶ms
);
1058 /** Clear a CCS to the "uncompressed" state
1060 * This pass is the CCS equivalent of a "HiZ resolve". It sets the CCS values
1061 * for a given layer/level of a surface to 0x0 which is the "uncompressed"
1062 * state which tells the sampler to go look at the main surface.
1065 blorp_ccs_ambiguate(struct blorp_batch
*batch
,
1066 struct blorp_surf
*surf
,
1067 uint32_t level
, uint32_t layer
)
1069 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 10) {
1070 /* On gen10 and above, we have a hardware resolve op for this */
1071 return blorp_ccs_resolve(batch
, surf
, level
, layer
, 1,
1072 surf
->surf
->format
, ISL_AUX_OP_AMBIGUATE
);
1075 struct blorp_params params
;
1076 blorp_params_init(¶ms
);
1078 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 7);
1080 const struct isl_format_layout
*aux_fmtl
=
1081 isl_format_get_layout(surf
->aux_surf
->format
);
1082 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
1084 params
.dst
= (struct brw_blorp_surface_info
) {
1086 .addr
= surf
->aux_addr
,
1088 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1089 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
1091 .base_array_layer
= 0,
1094 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1099 if (surf
->surf
->dim
== ISL_SURF_DIM_3D
) {
1104 uint32_t offset_B
, x_offset_el
, y_offset_el
;
1105 isl_surf_get_image_offset_el(surf
->aux_surf
, level
, layer
, z
,
1106 &x_offset_el
, &y_offset_el
);
1107 isl_tiling_get_intratile_offset_el(surf
->aux_surf
->tiling
, aux_fmtl
->bpb
,
1108 surf
->aux_surf
->row_pitch_B
,
1109 x_offset_el
, y_offset_el
,
1110 &offset_B
, &x_offset_el
, &y_offset_el
);
1111 params
.dst
.addr
.offset
+= offset_B
;
1113 const uint32_t width_px
=
1114 minify(surf
->aux_surf
->logical_level0_px
.width
, level
);
1115 const uint32_t height_px
=
1116 minify(surf
->aux_surf
->logical_level0_px
.height
, level
);
1117 const uint32_t width_el
= DIV_ROUND_UP(width_px
, aux_fmtl
->bw
);
1118 const uint32_t height_el
= DIV_ROUND_UP(height_px
, aux_fmtl
->bh
);
1120 struct isl_tile_info ccs_tile_info
;
1121 isl_surf_get_tile_info(surf
->aux_surf
, &ccs_tile_info
);
1123 /* We're going to map it as a regular RGBA32_UINT surface. We need to
1124 * downscale a good deal. We start by computing the area on the CCS to
1125 * clear in units of Y-tiled cache lines.
1127 uint32_t x_offset_cl
, y_offset_cl
, width_cl
, height_cl
;
1128 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
1129 /* From the Sky Lake PRM Vol. 12 in the section on planes:
1131 * "The Color Control Surface (CCS) contains the compression status
1132 * of the cache-line pairs. The compression state of the cache-line
1133 * pair is specified by 2 bits in the CCS. Each CCS cache-line
1134 * represents an area on the main surface of 16x16 sets of 128 byte
1135 * Y-tiled cache-line-pairs. CCS is always Y tiled."
1137 * Each 2-bit surface element in the CCS corresponds to a single
1138 * cache-line pair in the main surface. This means that 16x16 el block
1139 * in the CCS maps to a Y-tiled cache line. Fortunately, CCS layouts
1140 * are calculated with a very large alignment so we can round up to a
1141 * whole cache line without worrying about overdraw.
1144 /* On Broadwell and above, a CCS tile is the same as a Y tile when
1145 * viewed at the cache-line granularity. Fortunately, the horizontal
1146 * and vertical alignment requirements of the CCS are such that we can
1147 * align to an entire cache line without worrying about crossing over
1148 * from one LOD to another.
1150 const uint32_t x_el_per_cl
= ccs_tile_info
.logical_extent_el
.w
/ 8;
1151 const uint32_t y_el_per_cl
= ccs_tile_info
.logical_extent_el
.h
/ 8;
1152 assert(surf
->aux_surf
->image_alignment_el
.w
% x_el_per_cl
== 0);
1153 assert(surf
->aux_surf
->image_alignment_el
.h
% y_el_per_cl
== 0);
1155 assert(x_offset_el
% x_el_per_cl
== 0);
1156 assert(y_offset_el
% y_el_per_cl
== 0);
1157 x_offset_cl
= x_offset_el
/ x_el_per_cl
;
1158 y_offset_cl
= y_offset_el
/ y_el_per_cl
;
1159 width_cl
= DIV_ROUND_UP(width_el
, x_el_per_cl
);
1160 height_cl
= DIV_ROUND_UP(height_el
, y_el_per_cl
);
1162 /* On gen7, the CCS tiling is not so nice. However, there we are
1163 * guaranteed that we only have a single level and slice so we don't
1164 * have to worry about it and can just align to a whole tile.
1166 assert(surf
->aux_surf
->logical_level0_px
.depth
== 1);
1167 assert(surf
->aux_surf
->logical_level0_px
.array_len
== 1);
1168 assert(x_offset_el
== 0 && y_offset_el
== 0);
1169 const uint32_t width_tl
=
1170 DIV_ROUND_UP(width_el
, ccs_tile_info
.logical_extent_el
.w
);
1171 const uint32_t height_tl
=
1172 DIV_ROUND_UP(height_el
, ccs_tile_info
.logical_extent_el
.h
);
1175 width_cl
= width_tl
* 8;
1176 height_cl
= height_tl
* 8;
1179 /* We're going to use a RGBA32 format so as to write data as quickly as
1180 * possible. A y-tiled cache line will then be 1x4 px.
1182 const uint32_t x_offset_rgba_px
= x_offset_cl
;
1183 const uint32_t y_offset_rgba_px
= y_offset_cl
* 4;
1184 const uint32_t width_rgba_px
= width_cl
;
1185 const uint32_t height_rgba_px
= height_cl
* 4;
1187 MAYBE_UNUSED
bool ok
=
1188 isl_surf_init(batch
->blorp
->isl_dev
, ¶ms
.dst
.surf
,
1189 .dim
= ISL_SURF_DIM_2D
,
1190 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
1191 .width
= width_rgba_px
+ x_offset_rgba_px
,
1192 .height
= height_rgba_px
+ y_offset_rgba_px
,
1197 .row_pitch_B
= surf
->aux_surf
->row_pitch_B
,
1198 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1199 .tiling_flags
= ISL_TILING_Y0_BIT
);
1202 params
.x0
= x_offset_rgba_px
;
1203 params
.y0
= y_offset_rgba_px
;
1204 params
.x1
= x_offset_rgba_px
+ width_rgba_px
;
1205 params
.y1
= y_offset_rgba_px
+ height_rgba_px
;
1207 /* A CCS value of 0 means "uncompressed." */
1208 memset(¶ms
.wm_inputs
.clear_color
, 0,
1209 sizeof(params
.wm_inputs
.clear_color
));
1211 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
1214 batch
->blorp
->exec(batch
, ¶ms
);