2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/ralloc.h"
26 #include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
27 #include "util/format_rgb9e5.h"
28 #include "util/format_srgb.h"
30 #include "blorp_priv.h"
31 #include "compiler/brw_eu_defines.h"
33 #include "blorp_nir_builder.h"
35 #define FILE_DEBUG_FLAG DEBUG_BLORP
38 struct brw_blorp_const_color_prog_key
40 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_CLEAR */
41 bool use_simd16_replicated_data
;
42 bool clear_rgb_as_red
;
47 blorp_params_get_clear_kernel(struct blorp_batch
*batch
,
48 struct blorp_params
*params
,
49 bool use_replicated_data
,
50 bool clear_rgb_as_red
)
52 struct blorp_context
*blorp
= batch
->blorp
;
54 const struct brw_blorp_const_color_prog_key blorp_key
= {
55 .shader_type
= BLORP_SHADER_TYPE_CLEAR
,
56 .use_simd16_replicated_data
= use_replicated_data
,
57 .clear_rgb_as_red
= clear_rgb_as_red
,
60 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
61 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
64 void *mem_ctx
= ralloc_context(NULL
);
67 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, "BLORP-clear");
69 nir_variable
*v_color
=
70 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
71 nir_ssa_def
*color
= nir_load_var(&b
, v_color
);
73 if (clear_rgb_as_red
) {
74 nir_ssa_def
*pos
= nir_f2i32(&b
, nir_load_frag_coord(&b
));
75 nir_ssa_def
*comp
= nir_umod(&b
, nir_channel(&b
, pos
, 0),
77 nir_ssa_def
*color_component
=
78 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
79 nir_channel(&b
, color
, 0),
80 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
81 nir_channel(&b
, color
, 1),
82 nir_channel(&b
, color
, 2)));
84 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
85 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
88 nir_variable
*frag_color
= nir_variable_create(b
.shader
, nir_var_shader_out
,
91 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
92 nir_store_var(&b
, frag_color
, color
, 0xf);
94 struct brw_wm_prog_key wm_key
;
95 brw_blorp_init_wm_prog_key(&wm_key
);
97 struct brw_wm_prog_data prog_data
;
98 const unsigned *program
=
99 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, use_replicated_data
,
103 blorp
->upload_shader(batch
, MESA_SHADER_FRAGMENT
,
104 &blorp_key
, sizeof(blorp_key
),
105 program
, prog_data
.base
.program_size
,
106 &prog_data
.base
, sizeof(prog_data
),
107 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
109 ralloc_free(mem_ctx
);
113 #pragma pack(push, 1)
114 struct layer_offset_vs_key
{
115 enum blorp_shader_type shader_type
;
120 /* In the case of doing attachment clears, we are using a surface state that
121 * is handed to us so we can't set (and don't even know) the base array layer.
122 * In order to do a layered clear in this scenario, we need some way of adding
123 * the base array layer to the instance id. Unfortunately, our hardware has
124 * no real concept of "base instance", so we have to do it manually in a
128 blorp_params_get_layer_offset_vs(struct blorp_batch
*batch
,
129 struct blorp_params
*params
)
131 struct blorp_context
*blorp
= batch
->blorp
;
132 struct layer_offset_vs_key blorp_key
= {
133 .shader_type
= BLORP_SHADER_TYPE_LAYER_OFFSET_VS
,
136 if (params
->wm_prog_data
)
137 blorp_key
.num_inputs
= params
->wm_prog_data
->num_varying_inputs
;
139 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
140 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
))
143 void *mem_ctx
= ralloc_context(NULL
);
146 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_VERTEX
, "BLORP-layer-offset-vs");
148 const struct glsl_type
*uvec4_type
= glsl_vector_type(GLSL_TYPE_UINT
, 4);
150 /* First we deal with the header which has instance and base instance */
151 nir_variable
*a_header
= nir_variable_create(b
.shader
, nir_var_shader_in
,
152 uvec4_type
, "header");
153 a_header
->data
.location
= VERT_ATTRIB_GENERIC0
;
155 nir_variable
*v_layer
= nir_variable_create(b
.shader
, nir_var_shader_out
,
156 glsl_int_type(), "layer_id");
157 v_layer
->data
.location
= VARYING_SLOT_LAYER
;
159 /* Compute the layer id */
160 nir_ssa_def
*header
= nir_load_var(&b
, a_header
);
161 nir_ssa_def
*base_layer
= nir_channel(&b
, header
, 0);
162 nir_ssa_def
*instance
= nir_channel(&b
, header
, 1);
163 nir_store_var(&b
, v_layer
, nir_iadd(&b
, instance
, base_layer
), 0x1);
165 /* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
166 nir_variable
*a_vertex
= nir_variable_create(b
.shader
, nir_var_shader_in
,
167 glsl_vec4_type(), "a_vertex");
168 a_vertex
->data
.location
= VERT_ATTRIB_GENERIC1
;
170 nir_variable
*v_pos
= nir_variable_create(b
.shader
, nir_var_shader_out
,
171 glsl_vec4_type(), "v_pos");
172 v_pos
->data
.location
= VARYING_SLOT_POS
;
174 nir_copy_var(&b
, v_pos
, a_vertex
);
176 /* Then we copy everything else */
177 for (unsigned i
= 0; i
< blorp_key
.num_inputs
; i
++) {
178 nir_variable
*a_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
179 uvec4_type
, "input");
180 a_in
->data
.location
= VERT_ATTRIB_GENERIC2
+ i
;
182 nir_variable
*v_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
183 uvec4_type
, "output");
184 v_out
->data
.location
= VARYING_SLOT_VAR0
+ i
;
186 nir_copy_var(&b
, v_out
, a_in
);
189 struct brw_vs_prog_data vs_prog_data
;
190 memset(&vs_prog_data
, 0, sizeof(vs_prog_data
));
192 const unsigned *program
=
193 blorp_compile_vs(blorp
, mem_ctx
, b
.shader
, &vs_prog_data
);
196 blorp
->upload_shader(batch
, MESA_SHADER_VERTEX
,
197 &blorp_key
, sizeof(blorp_key
),
198 program
, vs_prog_data
.base
.base
.program_size
,
199 &vs_prog_data
.base
.base
, sizeof(vs_prog_data
),
200 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
);
202 ralloc_free(mem_ctx
);
206 /* The x0, y0, x1, and y1 parameters must already be populated with the render
207 * area of the framebuffer to be cleared.
210 get_fast_clear_rect(const struct isl_device
*dev
,
211 const struct isl_surf
*aux_surf
,
212 unsigned *x0
, unsigned *y0
,
213 unsigned *x1
, unsigned *y1
)
215 unsigned int x_align
, y_align
;
216 unsigned int x_scaledown
, y_scaledown
;
218 /* Only single sampled surfaces need to (and actually can) be resolved. */
219 if (aux_surf
->usage
== ISL_SURF_USAGE_CCS_BIT
) {
220 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
221 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
223 * Clear pass must have a clear rectangle that must follow
224 * alignment rules in terms of pixels and lines as shown in the
225 * table below. Further, the clear-rectangle height and width
226 * must be multiple of the following dimensions. If the height
227 * and width of the render target being cleared do not meet these
228 * requirements, an MCS buffer can be created such that it
229 * follows the requirement and covers the RT.
231 * The alignment size in the table that follows is related to the
232 * alignment size that is baked into the CCS surface format but with X
233 * alignment multiplied by 16 and Y alignment multiplied by 32.
235 x_align
= isl_format_get_layout(aux_surf
->format
)->bw
;
236 y_align
= isl_format_get_layout(aux_surf
->format
)->bh
;
240 /* The line alignment requirement for Y-tiled is halved at SKL and again
243 if (dev
->info
->gen
>= 12)
245 else if (dev
->info
->gen
>= 9)
250 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
251 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
253 * In order to optimize the performance MCS buffer (when bound to
254 * 1X RT) clear similarly to MCS buffer clear for MSRT case,
255 * clear rect is required to be scaled by the following factors
256 * in the horizontal and vertical directions:
258 * The X and Y scale down factors in the table that follows are each
259 * equal to half the alignment value computed above.
261 x_scaledown
= x_align
/ 2;
262 y_scaledown
= y_align
/ 2;
264 if (ISL_DEV_IS_HASWELL(dev
)) {
265 /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
266 * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
267 * Clear of Non-MultiSampled Render Target Restrictions":
269 * Clear rectangle must be aligned to two times the number of
270 * pixels in the table shown below due to 16x16 hashing across the
273 * This restriction is only documented to exist on HSW GT3 but
274 * empirical evidence suggests that it's also needed GT2.
280 assert(aux_surf
->usage
== ISL_SURF_USAGE_MCS_BIT
);
282 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
283 * Target(s)", beneath the "MSAA Compression" bullet (p326):
285 * Clear pass for this case requires that scaled down primitive
286 * is sent down with upper left co-ordinate to coincide with
287 * actual rectangle being cleared. For MSAA, clear rectangle’s
288 * height and width need to as show in the following table in
289 * terms of (width,height) of the RT.
291 * MSAA Width of Clear Rect Height of Clear Rect
292 * 2X Ceil(1/8*width) Ceil(1/2*height)
293 * 4X Ceil(1/8*width) Ceil(1/2*height)
294 * 8X Ceil(1/2*width) Ceil(1/2*height)
295 * 16X width Ceil(1/2*height)
297 * The text "with upper left co-ordinate to coincide with actual
298 * rectangle being cleared" is a little confusing--it seems to imply
299 * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
300 * feed the pipeline using the rectangle (x,y) to
301 * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
302 * the number of samples. Experiments indicate that this is not
303 * quite correct; actually, what the hardware appears to do is to
304 * align whatever rectangle is sent down the pipeline to the nearest
305 * multiple of 2x2 blocks, and then scale it up by a factor of N
306 * horizontally and 2 vertically. So the resulting alignment is 4
307 * vertically and either 4 or 16 horizontally, and the scaledown
308 * factor is 2 vertically and either 2 or 8 horizontally.
310 switch (aux_surf
->format
) {
311 case ISL_FORMAT_MCS_2X
:
312 case ISL_FORMAT_MCS_4X
:
315 case ISL_FORMAT_MCS_8X
:
318 case ISL_FORMAT_MCS_16X
:
322 unreachable("Unexpected MCS format for fast clear");
325 x_align
= x_scaledown
* 2;
326 y_align
= y_scaledown
* 2;
329 *x0
= ROUND_DOWN_TO(*x0
, x_align
) / x_scaledown
;
330 *y0
= ROUND_DOWN_TO(*y0
, y_align
) / y_scaledown
;
331 *x1
= ALIGN(*x1
, x_align
) / x_scaledown
;
332 *y1
= ALIGN(*y1
, y_align
) / y_scaledown
;
336 blorp_fast_clear(struct blorp_batch
*batch
,
337 const struct blorp_surf
*surf
, enum isl_format format
,
338 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
339 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
341 struct blorp_params params
;
342 blorp_params_init(¶ms
);
343 params
.num_layers
= num_layers
;
350 memset(¶ms
.wm_inputs
.clear_color
, 0xff, 4*sizeof(float));
351 params
.fast_clear_op
= ISL_AUX_OP_FAST_CLEAR
;
353 get_fast_clear_rect(batch
->blorp
->isl_dev
, surf
->aux_surf
,
354 ¶ms
.x0
, ¶ms
.y0
, ¶ms
.x1
, ¶ms
.y1
);
356 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
359 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
360 start_layer
, format
, true);
361 params
.num_samples
= params
.dst
.surf
.samples
;
363 batch
->blorp
->exec(batch
, ¶ms
);
366 union isl_color_value
367 swizzle_color_value(union isl_color_value src
, struct isl_swizzle swizzle
)
369 union isl_color_value dst
= { .u32
= { 0, } };
371 /* We assign colors in ABGR order so that the first one will be taken in
372 * RGBA precedence order. According to the PRM docs for shader channel
373 * select, this matches Haswell hardware behavior.
375 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
376 dst
.u32
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[3];
377 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
378 dst
.u32
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[2];
379 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
380 dst
.u32
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[1];
381 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
382 dst
.u32
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[0];
388 blorp_clear(struct blorp_batch
*batch
,
389 const struct blorp_surf
*surf
,
390 enum isl_format format
, struct isl_swizzle swizzle
,
391 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
392 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
393 union isl_color_value clear_color
,
394 const bool color_write_disable
[4])
396 struct blorp_params params
;
397 blorp_params_init(¶ms
);
399 /* Manually apply the clear destination swizzle. This way swizzled clears
400 * will work for swizzles which we can't normally use for rendering and it
401 * also ensures that they work on pre-Haswell hardware which can't swizlle
404 clear_color
= swizzle_color_value(clear_color
, swizzle
);
405 swizzle
= ISL_SWIZZLE_IDENTITY
;
407 bool clear_rgb_as_red
= false;
408 if (format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
409 clear_color
.u32
[0] = float3_to_rgb9e5(clear_color
.f32
);
410 format
= ISL_FORMAT_R32_UINT
;
411 } else if (format
== ISL_FORMAT_L8_UNORM_SRGB
) {
412 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
413 format
= ISL_FORMAT_R8_UNORM
;
414 } else if (format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
415 /* Broadwell and earlier cannot render to this format so we need to work
416 * around it by swapping the colors around and using B4G4R4A4 instead.
418 const struct isl_swizzle ARGB
= ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
);
419 clear_color
= swizzle_color_value(clear_color
, ARGB
);
420 format
= ISL_FORMAT_B4G4R4A4_UNORM
;
421 } else if (isl_format_get_layout(format
)->bpb
% 3 == 0) {
422 clear_rgb_as_red
= true;
423 if (format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
) {
424 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
425 clear_color
.f32
[1] = util_format_linear_to_srgb_float(clear_color
.f32
[1]);
426 clear_color
.f32
[2] = util_format_linear_to_srgb_float(clear_color
.f32
[2]);
430 memcpy(¶ms
.wm_inputs
.clear_color
, clear_color
.f32
, sizeof(float) * 4);
432 bool use_simd16_replicated_data
= true;
434 /* From the SNB PRM (Vol4_Part1):
436 * "Replicated data (Message Type = 111) is only supported when
437 * accessing tiled memory. Using this Message Type to access linear
438 * (untiled) memory is UNDEFINED."
440 if (surf
->surf
->tiling
== ISL_TILING_LINEAR
)
441 use_simd16_replicated_data
= false;
443 /* Replicated clears don't work yet before gen6 */
444 if (batch
->blorp
->isl_dev
->info
->gen
< 6)
445 use_simd16_replicated_data
= false;
447 /* Constant color writes ignore everyting in blend and color calculator
448 * state. This is not documented.
450 if (color_write_disable
) {
451 for (unsigned i
= 0; i
< 4; i
++) {
452 params
.color_write_disable
[i
] = color_write_disable
[i
];
453 if (color_write_disable
[i
])
454 use_simd16_replicated_data
= false;
458 if (!blorp_params_get_clear_kernel(batch
, ¶ms
,
459 use_simd16_replicated_data
,
463 if (!blorp_ensure_sf_program(batch
, ¶ms
))
466 while (num_layers
> 0) {
467 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
468 start_layer
, format
, true);
469 params
.dst
.view
.swizzle
= swizzle
;
476 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
477 assert(params
.dst
.surf
.samples
== 1);
478 assert(num_layers
== 1);
479 params
.x0
+= params
.dst
.tile_x_sa
;
480 params
.y0
+= params
.dst
.tile_y_sa
;
481 params
.x1
+= params
.dst
.tile_x_sa
;
482 params
.y1
+= params
.dst
.tile_y_sa
;
485 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
486 * Convert them to a single slice on gen4.
488 if (batch
->blorp
->isl_dev
->info
->gen
== 4 &&
489 (params
.dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
)) {
490 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
.dst
);
493 if (clear_rgb_as_red
) {
494 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
.dst
);
499 if (isl_format_is_compressed(params
.dst
.surf
.format
)) {
500 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
501 NULL
, NULL
, NULL
, NULL
);
502 //&dst_x, &dst_y, &dst_w, &dst_h);
505 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
506 /* Either we're on gen4 where there is no multisampling or the
507 * surface is compressed which also implies no multisampling.
508 * Therefore, sa == px and we don't need to do a conversion.
510 assert(params
.dst
.surf
.samples
== 1);
511 params
.x0
+= params
.dst
.tile_x_sa
;
512 params
.y0
+= params
.dst
.tile_y_sa
;
513 params
.x1
+= params
.dst
.tile_x_sa
;
514 params
.y1
+= params
.dst
.tile_y_sa
;
517 params
.num_samples
= params
.dst
.surf
.samples
;
519 /* We may be restricted on the number of layers we can bind at any one
520 * time. In particular, Sandy Bridge has a maximum number of layers of
521 * 512 but a maximum 3D texture size is much larger.
523 params
.num_layers
= MIN2(params
.dst
.view
.array_len
, num_layers
);
525 const unsigned max_image_width
= 16 * 1024;
526 if (params
.dst
.surf
.logical_level0_px
.width
> max_image_width
) {
527 /* Clearing an RGB image as red multiplies the surface width by 3
528 * so it may now be too wide for the hardware surface limits. We
529 * have to break the clear up into pieces in order to clear wide
532 assert(clear_rgb_as_red
);
533 assert(params
.dst
.surf
.dim
== ISL_SURF_DIM_2D
);
534 assert(params
.dst
.surf
.tiling
== ISL_TILING_LINEAR
);
535 assert(params
.dst
.surf
.logical_level0_px
.depth
== 1);
536 assert(params
.dst
.surf
.logical_level0_px
.array_len
== 1);
537 assert(params
.dst
.surf
.levels
== 1);
538 assert(params
.dst
.surf
.samples
== 1);
539 assert(params
.dst
.tile_x_sa
== 0 || params
.dst
.tile_y_sa
== 0);
540 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
);
542 /* max_image_width rounded down to a multiple of 3 */
543 const unsigned max_fake_rgb_width
= (max_image_width
/ 3) * 3;
545 isl_format_get_layout(params
.dst
.surf
.format
)->bpb
/ 8;
547 params
.dst
.surf
.logical_level0_px
.width
= max_fake_rgb_width
;
548 params
.dst
.surf
.phys_level0_sa
.width
= max_fake_rgb_width
;
550 uint32_t orig_x0
= params
.x0
, orig_x1
= params
.x1
;
551 uint64_t orig_offset
= params
.dst
.addr
.offset
;
552 for (uint32_t x
= orig_x0
; x
< orig_x1
; x
+= max_fake_rgb_width
) {
553 /* Offset to the surface. It's easy because we're linear */
554 params
.dst
.addr
.offset
= orig_offset
+ x
* cpp
;
557 params
.x1
= MIN2(orig_x1
- x
, max_image_width
);
559 batch
->blorp
->exec(batch
, ¶ms
);
562 batch
->blorp
->exec(batch
, ¶ms
);
565 start_layer
+= params
.num_layers
;
566 num_layers
-= params
.num_layers
;
571 blorp_clear_stencil_as_rgba(struct blorp_batch
*batch
,
572 const struct blorp_surf
*surf
,
573 uint32_t level
, uint32_t start_layer
,
575 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
576 uint8_t stencil_mask
, uint8_t stencil_value
)
578 /* We only support separate W-tiled stencil for now */
579 if (surf
->surf
->format
!= ISL_FORMAT_R8_UINT
||
580 surf
->surf
->tiling
!= ISL_TILING_W
)
583 /* Stencil mask support would require piles of shader magic */
584 if (stencil_mask
!= 0xff)
587 if (surf
->surf
->samples
> 1) {
588 /* Adjust x0, y0, x1, and y1 to be in units of samples */
589 assert(surf
->surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
590 struct isl_extent2d msaa_px_size_sa
=
591 isl_get_interleaved_msaa_px_size_sa(surf
->surf
->samples
);
593 x0
*= msaa_px_size_sa
.w
;
594 y0
*= msaa_px_size_sa
.h
;
595 x1
*= msaa_px_size_sa
.w
;
596 y1
*= msaa_px_size_sa
.h
;
599 /* W-tiles and Y-tiles have the same layout as far as cache lines are
600 * concerned: both are 8x8 cache lines laid out Y-major. The difference is
601 * entirely in how the data is arranged withing the cache line. W-tiling
602 * is 8x8 pixels in a swizzled pattern while Y-tiling is 16B by 4 rows
603 * regardless of image format size. As long as everything is aligned to 8,
604 * we can just treat the W-tiled image as Y-tiled, ignore the layout
605 * difference within a cache line, and blast out data.
607 if (x0
% 8 != 0 || y0
% 8 != 0 || x1
% 8 != 0 || y1
% 8 != 0)
610 struct blorp_params params
;
611 blorp_params_init(¶ms
);
613 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
616 memset(¶ms
.wm_inputs
.clear_color
, stencil_value
,
617 sizeof(params
.wm_inputs
.clear_color
));
619 /* The Sandy Bridge PRM Vol. 4 Pt. 2, section 2.11.2.1.1 has the
620 * following footnote to the format table:
622 * 128 BPE Formats cannot be Tiled Y when used as render targets
624 * We have to use RGBA16_UINT on SNB.
626 enum isl_format wide_format
;
627 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) <= 6) {
628 wide_format
= ISL_FORMAT_R16G16B16A16_UINT
;
630 /* For RGBA16_UINT, we need to mask the stencil value otherwise, we risk
631 * clamping giving us the wrong values
633 for (unsigned i
= 0; i
< 4; i
++)
634 params
.wm_inputs
.clear_color
[i
] &= 0xffff;
636 wide_format
= ISL_FORMAT_R32G32B32A32_UINT
;
639 for (uint32_t a
= 0; a
< num_layers
; a
++) {
640 uint32_t layer
= start_layer
+ a
;
642 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
643 layer
, ISL_FORMAT_UNSUPPORTED
, true);
645 if (surf
->surf
->samples
> 1)
646 blorp_surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
.dst
);
648 /* Make it Y-tiled */
649 blorp_surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
.dst
);
652 isl_format_get_layout(wide_format
)->bpb
/ 8;
654 params
.dst
.view
.format
= params
.dst
.surf
.format
= wide_format
;
655 assert(params
.dst
.surf
.logical_level0_px
.width
% wide_Bpp
== 0);
656 params
.dst
.surf
.logical_level0_px
.width
/= wide_Bpp
;
657 assert(params
.dst
.tile_x_sa
% wide_Bpp
== 0);
658 params
.dst
.tile_x_sa
/= wide_Bpp
;
660 params
.x0
= params
.dst
.tile_x_sa
+ x0
/ (wide_Bpp
/ 2);
661 params
.y0
= params
.dst
.tile_y_sa
+ y0
/ 2;
662 params
.x1
= params
.dst
.tile_x_sa
+ x1
/ (wide_Bpp
/ 2);
663 params
.y1
= params
.dst
.tile_y_sa
+ y1
/ 2;
665 batch
->blorp
->exec(batch
, ¶ms
);
672 blorp_clear_depth_stencil(struct blorp_batch
*batch
,
673 const struct blorp_surf
*depth
,
674 const struct blorp_surf
*stencil
,
675 uint32_t level
, uint32_t start_layer
,
677 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
678 bool clear_depth
, float depth_value
,
679 uint8_t stencil_mask
, uint8_t stencil_value
)
681 if (!clear_depth
&& blorp_clear_stencil_as_rgba(batch
, stencil
, level
,
682 start_layer
, num_layers
,
688 struct blorp_params params
;
689 blorp_params_init(¶ms
);
696 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) == 6) {
697 /* For some reason, Sandy Bridge gets occlusion queries wrong if we
698 * don't have a shader. In particular, it records samples even though
699 * we disable statistics in 3DSTATE_WM. Give it the usual clear shader
700 * to work around the issue.
702 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, false, false))
706 while (num_layers
> 0) {
707 params
.num_layers
= num_layers
;
710 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
712 ISL_FORMAT_UNSUPPORTED
, true);
713 params
.stencil_mask
= stencil_mask
;
714 params
.stencil_ref
= stencil_value
;
716 params
.dst
.surf
.samples
= params
.stencil
.surf
.samples
;
717 params
.dst
.surf
.logical_level0_px
=
718 params
.stencil
.surf
.logical_level0_px
;
719 params
.dst
.view
= params
.stencil
.view
;
721 params
.num_samples
= params
.stencil
.surf
.samples
;
723 /* We may be restricted on the number of layers we can bind at any
724 * one time. In particular, Sandy Bridge has a maximum number of
725 * layers of 512 but a maximum 3D texture size is much larger.
727 if (params
.stencil
.view
.array_len
< params
.num_layers
)
728 params
.num_layers
= params
.stencil
.view
.array_len
;
732 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
734 ISL_FORMAT_UNSUPPORTED
, true);
735 params
.z
= depth_value
;
736 params
.depth_format
=
737 isl_format_get_depth_format(depth
->surf
->format
, false);
739 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
740 params
.dst
.surf
.logical_level0_px
=
741 params
.depth
.surf
.logical_level0_px
;
742 params
.dst
.view
= params
.depth
.view
;
744 params
.num_samples
= params
.depth
.surf
.samples
;
746 /* We may be restricted on the number of layers we can bind at any
747 * one time. In particular, Sandy Bridge has a maximum number of
748 * layers of 512 but a maximum 3D texture size is much larger.
750 if (params
.depth
.view
.array_len
< params
.num_layers
)
751 params
.num_layers
= params
.depth
.view
.array_len
;
754 batch
->blorp
->exec(batch
, ¶ms
);
756 start_layer
+= params
.num_layers
;
757 num_layers
-= params
.num_layers
;
762 blorp_can_hiz_clear_depth(const struct gen_device_info
*devinfo
,
763 const struct isl_surf
*surf
,
764 enum isl_aux_usage aux_usage
,
765 uint32_t level
, uint32_t layer
,
766 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
768 /* This function currently doesn't support any gen prior to gen8 */
769 assert(devinfo
->gen
>= 8);
771 if (devinfo
->gen
== 8 && surf
->format
== ISL_FORMAT_R16_UNORM
) {
772 /* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample
773 * block with the following property: as the number of samples increases,
774 * the number of pixels representable by this block decreases by a factor
775 * of the sample dimensions. Sample dimensions scale following the MSAA
776 * interleaved pattern.
778 * Sample|Sample|Pixel
780 * ===================
787 * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
789 const struct isl_extent2d sa_block_dim
=
790 isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
791 const uint8_t align_px_w
= 8 / sa_block_dim
.w
;
792 const uint8_t align_px_h
= 4 / sa_block_dim
.h
;
794 /* Fast depth clears clear an entire sample block at a time. As a result,
795 * the rectangle must be aligned to the dimensions of the encompassing
796 * pixel block for a successful operation.
798 * Fast clears can still work if the upper-left corner is aligned and the
799 * bottom-rigtht corner touches the edge of a depth buffer whose extent
800 * is unaligned. This is because each miplevel in the depth buffer is
801 * padded by the Pixel Dim (similar to a standard compressed texture).
802 * In this case, the clear rectangle could be padded by to match the full
803 * depth buffer extent but to support multiple clearing techniques, we
804 * chose to be unaware of the depth buffer's extent and thus don't handle
807 if (x0
% align_px_w
|| y0
% align_px_h
||
808 x1
% align_px_w
|| y1
% align_px_h
)
810 } else if (aux_usage
== ISL_AUX_USAGE_HIZ_CCS_WT
) {
811 /* We have to set the WM_HZ_OP::FullSurfaceDepthandStencilClear bit
812 * whenever we clear an uninitialized HIZ buffer (as some drivers
813 * currently do). However, this bit seems liable to clear 16x8 pixels in
814 * the ZCS on Gen12 - greater than the slice alignments for depth
817 assert(surf
->image_alignment_el
.w
% 16 != 0 ||
818 surf
->image_alignment_el
.h
% 8 != 0);
820 /* This is the hypothesis behind some corruption that was seen with the
821 * amd_vertex_shader_layer-layered-depth-texture-render piglit test.
823 * From the Compressed Depth Buffers section of the Bspec, under the
824 * Gen12 texture performant and ZCS columns:
826 * Update with clear at either 16x8 or 8x4 granularity, based on
827 * fs_clr or otherwise.
829 * There are a number of ways to avoid full surface CCS clears that
830 * overlap other slices, but for now we choose to disable fast-clears
831 * when an initializing clear could hit another miplevel.
833 * NOTE: Because the CCS compresses the depth buffer and not a version
834 * of it that has been rearranged with different alignments (like Gen8+
835 * HIZ), we have to make sure that the x0 and y0 are at least 16x8
836 * aligned in the context of the entire surface.
838 uint32_t slice_x0
, slice_y0
;
839 isl_surf_get_image_offset_el(surf
, level
,
840 surf
->dim
== ISL_SURF_DIM_3D
? 0 : layer
,
841 surf
->dim
== ISL_SURF_DIM_3D
? layer
: 0,
842 &slice_x0
, &slice_y0
);
843 const bool max_x1_y1
=
844 x1
== minify(surf
->logical_level0_px
.width
, level
) &&
845 y1
== minify(surf
->logical_level0_px
.height
, level
);
846 const uint32_t haligned_x1
= ALIGN(x1
, surf
->image_alignment_el
.w
);
847 const uint32_t valigned_y1
= ALIGN(y1
, surf
->image_alignment_el
.h
);
848 const bool unaligned
= (slice_x0
+ x0
) % 16 || (slice_y0
+ y0
) % 8 ||
849 max_x1_y1
? haligned_x1
% 16 || valigned_y1
% 8 :
851 const bool alignment_used
= surf
->levels
> 1 ||
852 surf
->logical_level0_px
.depth
> 1 ||
853 surf
->logical_level0_px
.array_len
> 1;
855 if (unaligned
&& alignment_used
)
859 return isl_aux_usage_has_hiz(aux_usage
);
863 blorp_hiz_clear_depth_stencil(struct blorp_batch
*batch
,
864 const struct blorp_surf
*depth
,
865 const struct blorp_surf
*stencil
,
867 uint32_t start_layer
, uint32_t num_layers
,
868 uint32_t x0
, uint32_t y0
,
869 uint32_t x1
, uint32_t y1
,
870 bool clear_depth
, float depth_value
,
871 bool clear_stencil
, uint8_t stencil_value
)
873 struct blorp_params params
;
874 blorp_params_init(¶ms
);
876 /* This requires WM_HZ_OP which only exists on gen8+ */
877 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8);
879 params
.hiz_op
= ISL_AUX_OP_FAST_CLEAR
;
880 params
.num_layers
= 1;
887 for (uint32_t l
= 0; l
< num_layers
; l
++) {
888 const uint32_t layer
= start_layer
+ l
;
890 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
892 ISL_FORMAT_UNSUPPORTED
, true);
893 params
.stencil_mask
= 0xff;
894 params
.stencil_ref
= stencil_value
;
895 params
.num_samples
= params
.stencil
.surf
.samples
;
899 /* If we're clearing depth, we must have HiZ */
900 assert(depth
&& depth
->aux_usage
== ISL_AUX_USAGE_HIZ
);
902 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
904 ISL_FORMAT_UNSUPPORTED
, true);
905 params
.depth
.clear_color
.f32
[0] = depth_value
;
906 params
.depth_format
=
907 isl_format_get_depth_format(depth
->surf
->format
, false);
908 params
.num_samples
= params
.depth
.surf
.samples
;
911 batch
->blorp
->exec(batch
, ¶ms
);
915 /* Given a depth stencil attachment, this function performs a fast depth clear
916 * on a depth portion and a regular clear on the stencil portion. When
917 * performing a fast depth clear on the depth portion, the HiZ buffer is simply
918 * tagged as cleared so the depth clear value is not actually needed.
921 blorp_gen8_hiz_clear_attachments(struct blorp_batch
*batch
,
922 uint32_t num_samples
,
923 uint32_t x0
, uint32_t y0
,
924 uint32_t x1
, uint32_t y1
,
925 bool clear_depth
, bool clear_stencil
,
926 uint8_t stencil_value
)
928 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
930 struct blorp_params params
;
931 blorp_params_init(¶ms
);
932 params
.num_layers
= 1;
933 params
.hiz_op
= ISL_AUX_OP_FAST_CLEAR
;
938 params
.num_samples
= num_samples
;
939 params
.depth
.enabled
= clear_depth
;
940 params
.stencil
.enabled
= clear_stencil
;
941 params
.stencil_ref
= stencil_value
;
942 batch
->blorp
->exec(batch
, ¶ms
);
945 /** Clear active color/depth/stencili attachments
947 * This function performs a clear operation on the currently bound
948 * color/depth/stencil attachments. It is assumed that any information passed
949 * in here is valid, consistent, and in-bounds relative to the currently
950 * attached depth/stencil. The binding_table_offset parameter is the 32-bit
951 * offset relative to surface state base address where pre-baked binding table
952 * that we are to use lives. If clear_color is false, binding_table_offset
953 * must point to a binding table with one entry which is a valid null surface
954 * that matches the currently bound depth and stencil.
957 blorp_clear_attachments(struct blorp_batch
*batch
,
958 uint32_t binding_table_offset
,
959 enum isl_format depth_format
,
960 uint32_t num_samples
,
961 uint32_t start_layer
, uint32_t num_layers
,
962 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
963 bool clear_color
, union isl_color_value color_value
,
964 bool clear_depth
, float depth_value
,
965 uint8_t stencil_mask
, uint8_t stencil_value
)
967 struct blorp_params params
;
968 blorp_params_init(¶ms
);
970 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
977 params
.use_pre_baked_binding_table
= true;
978 params
.pre_baked_binding_table_offset
= binding_table_offset
;
980 params
.num_layers
= num_layers
;
981 params
.num_samples
= num_samples
;
984 params
.dst
.enabled
= true;
986 memcpy(¶ms
.wm_inputs
.clear_color
, color_value
.f32
, sizeof(float) * 4);
988 /* Unfortunately, without knowing whether or not our destination surface
989 * is tiled or not, we have to assume it may be linear. This means no
990 * SIMD16_REPDATA for us. :-(
992 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, false, false))
997 params
.depth
.enabled
= true;
999 params
.z
= depth_value
;
1000 params
.depth_format
= isl_format_get_depth_format(depth_format
, false);
1004 params
.stencil
.enabled
= true;
1006 params
.stencil_mask
= stencil_mask
;
1007 params
.stencil_ref
= stencil_value
;
1010 if (!blorp_params_get_layer_offset_vs(batch
, ¶ms
))
1013 params
.vs_inputs
.base_layer
= start_layer
;
1015 batch
->blorp
->exec(batch
, ¶ms
);
1019 blorp_ccs_resolve(struct blorp_batch
*batch
,
1020 struct blorp_surf
*surf
, uint32_t level
,
1021 uint32_t start_layer
, uint32_t num_layers
,
1022 enum isl_format format
,
1023 enum isl_aux_op resolve_op
)
1025 struct blorp_params params
;
1027 blorp_params_init(¶ms
);
1028 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
,
1029 level
, start_layer
, format
, true);
1031 /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
1033 * A rectangle primitive must be scaled down by the following factors
1034 * with respect to render target being resolved.
1036 * The scaledown factors in the table that follows are related to the block
1037 * size of the CCS format. For IVB and HSW, we divide by two, for BDW we
1038 * multiply by 8 and 16. On Sky Lake, we multiply by 8.
1040 const struct isl_format_layout
*aux_fmtl
=
1041 isl_format_get_layout(params
.dst
.aux_surf
.format
);
1042 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
1044 unsigned x_scaledown
, y_scaledown
;
1045 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 12) {
1046 x_scaledown
= aux_fmtl
->bw
* 8;
1047 y_scaledown
= aux_fmtl
->bh
* 4;
1048 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 9) {
1049 x_scaledown
= aux_fmtl
->bw
* 8;
1050 y_scaledown
= aux_fmtl
->bh
* 8;
1051 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
1052 x_scaledown
= aux_fmtl
->bw
* 8;
1053 y_scaledown
= aux_fmtl
->bh
* 16;
1055 x_scaledown
= aux_fmtl
->bw
/ 2;
1056 y_scaledown
= aux_fmtl
->bh
/ 2;
1058 params
.x0
= params
.y0
= 0;
1059 params
.x1
= minify(params
.dst
.surf
.logical_level0_px
.width
, level
);
1060 params
.y1
= minify(params
.dst
.surf
.logical_level0_px
.height
, level
);
1061 params
.x1
= ALIGN(params
.x1
, x_scaledown
) / x_scaledown
;
1062 params
.y1
= ALIGN(params
.y1
, y_scaledown
) / y_scaledown
;
1064 if (batch
->blorp
->isl_dev
->info
->gen
>= 10) {
1065 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
||
1066 resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
||
1067 resolve_op
== ISL_AUX_OP_AMBIGUATE
);
1068 } else if (batch
->blorp
->isl_dev
->info
->gen
>= 9) {
1069 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
||
1070 resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
1072 /* Broadwell and earlier do not have a partial resolve */
1073 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
);
1075 params
.fast_clear_op
= resolve_op
;
1076 params
.num_layers
= num_layers
;
1078 /* Note: there is no need to initialize push constants because it doesn't
1079 * matter what data gets dispatched to the render target. However, we must
1080 * ensure that the fragment shader delivers the data using the "replicated
1084 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
1087 batch
->blorp
->exec(batch
, ¶ms
);
1090 static nir_ssa_def
*
1091 blorp_nir_bit(nir_builder
*b
, nir_ssa_def
*src
, unsigned bit
)
1093 return nir_iand(b
, nir_ushr(b
, src
, nir_imm_int(b
, bit
)),
1097 #pragma pack(push, 1)
1098 struct blorp_mcs_partial_resolve_key
1100 enum blorp_shader_type shader_type
;
1101 bool indirect_clear_color
;
1103 uint32_t num_samples
;
1108 blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch
*batch
,
1109 struct blorp_params
*params
)
1111 struct blorp_context
*blorp
= batch
->blorp
;
1112 const struct blorp_mcs_partial_resolve_key blorp_key
= {
1113 .shader_type
= BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE
,
1114 .indirect_clear_color
= params
->dst
.clear_color_addr
.buffer
!= NULL
,
1115 .int_format
= isl_format_has_int_channel(params
->dst
.view
.format
),
1116 .num_samples
= params
->num_samples
,
1119 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
1120 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1123 void *mem_ctx
= ralloc_context(NULL
);
1126 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
,
1127 "BLORP-mcs-partial-resolve");
1129 nir_variable
*v_color
=
1130 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
1132 nir_variable
*frag_color
=
1133 nir_variable_create(b
.shader
, nir_var_shader_out
,
1134 glsl_vec4_type(), "gl_FragColor");
1135 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
1137 /* Do an MCS fetch and check if it is equal to the magic clear value */
1139 blorp_nir_txf_ms_mcs(&b
, nir_f2i32(&b
, nir_load_frag_coord(&b
)),
1140 nir_load_layer_id(&b
));
1141 nir_ssa_def
*is_clear
=
1142 blorp_nir_mcs_is_clear_color(&b
, mcs
, blorp_key
.num_samples
);
1144 /* If we aren't the clear value, discard. */
1145 nir_intrinsic_instr
*discard
=
1146 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_discard_if
);
1147 discard
->src
[0] = nir_src_for_ssa(nir_inot(&b
, is_clear
));
1148 nir_builder_instr_insert(&b
, &discard
->instr
);
1150 nir_ssa_def
*clear_color
= nir_load_var(&b
, v_color
);
1151 if (blorp_key
.indirect_clear_color
&& blorp
->isl_dev
->info
->gen
<= 8) {
1152 /* Gen7-8 clear colors are stored as single 0/1 bits */
1153 clear_color
= nir_vec4(&b
, blorp_nir_bit(&b
, clear_color
, 31),
1154 blorp_nir_bit(&b
, clear_color
, 30),
1155 blorp_nir_bit(&b
, clear_color
, 29),
1156 blorp_nir_bit(&b
, clear_color
, 28));
1158 if (!blorp_key
.int_format
)
1159 clear_color
= nir_i2f32(&b
, clear_color
);
1161 nir_store_var(&b
, frag_color
, clear_color
, 0xf);
1163 struct brw_wm_prog_key wm_key
;
1164 brw_blorp_init_wm_prog_key(&wm_key
);
1165 wm_key
.base
.tex
.compressed_multisample_layout_mask
= 1;
1166 wm_key
.base
.tex
.msaa_16
= blorp_key
.num_samples
== 16;
1167 wm_key
.multisample_fbo
= true;
1169 struct brw_wm_prog_data prog_data
;
1170 const unsigned *program
=
1171 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, false,
1175 blorp
->upload_shader(batch
, MESA_SHADER_FRAGMENT
,
1176 &blorp_key
, sizeof(blorp_key
),
1177 program
, prog_data
.base
.program_size
,
1178 &prog_data
.base
, sizeof(prog_data
),
1179 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1181 ralloc_free(mem_ctx
);
1186 blorp_mcs_partial_resolve(struct blorp_batch
*batch
,
1187 struct blorp_surf
*surf
,
1188 enum isl_format format
,
1189 uint32_t start_layer
, uint32_t num_layers
)
1191 struct blorp_params params
;
1192 blorp_params_init(¶ms
);
1194 assert(batch
->blorp
->isl_dev
->info
->gen
>= 7);
1198 params
.x1
= surf
->surf
->logical_level0_px
.width
;
1199 params
.y1
= surf
->surf
->logical_level0_px
.height
;
1201 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, surf
, 0,
1202 start_layer
, format
, false);
1203 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, 0,
1204 start_layer
, format
, true);
1206 params
.num_samples
= params
.dst
.surf
.samples
;
1207 params
.num_layers
= num_layers
;
1208 params
.dst_clear_color_as_input
= surf
->clear_color_addr
.buffer
!= NULL
;
1210 memcpy(¶ms
.wm_inputs
.clear_color
,
1211 surf
->clear_color
.f32
, sizeof(float) * 4);
1213 if (!blorp_params_get_mcs_partial_resolve_kernel(batch
, ¶ms
))
1216 batch
->blorp
->exec(batch
, ¶ms
);
1219 /** Clear a CCS to the "uncompressed" state
1221 * This pass is the CCS equivalent of a "HiZ resolve". It sets the CCS values
1222 * for a given layer/level of a surface to 0x0 which is the "uncompressed"
1223 * state which tells the sampler to go look at the main surface.
1226 blorp_ccs_ambiguate(struct blorp_batch
*batch
,
1227 struct blorp_surf
*surf
,
1228 uint32_t level
, uint32_t layer
)
1230 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 10) {
1231 /* On gen10 and above, we have a hardware resolve op for this */
1232 return blorp_ccs_resolve(batch
, surf
, level
, layer
, 1,
1233 surf
->surf
->format
, ISL_AUX_OP_AMBIGUATE
);
1236 struct blorp_params params
;
1237 blorp_params_init(¶ms
);
1239 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 7);
1241 const struct isl_format_layout
*aux_fmtl
=
1242 isl_format_get_layout(surf
->aux_surf
->format
);
1243 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
1245 params
.dst
= (struct brw_blorp_surface_info
) {
1247 .addr
= surf
->aux_addr
,
1249 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1250 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
1252 .base_array_layer
= 0,
1255 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1260 if (surf
->surf
->dim
== ISL_SURF_DIM_3D
) {
1265 uint32_t offset_B
, x_offset_el
, y_offset_el
;
1266 isl_surf_get_image_offset_el(surf
->aux_surf
, level
, layer
, z
,
1267 &x_offset_el
, &y_offset_el
);
1268 isl_tiling_get_intratile_offset_el(surf
->aux_surf
->tiling
, aux_fmtl
->bpb
,
1269 surf
->aux_surf
->row_pitch_B
,
1270 x_offset_el
, y_offset_el
,
1271 &offset_B
, &x_offset_el
, &y_offset_el
);
1272 params
.dst
.addr
.offset
+= offset_B
;
1274 const uint32_t width_px
=
1275 minify(surf
->aux_surf
->logical_level0_px
.width
, level
);
1276 const uint32_t height_px
=
1277 minify(surf
->aux_surf
->logical_level0_px
.height
, level
);
1278 const uint32_t width_el
= DIV_ROUND_UP(width_px
, aux_fmtl
->bw
);
1279 const uint32_t height_el
= DIV_ROUND_UP(height_px
, aux_fmtl
->bh
);
1281 struct isl_tile_info ccs_tile_info
;
1282 isl_surf_get_tile_info(surf
->aux_surf
, &ccs_tile_info
);
1284 /* We're going to map it as a regular RGBA32_UINT surface. We need to
1285 * downscale a good deal. We start by computing the area on the CCS to
1286 * clear in units of Y-tiled cache lines.
1288 uint32_t x_offset_cl
, y_offset_cl
, width_cl
, height_cl
;
1289 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
1290 /* From the Sky Lake PRM Vol. 12 in the section on planes:
1292 * "The Color Control Surface (CCS) contains the compression status
1293 * of the cache-line pairs. The compression state of the cache-line
1294 * pair is specified by 2 bits in the CCS. Each CCS cache-line
1295 * represents an area on the main surface of 16x16 sets of 128 byte
1296 * Y-tiled cache-line-pairs. CCS is always Y tiled."
1298 * Each 2-bit surface element in the CCS corresponds to a single
1299 * cache-line pair in the main surface. This means that 16x16 el block
1300 * in the CCS maps to a Y-tiled cache line. Fortunately, CCS layouts
1301 * are calculated with a very large alignment so we can round up to a
1302 * whole cache line without worrying about overdraw.
1305 /* On Broadwell and above, a CCS tile is the same as a Y tile when
1306 * viewed at the cache-line granularity. Fortunately, the horizontal
1307 * and vertical alignment requirements of the CCS are such that we can
1308 * align to an entire cache line without worrying about crossing over
1309 * from one LOD to another.
1311 const uint32_t x_el_per_cl
= ccs_tile_info
.logical_extent_el
.w
/ 8;
1312 const uint32_t y_el_per_cl
= ccs_tile_info
.logical_extent_el
.h
/ 8;
1313 assert(surf
->aux_surf
->image_alignment_el
.w
% x_el_per_cl
== 0);
1314 assert(surf
->aux_surf
->image_alignment_el
.h
% y_el_per_cl
== 0);
1316 assert(x_offset_el
% x_el_per_cl
== 0);
1317 assert(y_offset_el
% y_el_per_cl
== 0);
1318 x_offset_cl
= x_offset_el
/ x_el_per_cl
;
1319 y_offset_cl
= y_offset_el
/ y_el_per_cl
;
1320 width_cl
= DIV_ROUND_UP(width_el
, x_el_per_cl
);
1321 height_cl
= DIV_ROUND_UP(height_el
, y_el_per_cl
);
1323 /* On gen7, the CCS tiling is not so nice. However, there we are
1324 * guaranteed that we only have a single level and slice so we don't
1325 * have to worry about it and can just align to a whole tile.
1327 assert(surf
->aux_surf
->logical_level0_px
.depth
== 1);
1328 assert(surf
->aux_surf
->logical_level0_px
.array_len
== 1);
1329 assert(x_offset_el
== 0 && y_offset_el
== 0);
1330 const uint32_t width_tl
=
1331 DIV_ROUND_UP(width_el
, ccs_tile_info
.logical_extent_el
.w
);
1332 const uint32_t height_tl
=
1333 DIV_ROUND_UP(height_el
, ccs_tile_info
.logical_extent_el
.h
);
1336 width_cl
= width_tl
* 8;
1337 height_cl
= height_tl
* 8;
1340 /* We're going to use a RGBA32 format so as to write data as quickly as
1341 * possible. A y-tiled cache line will then be 1x4 px.
1343 const uint32_t x_offset_rgba_px
= x_offset_cl
;
1344 const uint32_t y_offset_rgba_px
= y_offset_cl
* 4;
1345 const uint32_t width_rgba_px
= width_cl
;
1346 const uint32_t height_rgba_px
= height_cl
* 4;
1349 isl_surf_init(batch
->blorp
->isl_dev
, ¶ms
.dst
.surf
,
1350 .dim
= ISL_SURF_DIM_2D
,
1351 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
1352 .width
= width_rgba_px
+ x_offset_rgba_px
,
1353 .height
= height_rgba_px
+ y_offset_rgba_px
,
1358 .row_pitch_B
= surf
->aux_surf
->row_pitch_B
,
1359 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1360 .tiling_flags
= ISL_TILING_Y0_BIT
);
1363 params
.x0
= x_offset_rgba_px
;
1364 params
.y0
= y_offset_rgba_px
;
1365 params
.x1
= x_offset_rgba_px
+ width_rgba_px
;
1366 params
.y1
= y_offset_rgba_px
+ height_rgba_px
;
1368 /* A CCS value of 0 means "uncompressed." */
1369 memset(¶ms
.wm_inputs
.clear_color
, 0,
1370 sizeof(params
.wm_inputs
.clear_color
));
1372 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
1375 batch
->blorp
->exec(batch
, ¶ms
);