2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/ralloc.h"
26 #include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
27 #include "util/format_rgb9e5.h"
28 #include "util/format_srgb.h"
30 #include "blorp_priv.h"
31 #include "compiler/brw_eu_defines.h"
33 #include "blorp_nir_builder.h"
35 #define FILE_DEBUG_FLAG DEBUG_BLORP
38 struct brw_blorp_const_color_prog_key
40 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_CLEAR */
41 bool use_simd16_replicated_data
;
42 bool clear_rgb_as_red
;
47 blorp_params_get_clear_kernel(struct blorp_batch
*batch
,
48 struct blorp_params
*params
,
49 bool use_replicated_data
,
50 bool clear_rgb_as_red
)
52 struct blorp_context
*blorp
= batch
->blorp
;
54 const struct brw_blorp_const_color_prog_key blorp_key
= {
55 .shader_type
= BLORP_SHADER_TYPE_CLEAR
,
56 .use_simd16_replicated_data
= use_replicated_data
,
57 .clear_rgb_as_red
= clear_rgb_as_red
,
60 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
61 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
64 void *mem_ctx
= ralloc_context(NULL
);
67 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, "BLORP-clear");
69 nir_variable
*v_color
=
70 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
71 nir_ssa_def
*color
= nir_load_var(&b
, v_color
);
73 if (clear_rgb_as_red
) {
74 nir_ssa_def
*pos
= nir_f2i32(&b
, nir_load_frag_coord(&b
));
75 nir_ssa_def
*comp
= nir_umod(&b
, nir_channel(&b
, pos
, 0),
77 nir_ssa_def
*color_component
=
78 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
79 nir_channel(&b
, color
, 0),
80 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
81 nir_channel(&b
, color
, 1),
82 nir_channel(&b
, color
, 2)));
84 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
85 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
88 nir_variable
*frag_color
= nir_variable_create(b
.shader
, nir_var_shader_out
,
91 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
92 nir_store_var(&b
, frag_color
, color
, 0xf);
94 struct brw_wm_prog_key wm_key
;
95 brw_blorp_init_wm_prog_key(&wm_key
);
97 struct brw_wm_prog_data prog_data
;
98 const unsigned *program
=
99 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, use_replicated_data
,
103 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
104 program
, prog_data
.base
.program_size
,
105 &prog_data
.base
, sizeof(prog_data
),
106 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
108 ralloc_free(mem_ctx
);
112 #pragma pack(push, 1)
113 struct layer_offset_vs_key
{
114 enum blorp_shader_type shader_type
;
119 /* In the case of doing attachment clears, we are using a surface state that
120 * is handed to us so we can't set (and don't even know) the base array layer.
121 * In order to do a layered clear in this scenario, we need some way of adding
122 * the base array layer to the instance id. Unfortunately, our hardware has
123 * no real concept of "base instance", so we have to do it manually in a
127 blorp_params_get_layer_offset_vs(struct blorp_batch
*batch
,
128 struct blorp_params
*params
)
130 struct blorp_context
*blorp
= batch
->blorp
;
131 struct layer_offset_vs_key blorp_key
= {
132 .shader_type
= BLORP_SHADER_TYPE_LAYER_OFFSET_VS
,
135 if (params
->wm_prog_data
)
136 blorp_key
.num_inputs
= params
->wm_prog_data
->num_varying_inputs
;
138 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
139 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
))
142 void *mem_ctx
= ralloc_context(NULL
);
145 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_VERTEX
, "BLORP-layer-offset-vs");
147 const struct glsl_type
*uvec4_type
= glsl_vector_type(GLSL_TYPE_UINT
, 4);
149 /* First we deal with the header which has instance and base instance */
150 nir_variable
*a_header
= nir_variable_create(b
.shader
, nir_var_shader_in
,
151 uvec4_type
, "header");
152 a_header
->data
.location
= VERT_ATTRIB_GENERIC0
;
154 nir_variable
*v_layer
= nir_variable_create(b
.shader
, nir_var_shader_out
,
155 glsl_int_type(), "layer_id");
156 v_layer
->data
.location
= VARYING_SLOT_LAYER
;
158 /* Compute the layer id */
159 nir_ssa_def
*header
= nir_load_var(&b
, a_header
);
160 nir_ssa_def
*base_layer
= nir_channel(&b
, header
, 0);
161 nir_ssa_def
*instance
= nir_channel(&b
, header
, 1);
162 nir_store_var(&b
, v_layer
, nir_iadd(&b
, instance
, base_layer
), 0x1);
164 /* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
165 nir_variable
*a_vertex
= nir_variable_create(b
.shader
, nir_var_shader_in
,
166 glsl_vec4_type(), "a_vertex");
167 a_vertex
->data
.location
= VERT_ATTRIB_GENERIC1
;
169 nir_variable
*v_pos
= nir_variable_create(b
.shader
, nir_var_shader_out
,
170 glsl_vec4_type(), "v_pos");
171 v_pos
->data
.location
= VARYING_SLOT_POS
;
173 nir_copy_var(&b
, v_pos
, a_vertex
);
175 /* Then we copy everything else */
176 for (unsigned i
= 0; i
< blorp_key
.num_inputs
; i
++) {
177 nir_variable
*a_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
178 uvec4_type
, "input");
179 a_in
->data
.location
= VERT_ATTRIB_GENERIC2
+ i
;
181 nir_variable
*v_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
182 uvec4_type
, "output");
183 v_out
->data
.location
= VARYING_SLOT_VAR0
+ i
;
185 nir_copy_var(&b
, v_out
, a_in
);
188 struct brw_vs_prog_data vs_prog_data
;
189 memset(&vs_prog_data
, 0, sizeof(vs_prog_data
));
191 const unsigned *program
=
192 blorp_compile_vs(blorp
, mem_ctx
, b
.shader
, &vs_prog_data
);
195 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
196 program
, vs_prog_data
.base
.base
.program_size
,
197 &vs_prog_data
.base
.base
, sizeof(vs_prog_data
),
198 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
);
200 ralloc_free(mem_ctx
);
204 /* The x0, y0, x1, and y1 parameters must already be populated with the render
205 * area of the framebuffer to be cleared.
208 get_fast_clear_rect(const struct isl_device
*dev
,
209 const struct isl_surf
*aux_surf
,
210 unsigned *x0
, unsigned *y0
,
211 unsigned *x1
, unsigned *y1
)
213 unsigned int x_align
, y_align
;
214 unsigned int x_scaledown
, y_scaledown
;
216 /* Only single sampled surfaces need to (and actually can) be resolved. */
217 if (aux_surf
->usage
== ISL_SURF_USAGE_CCS_BIT
) {
218 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
219 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
221 * Clear pass must have a clear rectangle that must follow
222 * alignment rules in terms of pixels and lines as shown in the
223 * table below. Further, the clear-rectangle height and width
224 * must be multiple of the following dimensions. If the height
225 * and width of the render target being cleared do not meet these
226 * requirements, an MCS buffer can be created such that it
227 * follows the requirement and covers the RT.
229 * The alignment size in the table that follows is related to the
230 * alignment size that is baked into the CCS surface format but with X
231 * alignment multiplied by 16 and Y alignment multiplied by 32.
233 x_align
= isl_format_get_layout(aux_surf
->format
)->bw
;
234 y_align
= isl_format_get_layout(aux_surf
->format
)->bh
;
238 /* The line alignment requirement for Y-tiled is halved at SKL and again
241 if (dev
->info
->gen
>= 12)
243 else if (dev
->info
->gen
>= 9)
248 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
249 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
251 * In order to optimize the performance MCS buffer (when bound to
252 * 1X RT) clear similarly to MCS buffer clear for MSRT case,
253 * clear rect is required to be scaled by the following factors
254 * in the horizontal and vertical directions:
256 * The X and Y scale down factors in the table that follows are each
257 * equal to half the alignment value computed above.
259 x_scaledown
= x_align
/ 2;
260 y_scaledown
= y_align
/ 2;
262 if (ISL_DEV_IS_HASWELL(dev
)) {
263 /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
264 * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
265 * Clear of Non-MultiSampled Render Target Restrictions":
267 * Clear rectangle must be aligned to two times the number of
268 * pixels in the table shown below due to 16x16 hashing across the
271 * This restriction is only documented to exist on HSW GT3 but
272 * empirical evidence suggests that it's also needed GT2.
278 assert(aux_surf
->usage
== ISL_SURF_USAGE_MCS_BIT
);
280 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
281 * Target(s)", beneath the "MSAA Compression" bullet (p326):
283 * Clear pass for this case requires that scaled down primitive
284 * is sent down with upper left co-ordinate to coincide with
285 * actual rectangle being cleared. For MSAA, clear rectangle’s
286 * height and width need to as show in the following table in
287 * terms of (width,height) of the RT.
289 * MSAA Width of Clear Rect Height of Clear Rect
290 * 2X Ceil(1/8*width) Ceil(1/2*height)
291 * 4X Ceil(1/8*width) Ceil(1/2*height)
292 * 8X Ceil(1/2*width) Ceil(1/2*height)
293 * 16X width Ceil(1/2*height)
295 * The text "with upper left co-ordinate to coincide with actual
296 * rectangle being cleared" is a little confusing--it seems to imply
297 * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
298 * feed the pipeline using the rectangle (x,y) to
299 * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
300 * the number of samples. Experiments indicate that this is not
301 * quite correct; actually, what the hardware appears to do is to
302 * align whatever rectangle is sent down the pipeline to the nearest
303 * multiple of 2x2 blocks, and then scale it up by a factor of N
304 * horizontally and 2 vertically. So the resulting alignment is 4
305 * vertically and either 4 or 16 horizontally, and the scaledown
306 * factor is 2 vertically and either 2 or 8 horizontally.
308 switch (aux_surf
->format
) {
309 case ISL_FORMAT_MCS_2X
:
310 case ISL_FORMAT_MCS_4X
:
313 case ISL_FORMAT_MCS_8X
:
316 case ISL_FORMAT_MCS_16X
:
320 unreachable("Unexpected MCS format for fast clear");
323 x_align
= x_scaledown
* 2;
324 y_align
= y_scaledown
* 2;
327 *x0
= ROUND_DOWN_TO(*x0
, x_align
) / x_scaledown
;
328 *y0
= ROUND_DOWN_TO(*y0
, y_align
) / y_scaledown
;
329 *x1
= ALIGN(*x1
, x_align
) / x_scaledown
;
330 *y1
= ALIGN(*y1
, y_align
) / y_scaledown
;
334 blorp_fast_clear(struct blorp_batch
*batch
,
335 const struct blorp_surf
*surf
, enum isl_format format
,
336 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
337 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
339 struct blorp_params params
;
340 blorp_params_init(¶ms
);
341 params
.num_layers
= num_layers
;
348 memset(¶ms
.wm_inputs
.clear_color
, 0xff, 4*sizeof(float));
349 params
.fast_clear_op
= ISL_AUX_OP_FAST_CLEAR
;
351 get_fast_clear_rect(batch
->blorp
->isl_dev
, surf
->aux_surf
,
352 ¶ms
.x0
, ¶ms
.y0
, ¶ms
.x1
, ¶ms
.y1
);
354 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
357 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
358 start_layer
, format
, true);
359 params
.num_samples
= params
.dst
.surf
.samples
;
361 batch
->blorp
->exec(batch
, ¶ms
);
364 union isl_color_value
365 swizzle_color_value(union isl_color_value src
, struct isl_swizzle swizzle
)
367 union isl_color_value dst
= { .u32
= { 0, } };
369 /* We assign colors in ABGR order so that the first one will be taken in
370 * RGBA precedence order. According to the PRM docs for shader channel
371 * select, this matches Haswell hardware behavior.
373 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
374 dst
.u32
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[3];
375 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
376 dst
.u32
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[2];
377 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
378 dst
.u32
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[1];
379 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
380 dst
.u32
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[0];
386 blorp_clear(struct blorp_batch
*batch
,
387 const struct blorp_surf
*surf
,
388 enum isl_format format
, struct isl_swizzle swizzle
,
389 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
390 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
391 union isl_color_value clear_color
,
392 const bool color_write_disable
[4])
394 struct blorp_params params
;
395 blorp_params_init(¶ms
);
397 /* Manually apply the clear destination swizzle. This way swizzled clears
398 * will work for swizzles which we can't normally use for rendering and it
399 * also ensures that they work on pre-Haswell hardware which can't swizlle
402 clear_color
= swizzle_color_value(clear_color
, swizzle
);
403 swizzle
= ISL_SWIZZLE_IDENTITY
;
405 bool clear_rgb_as_red
= false;
406 if (format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
407 clear_color
.u32
[0] = float3_to_rgb9e5(clear_color
.f32
);
408 format
= ISL_FORMAT_R32_UINT
;
409 } else if (format
== ISL_FORMAT_L8_UNORM_SRGB
) {
410 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
411 format
= ISL_FORMAT_R8_UNORM
;
412 } else if (format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
413 /* Broadwell and earlier cannot render to this format so we need to work
414 * around it by swapping the colors around and using B4G4R4A4 instead.
416 const struct isl_swizzle ARGB
= ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
);
417 clear_color
= swizzle_color_value(clear_color
, ARGB
);
418 format
= ISL_FORMAT_B4G4R4A4_UNORM
;
419 } else if (isl_format_get_layout(format
)->bpb
% 3 == 0) {
420 clear_rgb_as_red
= true;
421 if (format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
) {
422 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
423 clear_color
.f32
[1] = util_format_linear_to_srgb_float(clear_color
.f32
[1]);
424 clear_color
.f32
[2] = util_format_linear_to_srgb_float(clear_color
.f32
[2]);
428 memcpy(¶ms
.wm_inputs
.clear_color
, clear_color
.f32
, sizeof(float) * 4);
430 bool use_simd16_replicated_data
= true;
432 /* From the SNB PRM (Vol4_Part1):
434 * "Replicated data (Message Type = 111) is only supported when
435 * accessing tiled memory. Using this Message Type to access linear
436 * (untiled) memory is UNDEFINED."
438 if (surf
->surf
->tiling
== ISL_TILING_LINEAR
)
439 use_simd16_replicated_data
= false;
441 /* Replicated clears don't work yet before gen6 */
442 if (batch
->blorp
->isl_dev
->info
->gen
< 6)
443 use_simd16_replicated_data
= false;
445 /* Constant color writes ignore everyting in blend and color calculator
446 * state. This is not documented.
448 if (color_write_disable
) {
449 for (unsigned i
= 0; i
< 4; i
++) {
450 params
.color_write_disable
[i
] = color_write_disable
[i
];
451 if (color_write_disable
[i
])
452 use_simd16_replicated_data
= false;
456 if (!blorp_params_get_clear_kernel(batch
, ¶ms
,
457 use_simd16_replicated_data
,
461 if (!blorp_ensure_sf_program(batch
, ¶ms
))
464 while (num_layers
> 0) {
465 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
466 start_layer
, format
, true);
467 params
.dst
.view
.swizzle
= swizzle
;
474 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
475 assert(params
.dst
.surf
.samples
== 1);
476 assert(num_layers
== 1);
477 params
.x0
+= params
.dst
.tile_x_sa
;
478 params
.y0
+= params
.dst
.tile_y_sa
;
479 params
.x1
+= params
.dst
.tile_x_sa
;
480 params
.y1
+= params
.dst
.tile_y_sa
;
483 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
484 * Convert them to a single slice on gen4.
486 if (batch
->blorp
->isl_dev
->info
->gen
== 4 &&
487 (params
.dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
)) {
488 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
.dst
);
491 if (clear_rgb_as_red
) {
492 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
.dst
);
497 if (isl_format_is_compressed(params
.dst
.surf
.format
)) {
498 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
499 NULL
, NULL
, NULL
, NULL
);
500 //&dst_x, &dst_y, &dst_w, &dst_h);
503 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
504 /* Either we're on gen4 where there is no multisampling or the
505 * surface is compressed which also implies no multisampling.
506 * Therefore, sa == px and we don't need to do a conversion.
508 assert(params
.dst
.surf
.samples
== 1);
509 params
.x0
+= params
.dst
.tile_x_sa
;
510 params
.y0
+= params
.dst
.tile_y_sa
;
511 params
.x1
+= params
.dst
.tile_x_sa
;
512 params
.y1
+= params
.dst
.tile_y_sa
;
515 params
.num_samples
= params
.dst
.surf
.samples
;
517 /* We may be restricted on the number of layers we can bind at any one
518 * time. In particular, Sandy Bridge has a maximum number of layers of
519 * 512 but a maximum 3D texture size is much larger.
521 params
.num_layers
= MIN2(params
.dst
.view
.array_len
, num_layers
);
523 const unsigned max_image_width
= 16 * 1024;
524 if (params
.dst
.surf
.logical_level0_px
.width
> max_image_width
) {
525 /* Clearing an RGB image as red multiplies the surface width by 3
526 * so it may now be too wide for the hardware surface limits. We
527 * have to break the clear up into pieces in order to clear wide
530 assert(clear_rgb_as_red
);
531 assert(params
.dst
.surf
.dim
== ISL_SURF_DIM_2D
);
532 assert(params
.dst
.surf
.tiling
== ISL_TILING_LINEAR
);
533 assert(params
.dst
.surf
.logical_level0_px
.depth
== 1);
534 assert(params
.dst
.surf
.logical_level0_px
.array_len
== 1);
535 assert(params
.dst
.surf
.levels
== 1);
536 assert(params
.dst
.surf
.samples
== 1);
537 assert(params
.dst
.tile_x_sa
== 0 || params
.dst
.tile_y_sa
== 0);
538 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
);
540 /* max_image_width rounded down to a multiple of 3 */
541 const unsigned max_fake_rgb_width
= (max_image_width
/ 3) * 3;
543 isl_format_get_layout(params
.dst
.surf
.format
)->bpb
/ 8;
545 params
.dst
.surf
.logical_level0_px
.width
= max_fake_rgb_width
;
546 params
.dst
.surf
.phys_level0_sa
.width
= max_fake_rgb_width
;
548 uint32_t orig_x0
= params
.x0
, orig_x1
= params
.x1
;
549 uint64_t orig_offset
= params
.dst
.addr
.offset
;
550 for (uint32_t x
= orig_x0
; x
< orig_x1
; x
+= max_fake_rgb_width
) {
551 /* Offset to the surface. It's easy because we're linear */
552 params
.dst
.addr
.offset
= orig_offset
+ x
* cpp
;
555 params
.x1
= MIN2(orig_x1
- x
, max_image_width
);
557 batch
->blorp
->exec(batch
, ¶ms
);
560 batch
->blorp
->exec(batch
, ¶ms
);
563 start_layer
+= params
.num_layers
;
564 num_layers
-= params
.num_layers
;
569 blorp_clear_stencil_as_rgba(struct blorp_batch
*batch
,
570 const struct blorp_surf
*surf
,
571 uint32_t level
, uint32_t start_layer
,
573 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
574 uint8_t stencil_mask
, uint8_t stencil_value
)
576 /* We only support separate W-tiled stencil for now */
577 if (surf
->surf
->format
!= ISL_FORMAT_R8_UINT
||
578 surf
->surf
->tiling
!= ISL_TILING_W
)
581 /* Stencil mask support would require piles of shader magic */
582 if (stencil_mask
!= 0xff)
585 if (surf
->surf
->samples
> 1) {
586 /* Adjust x0, y0, x1, and y1 to be in units of samples */
587 assert(surf
->surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
588 struct isl_extent2d msaa_px_size_sa
=
589 isl_get_interleaved_msaa_px_size_sa(surf
->surf
->samples
);
591 x0
*= msaa_px_size_sa
.w
;
592 y0
*= msaa_px_size_sa
.h
;
593 x1
*= msaa_px_size_sa
.w
;
594 y1
*= msaa_px_size_sa
.h
;
597 /* W-tiles and Y-tiles have the same layout as far as cache lines are
598 * concerned: both are 8x8 cache lines laid out Y-major. The difference is
599 * entirely in how the data is arranged withing the cache line. W-tiling
600 * is 8x8 pixels in a swizzled pattern while Y-tiling is 16B by 4 rows
601 * regardless of image format size. As long as everything is aligned to 8,
602 * we can just treat the W-tiled image as Y-tiled, ignore the layout
603 * difference within a cache line, and blast out data.
605 if (x0
% 8 != 0 || y0
% 8 != 0 || x1
% 8 != 0 || y1
% 8 != 0)
608 struct blorp_params params
;
609 blorp_params_init(¶ms
);
611 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
614 memset(¶ms
.wm_inputs
.clear_color
, stencil_value
,
615 sizeof(params
.wm_inputs
.clear_color
));
617 /* The Sandy Bridge PRM Vol. 4 Pt. 2, section 2.11.2.1.1 has the
618 * following footnote to the format table:
620 * 128 BPE Formats cannot be Tiled Y when used as render targets
622 * We have to use RGBA16_UINT on SNB.
624 enum isl_format wide_format
;
625 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) <= 6) {
626 wide_format
= ISL_FORMAT_R16G16B16A16_UINT
;
628 /* For RGBA16_UINT, we need to mask the stencil value otherwise, we risk
629 * clamping giving us the wrong values
631 for (unsigned i
= 0; i
< 4; i
++)
632 params
.wm_inputs
.clear_color
[i
] &= 0xffff;
634 wide_format
= ISL_FORMAT_R32G32B32A32_UINT
;
637 for (uint32_t a
= 0; a
< num_layers
; a
++) {
638 uint32_t layer
= start_layer
+ a
;
640 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
641 layer
, ISL_FORMAT_UNSUPPORTED
, true);
643 if (surf
->surf
->samples
> 1)
644 blorp_surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
.dst
);
646 /* Make it Y-tiled */
647 blorp_surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
.dst
);
650 isl_format_get_layout(wide_format
)->bpb
/ 8;
652 params
.dst
.view
.format
= params
.dst
.surf
.format
= wide_format
;
653 assert(params
.dst
.surf
.logical_level0_px
.width
% wide_Bpp
== 0);
654 params
.dst
.surf
.logical_level0_px
.width
/= wide_Bpp
;
655 assert(params
.dst
.tile_x_sa
% wide_Bpp
== 0);
656 params
.dst
.tile_x_sa
/= wide_Bpp
;
658 params
.x0
= params
.dst
.tile_x_sa
+ x0
/ (wide_Bpp
/ 2);
659 params
.y0
= params
.dst
.tile_y_sa
+ y0
/ 2;
660 params
.x1
= params
.dst
.tile_x_sa
+ x1
/ (wide_Bpp
/ 2);
661 params
.y1
= params
.dst
.tile_y_sa
+ y1
/ 2;
663 batch
->blorp
->exec(batch
, ¶ms
);
670 blorp_clear_depth_stencil(struct blorp_batch
*batch
,
671 const struct blorp_surf
*depth
,
672 const struct blorp_surf
*stencil
,
673 uint32_t level
, uint32_t start_layer
,
675 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
676 bool clear_depth
, float depth_value
,
677 uint8_t stencil_mask
, uint8_t stencil_value
)
679 if (!clear_depth
&& blorp_clear_stencil_as_rgba(batch
, stencil
, level
,
680 start_layer
, num_layers
,
686 struct blorp_params params
;
687 blorp_params_init(¶ms
);
694 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) == 6) {
695 /* For some reason, Sandy Bridge gets occlusion queries wrong if we
696 * don't have a shader. In particular, it records samples even though
697 * we disable statistics in 3DSTATE_WM. Give it the usual clear shader
698 * to work around the issue.
700 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, false, false))
704 while (num_layers
> 0) {
705 params
.num_layers
= num_layers
;
708 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
710 ISL_FORMAT_UNSUPPORTED
, true);
711 params
.stencil_mask
= stencil_mask
;
712 params
.stencil_ref
= stencil_value
;
714 params
.dst
.surf
.samples
= params
.stencil
.surf
.samples
;
715 params
.dst
.surf
.logical_level0_px
=
716 params
.stencil
.surf
.logical_level0_px
;
717 params
.dst
.view
= params
.stencil
.view
;
719 params
.num_samples
= params
.stencil
.surf
.samples
;
721 /* We may be restricted on the number of layers we can bind at any
722 * one time. In particular, Sandy Bridge has a maximum number of
723 * layers of 512 but a maximum 3D texture size is much larger.
725 if (params
.stencil
.view
.array_len
< params
.num_layers
)
726 params
.num_layers
= params
.stencil
.view
.array_len
;
730 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
732 ISL_FORMAT_UNSUPPORTED
, true);
733 params
.z
= depth_value
;
734 params
.depth_format
=
735 isl_format_get_depth_format(depth
->surf
->format
, false);
737 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
738 params
.dst
.surf
.logical_level0_px
=
739 params
.depth
.surf
.logical_level0_px
;
740 params
.dst
.view
= params
.depth
.view
;
742 params
.num_samples
= params
.depth
.surf
.samples
;
744 /* We may be restricted on the number of layers we can bind at any
745 * one time. In particular, Sandy Bridge has a maximum number of
746 * layers of 512 but a maximum 3D texture size is much larger.
748 if (params
.depth
.view
.array_len
< params
.num_layers
)
749 params
.num_layers
= params
.depth
.view
.array_len
;
752 batch
->blorp
->exec(batch
, ¶ms
);
754 start_layer
+= params
.num_layers
;
755 num_layers
-= params
.num_layers
;
760 blorp_can_hiz_clear_depth(const struct gen_device_info
*devinfo
,
761 const struct isl_surf
*surf
,
762 enum isl_aux_usage aux_usage
,
763 uint32_t level
, uint32_t layer
,
764 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
766 /* This function currently doesn't support any gen prior to gen8 */
767 assert(devinfo
->gen
>= 8);
769 if (devinfo
->gen
== 8 && surf
->format
== ISL_FORMAT_R16_UNORM
) {
770 /* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample
771 * block with the following property: as the number of samples increases,
772 * the number of pixels representable by this block decreases by a factor
773 * of the sample dimensions. Sample dimensions scale following the MSAA
774 * interleaved pattern.
776 * Sample|Sample|Pixel
778 * ===================
785 * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
787 const struct isl_extent2d sa_block_dim
=
788 isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
789 const uint8_t align_px_w
= 8 / sa_block_dim
.w
;
790 const uint8_t align_px_h
= 4 / sa_block_dim
.h
;
792 /* Fast depth clears clear an entire sample block at a time. As a result,
793 * the rectangle must be aligned to the dimensions of the encompassing
794 * pixel block for a successful operation.
796 * Fast clears can still work if the upper-left corner is aligned and the
797 * bottom-rigtht corner touches the edge of a depth buffer whose extent
798 * is unaligned. This is because each miplevel in the depth buffer is
799 * padded by the Pixel Dim (similar to a standard compressed texture).
800 * In this case, the clear rectangle could be padded by to match the full
801 * depth buffer extent but to support multiple clearing techniques, we
802 * chose to be unaware of the depth buffer's extent and thus don't handle
805 if (x0
% align_px_w
|| y0
% align_px_h
||
806 x1
% align_px_w
|| y1
% align_px_h
)
808 } else if (isl_surf_supports_hiz_ccs_wt(devinfo
, surf
, aux_usage
)) {
809 /* We have to set the WM_HZ_OP::FullSurfaceDepthandStencilClear bit
810 * whenever we clear an uninitialized HIZ buffer (as some drivers
811 * currently do). However, this bit seems liable to clear 16x8 pixels in
812 * the ZCS on Gen12 - greater than the slice alignments for depth
815 assert(surf
->image_alignment_el
.w
% 16 != 0 ||
816 surf
->image_alignment_el
.h
% 8 != 0);
818 /* This is the hypothesis behind some corruption that was seen with the
819 * amd_vertex_shader_layer-layered-depth-texture-render piglit test.
821 * From the Compressed Depth Buffers section of the Bspec, under the
822 * Gen12 texture performant and ZCS columns:
824 * Update with clear at either 16x8 or 8x4 granularity, based on
825 * fs_clr or otherwise.
827 * There are a number of ways to avoid full surface CCS clears that
828 * overlap other slices, but for now we choose to disable fast-clears
829 * when an initializing clear could hit another miplevel.
831 * NOTE: Because the CCS compresses the depth buffer and not a version
832 * of it that has been rearranged with different alignments (like Gen8+
833 * HIZ), we have to make sure that the x0 and y0 are at least 16x8
834 * aligned in the context of the entire surface.
836 uint32_t slice_x0
, slice_y0
;
837 isl_surf_get_image_offset_el(surf
, level
,
838 surf
->dim
== ISL_SURF_DIM_3D
? 0 : layer
,
839 surf
->dim
== ISL_SURF_DIM_3D
? layer
: 0,
840 &slice_x0
, &slice_y0
);
841 const bool max_x1_y1
=
842 x1
== minify(surf
->logical_level0_px
.width
, level
) &&
843 y1
== minify(surf
->logical_level0_px
.height
, level
);
844 const uint32_t haligned_x1
= ALIGN(x1
, surf
->image_alignment_el
.w
);
845 const uint32_t valigned_y1
= ALIGN(y1
, surf
->image_alignment_el
.h
);
846 const bool unaligned
= (slice_x0
+ x0
) % 16 || (slice_y0
+ y0
) % 8 ||
847 max_x1_y1
? haligned_x1
% 16 || valigned_y1
% 8 :
849 const bool alignment_used
= surf
->levels
> 1 ||
850 surf
->logical_level0_px
.depth
> 1 ||
851 surf
->logical_level0_px
.array_len
> 1;
853 if (unaligned
&& alignment_used
)
857 return isl_aux_usage_has_hiz(aux_usage
);
861 blorp_hiz_clear_depth_stencil(struct blorp_batch
*batch
,
862 const struct blorp_surf
*depth
,
863 const struct blorp_surf
*stencil
,
865 uint32_t start_layer
, uint32_t num_layers
,
866 uint32_t x0
, uint32_t y0
,
867 uint32_t x1
, uint32_t y1
,
868 bool clear_depth
, float depth_value
,
869 bool clear_stencil
, uint8_t stencil_value
)
871 struct blorp_params params
;
872 blorp_params_init(¶ms
);
874 /* This requires WM_HZ_OP which only exists on gen8+ */
875 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8);
877 params
.hiz_op
= ISL_AUX_OP_FAST_CLEAR
;
878 params
.num_layers
= 1;
885 for (uint32_t l
= 0; l
< num_layers
; l
++) {
886 const uint32_t layer
= start_layer
+ l
;
888 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
890 ISL_FORMAT_UNSUPPORTED
, true);
891 params
.stencil_mask
= 0xff;
892 params
.stencil_ref
= stencil_value
;
893 params
.num_samples
= params
.stencil
.surf
.samples
;
897 /* If we're clearing depth, we must have HiZ */
898 assert(depth
&& depth
->aux_usage
== ISL_AUX_USAGE_HIZ
);
900 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
902 ISL_FORMAT_UNSUPPORTED
, true);
903 params
.depth
.clear_color
.f32
[0] = depth_value
;
904 params
.depth_format
=
905 isl_format_get_depth_format(depth
->surf
->format
, false);
906 params
.num_samples
= params
.depth
.surf
.samples
;
909 batch
->blorp
->exec(batch
, ¶ms
);
913 /* Given a depth stencil attachment, this function performs a fast depth clear
914 * on a depth portion and a regular clear on the stencil portion. When
915 * performing a fast depth clear on the depth portion, the HiZ buffer is simply
916 * tagged as cleared so the depth clear value is not actually needed.
919 blorp_gen8_hiz_clear_attachments(struct blorp_batch
*batch
,
920 uint32_t num_samples
,
921 uint32_t x0
, uint32_t y0
,
922 uint32_t x1
, uint32_t y1
,
923 bool clear_depth
, bool clear_stencil
,
924 uint8_t stencil_value
)
926 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
928 struct blorp_params params
;
929 blorp_params_init(¶ms
);
930 params
.num_layers
= 1;
931 params
.hiz_op
= ISL_AUX_OP_FAST_CLEAR
;
936 params
.num_samples
= num_samples
;
937 params
.depth
.enabled
= clear_depth
;
938 params
.stencil
.enabled
= clear_stencil
;
939 params
.stencil_ref
= stencil_value
;
940 batch
->blorp
->exec(batch
, ¶ms
);
943 /** Clear active color/depth/stencili attachments
945 * This function performs a clear operation on the currently bound
946 * color/depth/stencil attachments. It is assumed that any information passed
947 * in here is valid, consistent, and in-bounds relative to the currently
948 * attached depth/stencil. The binding_table_offset parameter is the 32-bit
949 * offset relative to surface state base address where pre-baked binding table
950 * that we are to use lives. If clear_color is false, binding_table_offset
951 * must point to a binding table with one entry which is a valid null surface
952 * that matches the currently bound depth and stencil.
955 blorp_clear_attachments(struct blorp_batch
*batch
,
956 uint32_t binding_table_offset
,
957 enum isl_format depth_format
,
958 uint32_t num_samples
,
959 uint32_t start_layer
, uint32_t num_layers
,
960 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
961 bool clear_color
, union isl_color_value color_value
,
962 bool clear_depth
, float depth_value
,
963 uint8_t stencil_mask
, uint8_t stencil_value
)
965 struct blorp_params params
;
966 blorp_params_init(¶ms
);
968 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
975 params
.use_pre_baked_binding_table
= true;
976 params
.pre_baked_binding_table_offset
= binding_table_offset
;
978 params
.num_layers
= num_layers
;
979 params
.num_samples
= num_samples
;
982 params
.dst
.enabled
= true;
984 memcpy(¶ms
.wm_inputs
.clear_color
, color_value
.f32
, sizeof(float) * 4);
986 /* Unfortunately, without knowing whether or not our destination surface
987 * is tiled or not, we have to assume it may be linear. This means no
988 * SIMD16_REPDATA for us. :-(
990 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, false, false))
995 params
.depth
.enabled
= true;
997 params
.z
= depth_value
;
998 params
.depth_format
= isl_format_get_depth_format(depth_format
, false);
1002 params
.stencil
.enabled
= true;
1004 params
.stencil_mask
= stencil_mask
;
1005 params
.stencil_ref
= stencil_value
;
1008 if (!blorp_params_get_layer_offset_vs(batch
, ¶ms
))
1011 params
.vs_inputs
.base_layer
= start_layer
;
1013 batch
->blorp
->exec(batch
, ¶ms
);
1017 blorp_ccs_resolve(struct blorp_batch
*batch
,
1018 struct blorp_surf
*surf
, uint32_t level
,
1019 uint32_t start_layer
, uint32_t num_layers
,
1020 enum isl_format format
,
1021 enum isl_aux_op resolve_op
)
1023 struct blorp_params params
;
1025 blorp_params_init(¶ms
);
1026 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
,
1027 level
, start_layer
, format
, true);
1029 /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
1031 * A rectangle primitive must be scaled down by the following factors
1032 * with respect to render target being resolved.
1034 * The scaledown factors in the table that follows are related to the block
1035 * size of the CCS format. For IVB and HSW, we divide by two, for BDW we
1036 * multiply by 8 and 16. On Sky Lake, we multiply by 8.
1038 const struct isl_format_layout
*aux_fmtl
=
1039 isl_format_get_layout(params
.dst
.aux_surf
.format
);
1040 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
1042 unsigned x_scaledown
, y_scaledown
;
1043 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 12) {
1044 x_scaledown
= aux_fmtl
->bw
* 8;
1045 y_scaledown
= aux_fmtl
->bh
* 4;
1046 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 9) {
1047 x_scaledown
= aux_fmtl
->bw
* 8;
1048 y_scaledown
= aux_fmtl
->bh
* 8;
1049 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
1050 x_scaledown
= aux_fmtl
->bw
* 8;
1051 y_scaledown
= aux_fmtl
->bh
* 16;
1053 x_scaledown
= aux_fmtl
->bw
/ 2;
1054 y_scaledown
= aux_fmtl
->bh
/ 2;
1056 params
.x0
= params
.y0
= 0;
1057 params
.x1
= minify(params
.dst
.surf
.logical_level0_px
.width
, level
);
1058 params
.y1
= minify(params
.dst
.surf
.logical_level0_px
.height
, level
);
1059 params
.x1
= ALIGN(params
.x1
, x_scaledown
) / x_scaledown
;
1060 params
.y1
= ALIGN(params
.y1
, y_scaledown
) / y_scaledown
;
1062 if (batch
->blorp
->isl_dev
->info
->gen
>= 10) {
1063 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
||
1064 resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
||
1065 resolve_op
== ISL_AUX_OP_AMBIGUATE
);
1066 } else if (batch
->blorp
->isl_dev
->info
->gen
>= 9) {
1067 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
||
1068 resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
1070 /* Broadwell and earlier do not have a partial resolve */
1071 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
);
1073 params
.fast_clear_op
= resolve_op
;
1074 params
.num_layers
= num_layers
;
1076 /* Note: there is no need to initialize push constants because it doesn't
1077 * matter what data gets dispatched to the render target. However, we must
1078 * ensure that the fragment shader delivers the data using the "replicated
1082 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
1085 batch
->blorp
->exec(batch
, ¶ms
);
1088 static nir_ssa_def
*
1089 blorp_nir_bit(nir_builder
*b
, nir_ssa_def
*src
, unsigned bit
)
1091 return nir_iand(b
, nir_ushr(b
, src
, nir_imm_int(b
, bit
)),
1095 #pragma pack(push, 1)
1096 struct blorp_mcs_partial_resolve_key
1098 enum blorp_shader_type shader_type
;
1099 bool indirect_clear_color
;
1101 uint32_t num_samples
;
1106 blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch
*batch
,
1107 struct blorp_params
*params
)
1109 struct blorp_context
*blorp
= batch
->blorp
;
1110 const struct blorp_mcs_partial_resolve_key blorp_key
= {
1111 .shader_type
= BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE
,
1112 .indirect_clear_color
= params
->dst
.clear_color_addr
.buffer
!= NULL
,
1113 .int_format
= isl_format_has_int_channel(params
->dst
.view
.format
),
1114 .num_samples
= params
->num_samples
,
1117 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
1118 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1121 void *mem_ctx
= ralloc_context(NULL
);
1124 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
,
1125 "BLORP-mcs-partial-resolve");
1127 nir_variable
*v_color
=
1128 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
1130 nir_variable
*frag_color
=
1131 nir_variable_create(b
.shader
, nir_var_shader_out
,
1132 glsl_vec4_type(), "gl_FragColor");
1133 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
1135 /* Do an MCS fetch and check if it is equal to the magic clear value */
1137 blorp_nir_txf_ms_mcs(&b
, nir_f2i32(&b
, nir_load_frag_coord(&b
)),
1138 nir_load_layer_id(&b
));
1139 nir_ssa_def
*is_clear
=
1140 blorp_nir_mcs_is_clear_color(&b
, mcs
, blorp_key
.num_samples
);
1142 /* If we aren't the clear value, discard. */
1143 nir_intrinsic_instr
*discard
=
1144 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_discard_if
);
1145 discard
->src
[0] = nir_src_for_ssa(nir_inot(&b
, is_clear
));
1146 nir_builder_instr_insert(&b
, &discard
->instr
);
1148 nir_ssa_def
*clear_color
= nir_load_var(&b
, v_color
);
1149 if (blorp_key
.indirect_clear_color
&& blorp
->isl_dev
->info
->gen
<= 8) {
1150 /* Gen7-8 clear colors are stored as single 0/1 bits */
1151 clear_color
= nir_vec4(&b
, blorp_nir_bit(&b
, clear_color
, 31),
1152 blorp_nir_bit(&b
, clear_color
, 30),
1153 blorp_nir_bit(&b
, clear_color
, 29),
1154 blorp_nir_bit(&b
, clear_color
, 28));
1156 if (!blorp_key
.int_format
)
1157 clear_color
= nir_i2f32(&b
, clear_color
);
1159 nir_store_var(&b
, frag_color
, clear_color
, 0xf);
1161 struct brw_wm_prog_key wm_key
;
1162 brw_blorp_init_wm_prog_key(&wm_key
);
1163 wm_key
.base
.tex
.compressed_multisample_layout_mask
= 1;
1164 wm_key
.base
.tex
.msaa_16
= blorp_key
.num_samples
== 16;
1165 wm_key
.multisample_fbo
= true;
1167 struct brw_wm_prog_data prog_data
;
1168 const unsigned *program
=
1169 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, false,
1173 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
1174 program
, prog_data
.base
.program_size
,
1175 &prog_data
.base
, sizeof(prog_data
),
1176 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1178 ralloc_free(mem_ctx
);
1183 blorp_mcs_partial_resolve(struct blorp_batch
*batch
,
1184 struct blorp_surf
*surf
,
1185 enum isl_format format
,
1186 uint32_t start_layer
, uint32_t num_layers
)
1188 struct blorp_params params
;
1189 blorp_params_init(¶ms
);
1191 assert(batch
->blorp
->isl_dev
->info
->gen
>= 7);
1195 params
.x1
= surf
->surf
->logical_level0_px
.width
;
1196 params
.y1
= surf
->surf
->logical_level0_px
.height
;
1198 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, surf
, 0,
1199 start_layer
, format
, false);
1200 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, 0,
1201 start_layer
, format
, true);
1203 params
.num_samples
= params
.dst
.surf
.samples
;
1204 params
.num_layers
= num_layers
;
1205 params
.dst_clear_color_as_input
= surf
->clear_color_addr
.buffer
!= NULL
;
1207 memcpy(¶ms
.wm_inputs
.clear_color
,
1208 surf
->clear_color
.f32
, sizeof(float) * 4);
1210 if (!blorp_params_get_mcs_partial_resolve_kernel(batch
, ¶ms
))
1213 batch
->blorp
->exec(batch
, ¶ms
);
1216 /** Clear a CCS to the "uncompressed" state
1218 * This pass is the CCS equivalent of a "HiZ resolve". It sets the CCS values
1219 * for a given layer/level of a surface to 0x0 which is the "uncompressed"
1220 * state which tells the sampler to go look at the main surface.
1223 blorp_ccs_ambiguate(struct blorp_batch
*batch
,
1224 struct blorp_surf
*surf
,
1225 uint32_t level
, uint32_t layer
)
1227 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 10) {
1228 /* On gen10 and above, we have a hardware resolve op for this */
1229 return blorp_ccs_resolve(batch
, surf
, level
, layer
, 1,
1230 surf
->surf
->format
, ISL_AUX_OP_AMBIGUATE
);
1233 struct blorp_params params
;
1234 blorp_params_init(¶ms
);
1236 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 7);
1238 const struct isl_format_layout
*aux_fmtl
=
1239 isl_format_get_layout(surf
->aux_surf
->format
);
1240 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
1242 params
.dst
= (struct brw_blorp_surface_info
) {
1244 .addr
= surf
->aux_addr
,
1246 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1247 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
1249 .base_array_layer
= 0,
1252 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1257 if (surf
->surf
->dim
== ISL_SURF_DIM_3D
) {
1262 uint32_t offset_B
, x_offset_el
, y_offset_el
;
1263 isl_surf_get_image_offset_el(surf
->aux_surf
, level
, layer
, z
,
1264 &x_offset_el
, &y_offset_el
);
1265 isl_tiling_get_intratile_offset_el(surf
->aux_surf
->tiling
, aux_fmtl
->bpb
,
1266 surf
->aux_surf
->row_pitch_B
,
1267 x_offset_el
, y_offset_el
,
1268 &offset_B
, &x_offset_el
, &y_offset_el
);
1269 params
.dst
.addr
.offset
+= offset_B
;
1271 const uint32_t width_px
=
1272 minify(surf
->aux_surf
->logical_level0_px
.width
, level
);
1273 const uint32_t height_px
=
1274 minify(surf
->aux_surf
->logical_level0_px
.height
, level
);
1275 const uint32_t width_el
= DIV_ROUND_UP(width_px
, aux_fmtl
->bw
);
1276 const uint32_t height_el
= DIV_ROUND_UP(height_px
, aux_fmtl
->bh
);
1278 struct isl_tile_info ccs_tile_info
;
1279 isl_surf_get_tile_info(surf
->aux_surf
, &ccs_tile_info
);
1281 /* We're going to map it as a regular RGBA32_UINT surface. We need to
1282 * downscale a good deal. We start by computing the area on the CCS to
1283 * clear in units of Y-tiled cache lines.
1285 uint32_t x_offset_cl
, y_offset_cl
, width_cl
, height_cl
;
1286 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
1287 /* From the Sky Lake PRM Vol. 12 in the section on planes:
1289 * "The Color Control Surface (CCS) contains the compression status
1290 * of the cache-line pairs. The compression state of the cache-line
1291 * pair is specified by 2 bits in the CCS. Each CCS cache-line
1292 * represents an area on the main surface of 16x16 sets of 128 byte
1293 * Y-tiled cache-line-pairs. CCS is always Y tiled."
1295 * Each 2-bit surface element in the CCS corresponds to a single
1296 * cache-line pair in the main surface. This means that 16x16 el block
1297 * in the CCS maps to a Y-tiled cache line. Fortunately, CCS layouts
1298 * are calculated with a very large alignment so we can round up to a
1299 * whole cache line without worrying about overdraw.
1302 /* On Broadwell and above, a CCS tile is the same as a Y tile when
1303 * viewed at the cache-line granularity. Fortunately, the horizontal
1304 * and vertical alignment requirements of the CCS are such that we can
1305 * align to an entire cache line without worrying about crossing over
1306 * from one LOD to another.
1308 const uint32_t x_el_per_cl
= ccs_tile_info
.logical_extent_el
.w
/ 8;
1309 const uint32_t y_el_per_cl
= ccs_tile_info
.logical_extent_el
.h
/ 8;
1310 assert(surf
->aux_surf
->image_alignment_el
.w
% x_el_per_cl
== 0);
1311 assert(surf
->aux_surf
->image_alignment_el
.h
% y_el_per_cl
== 0);
1313 assert(x_offset_el
% x_el_per_cl
== 0);
1314 assert(y_offset_el
% y_el_per_cl
== 0);
1315 x_offset_cl
= x_offset_el
/ x_el_per_cl
;
1316 y_offset_cl
= y_offset_el
/ y_el_per_cl
;
1317 width_cl
= DIV_ROUND_UP(width_el
, x_el_per_cl
);
1318 height_cl
= DIV_ROUND_UP(height_el
, y_el_per_cl
);
1320 /* On gen7, the CCS tiling is not so nice. However, there we are
1321 * guaranteed that we only have a single level and slice so we don't
1322 * have to worry about it and can just align to a whole tile.
1324 assert(surf
->aux_surf
->logical_level0_px
.depth
== 1);
1325 assert(surf
->aux_surf
->logical_level0_px
.array_len
== 1);
1326 assert(x_offset_el
== 0 && y_offset_el
== 0);
1327 const uint32_t width_tl
=
1328 DIV_ROUND_UP(width_el
, ccs_tile_info
.logical_extent_el
.w
);
1329 const uint32_t height_tl
=
1330 DIV_ROUND_UP(height_el
, ccs_tile_info
.logical_extent_el
.h
);
1333 width_cl
= width_tl
* 8;
1334 height_cl
= height_tl
* 8;
1337 /* We're going to use a RGBA32 format so as to write data as quickly as
1338 * possible. A y-tiled cache line will then be 1x4 px.
1340 const uint32_t x_offset_rgba_px
= x_offset_cl
;
1341 const uint32_t y_offset_rgba_px
= y_offset_cl
* 4;
1342 const uint32_t width_rgba_px
= width_cl
;
1343 const uint32_t height_rgba_px
= height_cl
* 4;
1346 isl_surf_init(batch
->blorp
->isl_dev
, ¶ms
.dst
.surf
,
1347 .dim
= ISL_SURF_DIM_2D
,
1348 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
1349 .width
= width_rgba_px
+ x_offset_rgba_px
,
1350 .height
= height_rgba_px
+ y_offset_rgba_px
,
1355 .row_pitch_B
= surf
->aux_surf
->row_pitch_B
,
1356 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1357 .tiling_flags
= ISL_TILING_Y0_BIT
);
1360 params
.x0
= x_offset_rgba_px
;
1361 params
.y0
= y_offset_rgba_px
;
1362 params
.x1
= x_offset_rgba_px
+ width_rgba_px
;
1363 params
.y1
= y_offset_rgba_px
+ height_rgba_px
;
1365 /* A CCS value of 0 means "uncompressed." */
1366 memset(¶ms
.wm_inputs
.clear_color
, 0,
1367 sizeof(params
.wm_inputs
.clear_color
));
1369 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
1372 batch
->blorp
->exec(batch
, ¶ms
);