2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/ralloc.h"
26 #include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
27 #include "util/format_rgb9e5.h"
29 #include "blorp_priv.h"
30 #include "compiler/brw_eu_defines.h"
32 #include "compiler/nir/nir_builder.h"
34 #define FILE_DEBUG_FLAG DEBUG_BLORP
36 struct brw_blorp_const_color_prog_key
38 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_CLEAR */
39 bool use_simd16_replicated_data
;
44 blorp_params_get_clear_kernel(struct blorp_context
*blorp
,
45 struct blorp_params
*params
,
46 bool use_replicated_data
)
48 const struct brw_blorp_const_color_prog_key blorp_key
= {
49 .shader_type
= BLORP_SHADER_TYPE_CLEAR
,
50 .use_simd16_replicated_data
= use_replicated_data
,
53 if (blorp
->lookup_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
54 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
57 void *mem_ctx
= ralloc_context(NULL
);
60 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
61 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, "BLORP-clear");
63 nir_variable
*v_color
=
64 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
66 nir_variable
*frag_color
= nir_variable_create(b
.shader
, nir_var_shader_out
,
69 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
71 nir_copy_var(&b
, frag_color
, v_color
);
73 struct brw_wm_prog_key wm_key
;
74 brw_blorp_init_wm_prog_key(&wm_key
);
76 struct brw_wm_prog_data prog_data
;
77 unsigned program_size
;
78 const unsigned *program
=
79 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, use_replicated_data
,
80 &prog_data
, &program_size
);
83 blorp
->upload_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
84 program
, program_size
,
85 &prog_data
.base
, sizeof(prog_data
),
86 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
92 struct layer_offset_vs_key
{
93 enum blorp_shader_type shader_type
;
97 /* In the case of doing attachment clears, we are using a surface state that
98 * is handed to us so we can't set (and don't even know) the base array layer.
99 * In order to do a layered clear in this scenario, we need some way of adding
100 * the base array layer to the instance id. Unfortunately, our hardware has
101 * no real concept of "base instance", so we have to do it manually in a
105 blorp_params_get_layer_offset_vs(struct blorp_context
*blorp
,
106 struct blorp_params
*params
)
108 struct layer_offset_vs_key blorp_key
= {
109 .shader_type
= BLORP_SHADER_TYPE_LAYER_OFFSET_VS
,
112 if (params
->wm_prog_data
)
113 blorp_key
.num_inputs
= params
->wm_prog_data
->num_varying_inputs
;
115 if (blorp
->lookup_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
116 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
))
119 void *mem_ctx
= ralloc_context(NULL
);
122 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_VERTEX
, NULL
);
123 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, "BLORP-layer-offset-vs");
125 const struct glsl_type
*uvec4_type
= glsl_vector_type(GLSL_TYPE_UINT
, 4);
127 /* First we deal with the header which has instance and base instance */
128 nir_variable
*a_header
= nir_variable_create(b
.shader
, nir_var_shader_in
,
129 uvec4_type
, "header");
130 a_header
->data
.location
= VERT_ATTRIB_GENERIC0
;
132 nir_variable
*v_layer
= nir_variable_create(b
.shader
, nir_var_shader_out
,
133 glsl_int_type(), "layer_id");
134 v_layer
->data
.location
= VARYING_SLOT_LAYER
;
136 /* Compute the layer id */
137 nir_ssa_def
*header
= nir_load_var(&b
, a_header
);
138 nir_ssa_def
*base_layer
= nir_channel(&b
, header
, 0);
139 nir_ssa_def
*instance
= nir_channel(&b
, header
, 1);
140 nir_store_var(&b
, v_layer
, nir_iadd(&b
, instance
, base_layer
), 0x1);
142 /* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
143 nir_variable
*a_vertex
= nir_variable_create(b
.shader
, nir_var_shader_in
,
144 glsl_vec4_type(), "a_vertex");
145 a_vertex
->data
.location
= VERT_ATTRIB_GENERIC1
;
147 nir_variable
*v_pos
= nir_variable_create(b
.shader
, nir_var_shader_out
,
148 glsl_vec4_type(), "v_pos");
149 v_pos
->data
.location
= VARYING_SLOT_POS
;
151 nir_copy_var(&b
, v_pos
, a_vertex
);
153 /* Then we copy everything else */
154 for (unsigned i
= 0; i
< blorp_key
.num_inputs
; i
++) {
155 nir_variable
*a_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
156 uvec4_type
, "input");
157 a_in
->data
.location
= VERT_ATTRIB_GENERIC2
+ i
;
159 nir_variable
*v_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
160 uvec4_type
, "output");
161 v_out
->data
.location
= VARYING_SLOT_VAR0
+ i
;
163 nir_copy_var(&b
, v_out
, a_in
);
166 struct brw_vs_prog_data vs_prog_data
;
167 memset(&vs_prog_data
, 0, sizeof(vs_prog_data
));
169 unsigned program_size
;
170 const unsigned *program
=
171 blorp_compile_vs(blorp
, mem_ctx
, b
.shader
, &vs_prog_data
, &program_size
);
174 blorp
->upload_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
175 program
, program_size
,
176 &vs_prog_data
.base
.base
, sizeof(vs_prog_data
),
177 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
);
179 ralloc_free(mem_ctx
);
183 /* The x0, y0, x1, and y1 parameters must already be populated with the render
184 * area of the framebuffer to be cleared.
187 get_fast_clear_rect(const struct isl_device
*dev
,
188 const struct isl_surf
*aux_surf
,
189 unsigned *x0
, unsigned *y0
,
190 unsigned *x1
, unsigned *y1
)
192 unsigned int x_align
, y_align
;
193 unsigned int x_scaledown
, y_scaledown
;
195 /* Only single sampled surfaces need to (and actually can) be resolved. */
196 if (aux_surf
->usage
== ISL_SURF_USAGE_CCS_BIT
) {
197 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
198 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
200 * Clear pass must have a clear rectangle that must follow
201 * alignment rules in terms of pixels and lines as shown in the
202 * table below. Further, the clear-rectangle height and width
203 * must be multiple of the following dimensions. If the height
204 * and width of the render target being cleared do not meet these
205 * requirements, an MCS buffer can be created such that it
206 * follows the requirement and covers the RT.
208 * The alignment size in the table that follows is related to the
209 * alignment size that is baked into the CCS surface format but with X
210 * alignment multiplied by 16 and Y alignment multiplied by 32.
212 x_align
= isl_format_get_layout(aux_surf
->format
)->bw
;
213 y_align
= isl_format_get_layout(aux_surf
->format
)->bh
;
217 /* SKL+ line alignment requirement for Y-tiled are half those of the prior
220 if (dev
->info
->gen
>= 9)
225 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
226 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
228 * In order to optimize the performance MCS buffer (when bound to
229 * 1X RT) clear similarly to MCS buffer clear for MSRT case,
230 * clear rect is required to be scaled by the following factors
231 * in the horizontal and vertical directions:
233 * The X and Y scale down factors in the table that follows are each
234 * equal to half the alignment value computed above.
236 x_scaledown
= x_align
/ 2;
237 y_scaledown
= y_align
/ 2;
239 /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
240 * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
241 * Clear of Non-MultiSampled Render Target Restrictions":
243 * Clear rectangle must be aligned to two times the number of
244 * pixels in the table shown below due to 16x16 hashing across the
250 assert(aux_surf
->usage
== ISL_SURF_USAGE_MCS_BIT
);
252 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
253 * Target(s)", beneath the "MSAA Compression" bullet (p326):
255 * Clear pass for this case requires that scaled down primitive
256 * is sent down with upper left co-ordinate to coincide with
257 * actual rectangle being cleared. For MSAA, clear rectangle’s
258 * height and width need to as show in the following table in
259 * terms of (width,height) of the RT.
261 * MSAA Width of Clear Rect Height of Clear Rect
262 * 2X Ceil(1/8*width) Ceil(1/2*height)
263 * 4X Ceil(1/8*width) Ceil(1/2*height)
264 * 8X Ceil(1/2*width) Ceil(1/2*height)
265 * 16X width Ceil(1/2*height)
267 * The text "with upper left co-ordinate to coincide with actual
268 * rectangle being cleared" is a little confusing--it seems to imply
269 * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
270 * feed the pipeline using the rectangle (x,y) to
271 * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
272 * the number of samples. Experiments indicate that this is not
273 * quite correct; actually, what the hardware appears to do is to
274 * align whatever rectangle is sent down the pipeline to the nearest
275 * multiple of 2x2 blocks, and then scale it up by a factor of N
276 * horizontally and 2 vertically. So the resulting alignment is 4
277 * vertically and either 4 or 16 horizontally, and the scaledown
278 * factor is 2 vertically and either 2 or 8 horizontally.
280 switch (aux_surf
->format
) {
281 case ISL_FORMAT_MCS_2X
:
282 case ISL_FORMAT_MCS_4X
:
285 case ISL_FORMAT_MCS_8X
:
288 case ISL_FORMAT_MCS_16X
:
292 unreachable("Unexpected MCS format for fast clear");
295 x_align
= x_scaledown
* 2;
296 y_align
= y_scaledown
* 2;
299 *x0
= ROUND_DOWN_TO(*x0
, x_align
) / x_scaledown
;
300 *y0
= ROUND_DOWN_TO(*y0
, y_align
) / y_scaledown
;
301 *x1
= ALIGN(*x1
, x_align
) / x_scaledown
;
302 *y1
= ALIGN(*y1
, y_align
) / y_scaledown
;
306 blorp_fast_clear(struct blorp_batch
*batch
,
307 const struct blorp_surf
*surf
, enum isl_format format
,
308 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
309 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
311 struct blorp_params params
;
312 blorp_params_init(¶ms
);
313 params
.num_layers
= num_layers
;
320 memset(¶ms
.wm_inputs
.clear_color
, 0xff, 4*sizeof(float));
321 params
.fast_clear_op
= BLORP_FAST_CLEAR_OP_CLEAR
;
323 get_fast_clear_rect(batch
->blorp
->isl_dev
, surf
->aux_surf
,
324 ¶ms
.x0
, ¶ms
.y0
, ¶ms
.x1
, ¶ms
.y1
);
326 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, true))
329 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
330 start_layer
, format
, true);
331 params
.num_samples
= params
.dst
.surf
.samples
;
333 batch
->blorp
->exec(batch
, ¶ms
);
336 static union isl_color_value
337 swizzle_color_value(union isl_color_value src
, struct isl_swizzle swizzle
)
339 union isl_color_value dst
= { .u32
= { 0, } };
341 /* We assign colors in ABGR order so that the first one will be taken in
342 * RGBA precedence order. According to the PRM docs for shader channel
343 * select, this matches Haswell hardware behavior.
345 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
346 dst
.u32
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[3];
347 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
348 dst
.u32
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[2];
349 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
350 dst
.u32
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[1];
351 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
352 dst
.u32
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[0];
358 blorp_clear(struct blorp_batch
*batch
,
359 const struct blorp_surf
*surf
,
360 enum isl_format format
, struct isl_swizzle swizzle
,
361 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
362 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
363 union isl_color_value clear_color
,
364 const bool color_write_disable
[4])
366 struct blorp_params params
;
367 blorp_params_init(¶ms
);
374 /* Manually apply the clear destination swizzle. This way swizzled clears
375 * will work for swizzles which we can't normally use for rendering and it
376 * also ensures that they work on pre-Haswell hardware which can't swizlle
379 clear_color
= swizzle_color_value(clear_color
, swizzle
);
380 swizzle
= ISL_SWIZZLE_IDENTITY
;
382 if (format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
383 clear_color
.u32
[0] = float3_to_rgb9e5(clear_color
.f32
);
384 format
= ISL_FORMAT_R32_UINT
;
385 } else if (format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
386 /* Broadwell and earlier cannot render to this format so we need to work
387 * around it by swapping the colors around and using B4G4R4A4 instead.
389 const struct isl_swizzle ARGB
= ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
);
390 clear_color
= swizzle_color_value(clear_color
, ARGB
);
391 format
= ISL_FORMAT_B4G4R4A4_UNORM
;
394 memcpy(¶ms
.wm_inputs
.clear_color
, clear_color
.f32
, sizeof(float) * 4);
396 bool use_simd16_replicated_data
= true;
398 /* From the SNB PRM (Vol4_Part1):
400 * "Replicated data (Message Type = 111) is only supported when
401 * accessing tiled memory. Using this Message Type to access linear
402 * (untiled) memory is UNDEFINED."
404 if (surf
->surf
->tiling
== ISL_TILING_LINEAR
)
405 use_simd16_replicated_data
= false;
407 /* Constant color writes ignore everyting in blend and color calculator
408 * state. This is not documented.
410 if (color_write_disable
) {
411 for (unsigned i
= 0; i
< 4; i
++) {
412 params
.color_write_disable
[i
] = color_write_disable
[i
];
413 if (color_write_disable
[i
])
414 use_simd16_replicated_data
= false;
418 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
,
419 use_simd16_replicated_data
))
422 while (num_layers
> 0) {
423 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
424 start_layer
, format
, true);
425 params
.dst
.view
.swizzle
= swizzle
;
427 params
.num_samples
= params
.dst
.surf
.samples
;
429 /* We may be restricted on the number of layers we can bind at any one
430 * time. In particular, Sandy Bridge has a maximum number of layers of
431 * 512 but a maximum 3D texture size is much larger.
433 params
.num_layers
= MIN2(params
.dst
.view
.array_len
, num_layers
);
434 batch
->blorp
->exec(batch
, ¶ms
);
436 start_layer
+= params
.num_layers
;
437 num_layers
-= params
.num_layers
;
442 blorp_clear_depth_stencil(struct blorp_batch
*batch
,
443 const struct blorp_surf
*depth
,
444 const struct blorp_surf
*stencil
,
445 uint32_t level
, uint32_t start_layer
,
447 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
448 bool clear_depth
, float depth_value
,
449 uint8_t stencil_mask
, uint8_t stencil_value
)
451 struct blorp_params params
;
452 blorp_params_init(¶ms
);
459 while (num_layers
> 0) {
460 params
.num_layers
= num_layers
;
463 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
465 ISL_FORMAT_UNSUPPORTED
, true);
466 params
.stencil_mask
= stencil_mask
;
467 params
.stencil_ref
= stencil_value
;
469 params
.dst
.surf
.samples
= params
.stencil
.surf
.samples
;
470 params
.dst
.surf
.logical_level0_px
=
471 params
.stencil
.surf
.logical_level0_px
;
472 params
.dst
.view
= params
.depth
.view
;
474 params
.num_samples
= params
.stencil
.surf
.samples
;
476 /* We may be restricted on the number of layers we can bind at any
477 * one time. In particular, Sandy Bridge has a maximum number of
478 * layers of 512 but a maximum 3D texture size is much larger.
480 if (params
.stencil
.view
.array_len
< params
.num_layers
)
481 params
.num_layers
= params
.stencil
.view
.array_len
;
485 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
487 ISL_FORMAT_UNSUPPORTED
, true);
488 params
.z
= depth_value
;
489 params
.depth_format
=
490 isl_format_get_depth_format(depth
->surf
->format
, false);
492 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
493 params
.dst
.surf
.logical_level0_px
=
494 params
.depth
.surf
.logical_level0_px
;
495 params
.dst
.view
= params
.depth
.view
;
497 params
.num_samples
= params
.depth
.surf
.samples
;
499 /* We may be restricted on the number of layers we can bind at any
500 * one time. In particular, Sandy Bridge has a maximum number of
501 * layers of 512 but a maximum 3D texture size is much larger.
503 if (params
.depth
.view
.array_len
< params
.num_layers
)
504 params
.num_layers
= params
.depth
.view
.array_len
;
507 batch
->blorp
->exec(batch
, ¶ms
);
509 start_layer
+= params
.num_layers
;
510 num_layers
-= params
.num_layers
;
515 blorp_can_hiz_clear_depth(uint8_t gen
, enum isl_format format
,
516 uint32_t num_samples
,
517 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
519 /* This function currently doesn't support any gen prior to gen8 */
522 if (gen
== 8 && format
== ISL_FORMAT_R16_UNORM
) {
523 /* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample
524 * block with the following property: as the number of samples increases,
525 * the number of pixels representable by this block decreases by a factor
526 * of the sample dimensions. Sample dimensions scale following the MSAA
527 * interleaved pattern.
529 * Sample|Sample|Pixel
531 * ===================
538 * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
540 const struct isl_extent2d sa_block_dim
=
541 isl_get_interleaved_msaa_px_size_sa(num_samples
);
542 const uint8_t align_px_w
= 8 / sa_block_dim
.w
;
543 const uint8_t align_px_h
= 4 / sa_block_dim
.h
;
545 /* Fast depth clears clear an entire sample block at a time. As a result,
546 * the rectangle must be aligned to the dimensions of the encompassing
547 * pixel block for a successful operation.
549 * Fast clears can still work if the upper-left corner is aligned and the
550 * bottom-rigtht corner touches the edge of a depth buffer whose extent
551 * is unaligned. This is because each miplevel in the depth buffer is
552 * padded by the Pixel Dim (similar to a standard compressed texture).
553 * In this case, the clear rectangle could be padded by to match the full
554 * depth buffer extent but to support multiple clearing techniques, we
555 * chose to be unaware of the depth buffer's extent and thus don't handle
558 if (x0
% align_px_w
|| y0
% align_px_h
||
559 x1
% align_px_w
|| y1
% align_px_h
)
565 /* Given a depth stencil attachment, this function performs a fast depth clear
566 * on a depth portion and a regular clear on the stencil portion. When
567 * performing a fast depth clear on the depth portion, the HiZ buffer is simply
568 * tagged as cleared so the depth clear value is not actually needed.
571 blorp_gen8_hiz_clear_attachments(struct blorp_batch
*batch
,
572 uint32_t num_samples
,
573 uint32_t x0
, uint32_t y0
,
574 uint32_t x1
, uint32_t y1
,
575 bool clear_depth
, bool clear_stencil
,
576 uint8_t stencil_value
)
578 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
580 struct blorp_params params
;
581 blorp_params_init(¶ms
);
582 params
.num_layers
= 1;
583 params
.hiz_op
= BLORP_HIZ_OP_DEPTH_CLEAR
;
588 params
.num_samples
= num_samples
;
589 params
.depth
.enabled
= clear_depth
;
590 params
.stencil
.enabled
= clear_stencil
;
591 params
.stencil_ref
= stencil_value
;
592 batch
->blorp
->exec(batch
, ¶ms
);
595 /** Clear active color/depth/stencili attachments
597 * This function performs a clear operation on the currently bound
598 * color/depth/stencil attachments. It is assumed that any information passed
599 * in here is valid, consistent, and in-bounds relative to the currently
600 * attached depth/stencil. The binding_table_offset parameter is the 32-bit
601 * offset relative to surface state base address where pre-baked binding table
602 * that we are to use lives. If clear_color is false, binding_table_offset
603 * must point to a binding table with one entry which is a valid null surface
604 * that matches the currently bound depth and stencil.
607 blorp_clear_attachments(struct blorp_batch
*batch
,
608 uint32_t binding_table_offset
,
609 enum isl_format depth_format
,
610 uint32_t num_samples
,
611 uint32_t start_layer
, uint32_t num_layers
,
612 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
613 bool clear_color
, union isl_color_value color_value
,
614 bool clear_depth
, float depth_value
,
615 uint8_t stencil_mask
, uint8_t stencil_value
)
617 struct blorp_params params
;
618 blorp_params_init(¶ms
);
620 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
627 params
.use_pre_baked_binding_table
= true;
628 params
.pre_baked_binding_table_offset
= binding_table_offset
;
630 params
.num_layers
= num_layers
;
631 params
.num_samples
= num_samples
;
634 params
.dst
.enabled
= true;
636 memcpy(¶ms
.wm_inputs
.clear_color
, color_value
.f32
, sizeof(float) * 4);
638 /* Unfortunately, without knowing whether or not our destination surface
639 * is tiled or not, we have to assume it may be linear. This means no
640 * SIMD16_REPDATA for us. :-(
642 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, false))
647 params
.depth
.enabled
= true;
649 params
.z
= depth_value
;
650 params
.depth_format
= isl_format_get_depth_format(depth_format
, false);
654 params
.stencil
.enabled
= true;
656 params
.stencil_mask
= stencil_mask
;
657 params
.stencil_ref
= stencil_value
;
660 if (!blorp_params_get_layer_offset_vs(batch
->blorp
, ¶ms
))
663 params
.vs_inputs
.base_layer
= start_layer
;
665 batch
->blorp
->exec(batch
, ¶ms
);
669 blorp_ccs_resolve(struct blorp_batch
*batch
,
670 struct blorp_surf
*surf
, uint32_t level
, uint32_t layer
,
671 enum isl_format format
,
672 enum blorp_fast_clear_op resolve_op
)
674 struct blorp_params params
;
675 blorp_params_init(¶ms
);
677 /* Layered and mipmapped fast clear is only available from Gen8 onwards. */
678 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8 ||
679 (level
== 0 && layer
== 0));
681 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
,
682 level
, layer
, format
, true);
684 /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
686 * A rectangle primitive must be scaled down by the following factors
687 * with respect to render target being resolved.
689 * The scaledown factors in the table that follows are related to the block
690 * size of the CCS format. For IVB and HSW, we divide by two, for BDW we
691 * multiply by 8 and 16. On Sky Lake, we multiply by 8.
693 const struct isl_format_layout
*aux_fmtl
=
694 isl_format_get_layout(params
.dst
.aux_surf
.format
);
695 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
697 unsigned x_scaledown
, y_scaledown
;
698 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 9) {
699 x_scaledown
= aux_fmtl
->bw
* 8;
700 y_scaledown
= aux_fmtl
->bh
* 8;
701 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
702 x_scaledown
= aux_fmtl
->bw
* 8;
703 y_scaledown
= aux_fmtl
->bh
* 16;
705 x_scaledown
= aux_fmtl
->bw
/ 2;
706 y_scaledown
= aux_fmtl
->bh
/ 2;
708 params
.x0
= params
.y0
= 0;
709 params
.x1
= minify(params
.dst
.aux_surf
.logical_level0_px
.width
, level
);
710 params
.y1
= minify(params
.dst
.aux_surf
.logical_level0_px
.height
, level
);
711 params
.x1
= ALIGN(params
.x1
, x_scaledown
) / x_scaledown
;
712 params
.y1
= ALIGN(params
.y1
, y_scaledown
) / y_scaledown
;
714 if (batch
->blorp
->isl_dev
->info
->gen
>= 9) {
715 assert(resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_FULL
||
716 resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
);
718 /* Broadwell and earlier do not have a partial resolve */
719 assert(resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_FULL
);
721 params
.fast_clear_op
= resolve_op
;
723 /* Note: there is no need to initialize push constants because it doesn't
724 * matter what data gets dispatched to the render target. However, we must
725 * ensure that the fragment shader delivers the data using the "replicated
729 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, true))
732 batch
->blorp
->exec(batch
, ¶ms
);