2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "dev/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
34 * This file provides the blorp pipeline setup and execution functionality.
35 * It defines the following function:
38 * blorp_exec(struct blorp_context *blorp, void *batch_data,
39 * const struct blorp_params *params);
41 * It is the job of whoever includes this header to wrap this in something
42 * to get an externally visible symbol.
44 * In order for the blorp_exec function to work, the driver must provide
45 * implementations of the following static helper functions.
49 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
52 blorp_emit_reloc(struct blorp_batch
*batch
,
53 void *location
, struct blorp_address address
, uint32_t delta
);
56 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
61 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
62 struct blorp_address
*addr
);
64 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch
*batch
,
65 const struct blorp_address
*addrs
,
69 UNUSED
static struct blorp_address
70 blorp_get_workaround_page(struct blorp_batch
*batch
);
73 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
74 unsigned state_size
, unsigned state_alignment
,
75 uint32_t *bt_offset
, uint32_t *surface_offsets
,
79 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
82 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
83 struct blorp_address address
, uint32_t delta
);
86 blorp_get_surface_address(struct blorp_batch
*batch
,
87 struct blorp_address address
);
89 #if GEN_GEN >= 7 && GEN_GEN < 10
90 static struct blorp_address
91 blorp_get_surface_base_address(struct blorp_batch
*batch
);
95 static const struct gen_l3_config
*
96 blorp_get_l3_config(struct blorp_batch
*batch
);
99 blorp_emit_urb_config(struct blorp_batch
*batch
,
100 unsigned vs_entry_size
, unsigned sf_entry_size
);
104 blorp_emit_pipeline(struct blorp_batch
*batch
,
105 const struct blorp_params
*params
);
107 /***** BEGIN blorp_exec implementation ******/
110 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
111 struct blorp_address address
, uint32_t delta
)
113 if (address
.buffer
== NULL
) {
114 return address
.offset
+ delta
;
116 return blorp_emit_reloc(batch
, location
, address
, delta
);
120 #define __gen_address_type struct blorp_address
121 #define __gen_user_data struct blorp_batch
122 #define __gen_combine_address _blorp_combine_address
124 #include "genxml/genX_pack.h"
126 #define _blorp_cmd_length(cmd) cmd ## _length
127 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
128 #define _blorp_cmd_header(cmd) cmd ## _header
129 #define _blorp_cmd_pack(cmd) cmd ## _pack
131 #define blorp_emit(batch, cmd, name) \
132 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
133 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
134 __builtin_expect(_dst != NULL, 1); \
135 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
138 #define blorp_emitn(batch, cmd, n, ...) ({ \
139 uint32_t *_dw = blorp_emit_dwords(batch, n); \
141 struct cmd template = { \
142 _blorp_cmd_header(cmd), \
143 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
146 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
148 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
151 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
153 #define blorp_emit_dynamic(batch, state, name, align, offset) \
154 for (struct state name = STRUCT_ZERO(state), \
155 *_dst = blorp_alloc_dynamic_state(batch, \
156 _blorp_cmd_length(state) * 4, \
158 __builtin_expect(_dst != NULL, 1); \
159 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
160 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
169 * Assign the entire URB to the VS. Even though the VS disabled, URB space
170 * is still needed because the clipper loads the VUE's from the URB. From
171 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
172 * Dword 1.15:0 "VS Number of URB Entries":
173 * This field is always used (even if VS Function Enable is DISABLED).
175 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
176 * safely ignore it because this batch contains only one draw call.
177 * Because of URB corruption caused by allocating a previous GS unit
178 * URB entry to the VS unit, software is required to send a “GS NULL
179 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
180 * plus a dummy DRAW call before any case where VS will be taking over
183 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
184 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
186 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
187 * programmed in order for the programming of this state to be
191 emit_urb_config(struct blorp_batch
*batch
,
192 const struct blorp_params
*params
,
193 enum gen_urb_deref_block_size
*deref_block_size
)
195 /* Once vertex fetcher has written full VUE entries with complete
196 * header the space requirement is as follows per vertex (in bytes):
198 * Header Position Program constants
199 * +--------+------------+-------------------+
200 * | 16 | 16 | n x 16 |
201 * +--------+------------+-------------------+
203 * where 'n' stands for number of varying inputs expressed as vec4s.
205 const unsigned num_varyings
=
206 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
207 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
209 /* The URB size is expressed in units of 64 bytes (512 bits) */
210 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
212 const unsigned sf_entry_size
=
213 params
->sf_prog_data
? params
->sf_prog_data
->urb_entry_size
: 0;
216 assert(sf_entry_size
== 0);
217 const unsigned entry_size
[4] = { vs_entry_size
, 1, 1, 1 };
219 unsigned entries
[4], start
[4];
220 gen_get_urb_config(batch
->blorp
->compiler
->devinfo
,
221 blorp_get_l3_config(batch
),
222 false, false, entry_size
,
223 entries
, start
, deref_block_size
);
225 #if GEN_GEN == 7 && !GEN_IS_HASWELL
226 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
228 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
229 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
230 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
231 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
232 * needs to be sent before any combination of VS associated 3DSTATE."
234 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
235 pc
.DepthStallEnable
= true;
236 pc
.PostSyncOperation
= WriteImmediateData
;
237 pc
.Address
= blorp_get_workaround_page(batch
);
241 for (int i
= 0; i
<= MESA_SHADER_GEOMETRY
; i
++) {
242 blorp_emit(batch
, GENX(3DSTATE_URB_VS
), urb
) {
243 urb
._3DCommandSubOpcode
+= i
;
244 urb
.VSURBStartingAddress
= start
[i
];
245 urb
.VSURBEntryAllocationSize
= entry_size
[i
] - 1;
246 urb
.VSNumberofURBEntries
= entries
[i
];
249 #else /* GEN_GEN < 7 */
250 blorp_emit_urb_config(batch
, vs_entry_size
, sf_entry_size
);
256 blorp_emit_memcpy(struct blorp_batch
*batch
,
257 struct blorp_address dst
,
258 struct blorp_address src
,
263 blorp_emit_vertex_data(struct blorp_batch
*batch
,
264 const struct blorp_params
*params
,
265 struct blorp_address
*addr
,
268 const float vertices
[] = {
269 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
270 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
271 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
274 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
275 memcpy(data
, vertices
, sizeof(vertices
));
276 *size
= sizeof(vertices
);
277 blorp_flush_range(batch
, data
, *size
);
281 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
282 const struct blorp_params
*params
,
283 struct blorp_address
*addr
,
286 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
287 const unsigned max_num_varyings
=
288 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
289 const unsigned num_varyings
=
290 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
292 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
294 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
295 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
296 uint32_t *inputs
= data
;
298 /* Copy in the VS inputs */
299 assert(sizeof(params
->vs_inputs
) == 16);
300 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
303 if (params
->wm_prog_data
) {
304 /* Walk over the attribute slots, determine if the attribute is used by
305 * the program and when necessary copy the values from the input storage
306 * to the vertex data buffer.
308 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
309 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
311 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
315 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
321 blorp_flush_range(batch
, data
, *size
);
323 if (params
->dst_clear_color_as_input
) {
325 /* In this case, the clear color isn't known statically and instead
326 * comes in through an indirect which we have to copy into the vertex
327 * buffer before we execute the 3DPRIMITIVE. We already copied the
328 * value of params->wm_inputs.clear_color into the vertex buffer in the
329 * loop above. Now we emit code to stomp it from the GPU with the
330 * actual clear color value.
332 assert(num_varyings
== 1);
334 /* The clear color is the first thing after the header */
335 struct blorp_address clear_color_input_addr
= *addr
;
336 clear_color_input_addr
.offset
+= 16;
338 const unsigned clear_color_size
=
339 GEN_GEN
< 10 ? batch
->blorp
->isl_dev
->ss
.clear_value_size
: 4 * 4;
340 blorp_emit_memcpy(batch
, clear_color_input_addr
,
341 params
->dst
.clear_color_addr
,
344 unreachable("MCS partial resolve is not a thing on SNB and earlier");
350 blorp_fill_vertex_buffer_state(struct blorp_batch
*batch
,
351 struct GENX(VERTEX_BUFFER_STATE
) *vb
,
353 struct blorp_address addr
, uint32_t size
,
356 vb
[idx
].VertexBufferIndex
= idx
;
357 vb
[idx
].BufferStartingAddress
= addr
;
358 vb
[idx
].BufferPitch
= stride
;
361 vb
[idx
].MOCS
= addr
.mocs
;
365 vb
[idx
].AddressModifyEnable
= true;
369 vb
[idx
].BufferSize
= size
;
371 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
372 vb
[idx
].EndAddress
= vb
[idx
].BufferStartingAddress
;
373 vb
[idx
].EndAddress
.offset
+= size
- 1;
375 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
376 vb
[idx
].MaxIndex
= stride
> 0 ? size
/ stride
: 0;
381 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
382 const struct blorp_params
*params
)
384 struct GENX(VERTEX_BUFFER_STATE
) vb
[3];
385 uint32_t num_vbs
= 2;
386 memset(vb
, 0, sizeof(vb
));
388 struct blorp_address addrs
[2] = {};
390 blorp_emit_vertex_data(batch
, params
, &addrs
[0], &sizes
[0]);
391 blorp_fill_vertex_buffer_state(batch
, vb
, 0, addrs
[0], sizes
[0],
394 blorp_emit_input_varying_data(batch
, params
, &addrs
[1], &sizes
[1]);
395 blorp_fill_vertex_buffer_state(batch
, vb
, 1, addrs
[1], sizes
[1], 0);
397 blorp_vf_invalidate_for_vb_48b_transitions(batch
, addrs
, sizes
, num_vbs
);
399 const unsigned num_dwords
= 1 + num_vbs
* GENX(VERTEX_BUFFER_STATE_length
);
400 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
404 for (unsigned i
= 0; i
< num_vbs
; i
++) {
405 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
406 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
411 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
412 const struct blorp_params
*params
)
414 const unsigned num_varyings
=
415 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
416 bool need_ndc
= batch
->blorp
->compiler
->devinfo
->gen
<= 5;
417 const unsigned num_elements
= 2 + need_ndc
+ num_varyings
;
419 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
420 memset(ve
, 0, num_elements
* sizeof(*ve
));
422 /* Setup VBO for the rectangle primitive..
424 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
425 * vertices. The vertices reside in screen space with DirectX
426 * coordinates (that is, (0, 0) is the upper left corner).
433 * Since the VS is disabled, the clipper loads each VUE directly from
434 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
435 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
436 * dw0: Reserved, MBZ.
437 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
438 * to assign this with primitive instance identifier which will be
439 * used for layered clears. All other renders have only one instance
440 * and therefore the value will be effectively zero.
441 * dw2: Viewport Index. The HiZ op disables viewport mapping and
442 * scissoring, so set the dword to 0.
443 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
444 * so set the dword to 0.
445 * dw4: Vertex Position X.
446 * dw5: Vertex Position Y.
447 * dw6: Vertex Position Z.
448 * dw7: Vertex Position W.
450 * dw8: Flat vertex input 0
451 * dw9: Flat vertex input 1
453 * dwn: Flat vertex input n - 8
455 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
456 * "Vertex URB Entry (VUE) Formats".
458 * Only vertex position X and Y are going to be variable, Z is fixed to
459 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
460 * include the fixed values in the vertex buffer. Vertex fetcher can be
461 * instructed to fill vertex elements with constant values of one and zero
462 * instead of reading them from the buffer.
463 * Flat inputs are program constants that are not interpolated. Moreover
464 * their values will be the same between vertices.
466 * See the vertex element setup below.
470 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
471 .VertexBufferIndex
= 1,
473 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
474 .SourceElementOffset
= 0,
475 .Component0Control
= VFCOMP_STORE_SRC
,
477 /* From Gen8 onwards hardware is no more instructed to overwrite
478 * components using an element specifier. Instead one has separate
479 * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it.
482 .Component1Control
= VFCOMP_STORE_0
,
484 .Component1Control
= VFCOMP_STORE_IID
,
486 .Component1Control
= VFCOMP_STORE_0
,
488 .Component2Control
= VFCOMP_STORE_0
,
489 .Component3Control
= VFCOMP_STORE_0
,
491 .DestinationElementOffset
= slot
* 4,
497 /* On Iron Lake and earlier, a native device coordinates version of the
498 * position goes right after the normal VUE header and before position.
499 * Since w == 1 for all of our coordinates, this is just a copy of the
502 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
503 .VertexBufferIndex
= 0,
505 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
506 .SourceElementOffset
= 0,
507 .Component0Control
= VFCOMP_STORE_SRC
,
508 .Component1Control
= VFCOMP_STORE_SRC
,
509 .Component2Control
= VFCOMP_STORE_SRC
,
510 .Component3Control
= VFCOMP_STORE_1_FP
,
511 .DestinationElementOffset
= slot
* 4,
516 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
517 .VertexBufferIndex
= 0,
519 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
520 .SourceElementOffset
= 0,
521 .Component0Control
= VFCOMP_STORE_SRC
,
522 .Component1Control
= VFCOMP_STORE_SRC
,
523 .Component2Control
= VFCOMP_STORE_SRC
,
524 .Component3Control
= VFCOMP_STORE_1_FP
,
526 .DestinationElementOffset
= slot
* 4,
531 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
532 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
533 .VertexBufferIndex
= 1,
535 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
536 .SourceElementOffset
= 16 + i
* 4 * sizeof(float),
537 .Component0Control
= VFCOMP_STORE_SRC
,
538 .Component1Control
= VFCOMP_STORE_SRC
,
539 .Component2Control
= VFCOMP_STORE_SRC
,
540 .Component3Control
= VFCOMP_STORE_SRC
,
542 .DestinationElementOffset
= slot
* 4,
548 const unsigned num_dwords
=
549 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
550 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
554 for (unsigned i
= 0; i
< num_elements
; i
++) {
555 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
556 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
559 blorp_emit(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
560 vf
.StatisticsEnable
= false;
564 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
565 * primitive instance identifier. This is used for layered clears.
567 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
568 sgvs
.InstanceIDEnable
= true;
569 sgvs
.InstanceIDComponentNumber
= COMP_1
;
570 sgvs
.InstanceIDElementOffset
= 0;
573 for (unsigned i
= 0; i
< num_elements
; i
++) {
574 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
575 vf
.VertexElementIndex
= i
;
576 vf
.InstancingEnable
= false;
580 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
581 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
586 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
588 blorp_emit_cc_viewport(struct blorp_batch
*batch
)
590 uint32_t cc_vp_offset
;
591 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
592 vp
.MinimumDepth
= 0.0;
593 vp
.MaximumDepth
= 1.0;
597 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
598 vsp
.CCViewportPointer
= cc_vp_offset
;
601 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
602 vsp
.CCViewportStateChange
= true;
603 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
611 blorp_emit_sampler_state(struct blorp_batch
*batch
)
614 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
615 sampler
.MipModeFilter
= MIPFILTER_NONE
;
616 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
617 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
620 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
621 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
622 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
623 sampler
.MaximumAnisotropy
= RATIO21
;
624 sampler
.RAddressMinFilterRoundingEnable
= true;
625 sampler
.RAddressMagFilterRoundingEnable
= true;
626 sampler
.VAddressMinFilterRoundingEnable
= true;
627 sampler
.VAddressMagFilterRoundingEnable
= true;
628 sampler
.UAddressMinFilterRoundingEnable
= true;
629 sampler
.UAddressMagFilterRoundingEnable
= true;
631 sampler
.NonnormalizedCoordinateEnable
= true;
636 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
637 ssp
.PointertoPSSamplerState
= offset
;
640 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
641 ssp
.VSSamplerStateChange
= true;
642 ssp
.GSSamplerStateChange
= true;
643 ssp
.PSSamplerStateChange
= true;
644 ssp
.PointertoPSSamplerState
= offset
;
651 /* What follows is the code for setting up a "pipeline" on Sandy Bridge and
652 * later hardware. This file will be included by i965 for gen4-5 as well, so
653 * this code is guarded by GEN_GEN >= 6.
658 blorp_emit_vs_config(struct blorp_batch
*batch
,
659 const struct blorp_params
*params
)
661 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
662 assert(!vs_prog_data
|| GEN_GEN
< 11 ||
663 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
665 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
669 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
671 vs
.DispatchGRFStartRegisterForURBData
=
672 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
673 vs
.VertexURBEntryReadLength
=
674 vs_prog_data
->base
.urb_read_length
;
675 vs
.VertexURBEntryReadOffset
= 0;
677 vs
.MaximumNumberofThreads
=
678 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
681 vs
.SIMD8DispatchEnable
=
682 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
689 blorp_emit_sf_config(struct blorp_batch
*batch
,
690 const struct blorp_params
*params
,
691 enum gen_urb_deref_block_size urb_deref_block_size
)
693 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
697 * Disable ViewportTransformEnable (dw2.1)
699 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
700 * Primitives Overview":
701 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
702 * use of screen- space coordinates).
704 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
705 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
707 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
708 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
709 * SOLID: Any triangle or rectangle object found to be front-facing
710 * is rendered as a solid object. This setting is required when
711 * (rendering rectangle (RECTLIST) objects.
716 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
718 sf
.DerefBlockSize
= urb_deref_block_size
;
722 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
723 raster
.CullMode
= CULLMODE_NONE
;
726 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
727 sbe
.VertexURBEntryReadOffset
= 1;
729 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
730 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
731 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
733 sbe
.NumberofSFOutputAttributes
= 0;
734 sbe
.VertexURBEntryReadLength
= 1;
736 sbe
.ForceVertexURBEntryReadLength
= true;
737 sbe
.ForceVertexURBEntryReadOffset
= true;
740 for (unsigned i
= 0; i
< 32; i
++)
741 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
747 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
748 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
749 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
751 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
752 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
755 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
759 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
760 sbe
.VertexURBEntryReadOffset
= 1;
762 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
763 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
764 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
766 sbe
.NumberofSFOutputAttributes
= 0;
767 sbe
.VertexURBEntryReadLength
= 1;
771 #else /* GEN_GEN <= 6 */
773 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
774 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
775 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
777 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
778 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
780 sf
.VertexURBEntryReadOffset
= 1;
782 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
783 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
784 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
786 sf
.NumberofSFOutputAttributes
= 0;
787 sf
.VertexURBEntryReadLength
= 1;
795 blorp_emit_ps_config(struct blorp_batch
*batch
,
796 const struct blorp_params
*params
)
798 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
800 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
801 * nonzero to prevent the GPU from hanging. While the documentation doesn't
802 * mention this explicitly, it notes that the valid range for the field is
803 * [1,39] = [2,40] threads, which excludes zero.
805 * To be safe (and to minimize extraneous code) we go ahead and fully
806 * configure the WM state whether or not there is a WM program.
811 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
813 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
814 if (params
->src
.enabled
) {
815 ps
.SamplerCount
= 1; /* Up to 4 samplers */
816 ps
.BindingTableEntryCount
= 2;
818 ps
.BindingTableEntryCount
= 1;
821 /* SAMPLER_STATE prefetching is broken on Gen11 - WA_1606682166 */
826 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
827 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
828 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
830 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
832 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
833 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
835 * Since 16x MSAA is first introduced on SKL, we don't need to apply
836 * the workaround on any older hardware.
838 if (GEN_GEN
>= 9 && !prog_data
->persample_dispatch
&&
839 params
->num_samples
== 16) {
840 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
841 ps
._32PixelDispatchEnable
= false;
844 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
845 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
846 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
847 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
848 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
849 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
851 ps
.KernelStartPointer0
= params
->wm_prog_kernel
+
852 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
853 ps
.KernelStartPointer1
= params
->wm_prog_kernel
+
854 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
855 ps
.KernelStartPointer2
= params
->wm_prog_kernel
+
856 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
859 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
860 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
861 * k, it implies 2(k+1) threads. It implicitly scales for different GT
862 * levels (which have some # of PSDs).
864 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
867 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
869 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
871 switch (params
->fast_clear_op
) {
872 case ISL_AUX_OP_NONE
:
875 case ISL_AUX_OP_AMBIGUATE
:
876 ps
.RenderTargetFastClearEnable
= true;
877 ps
.RenderTargetResolveType
= FAST_CLEAR_0
;
881 case ISL_AUX_OP_PARTIAL_RESOLVE
:
882 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
884 case ISL_AUX_OP_FULL_RESOLVE
:
885 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
888 case ISL_AUX_OP_FULL_RESOLVE
:
889 ps
.RenderTargetResolveEnable
= true;
892 case ISL_AUX_OP_FAST_CLEAR
:
893 ps
.RenderTargetFastClearEnable
= true;
896 unreachable("Invalid fast clear op");
900 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
902 psx
.PixelShaderValid
= true;
903 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
904 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
907 if (params
->src
.enabled
)
908 psx
.PixelShaderKillsPixel
= true;
913 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
914 switch (params
->hiz_op
) {
915 case ISL_AUX_OP_FAST_CLEAR
:
916 wm
.DepthBufferClear
= true;
918 case ISL_AUX_OP_FULL_RESOLVE
:
919 wm
.DepthBufferResolveEnable
= true;
921 case ISL_AUX_OP_AMBIGUATE
:
922 wm
.HierarchicalDepthBufferResolveEnable
= true;
924 case ISL_AUX_OP_NONE
:
927 unreachable("not reached");
931 wm
.ThreadDispatchEnable
= true;
933 if (params
->src
.enabled
)
934 wm
.PixelShaderKillsPixel
= true;
936 if (params
->num_samples
> 1) {
937 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
938 wm
.MultisampleDispatchMode
=
939 (prog_data
&& prog_data
->persample_dispatch
) ?
940 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
942 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
943 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
947 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
948 ps
.MaximumNumberofThreads
=
949 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
956 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
957 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
958 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
960 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
961 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
962 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
963 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
964 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
965 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
967 ps
.KernelStartPointer0
= params
->wm_prog_kernel
+
968 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
969 ps
.KernelStartPointer1
= params
->wm_prog_kernel
+
970 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
971 ps
.KernelStartPointer2
= params
->wm_prog_kernel
+
972 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
974 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
976 /* Gen7 hardware gets angry if we don't enable at least one dispatch
977 * mode, so just enable 16-pixel dispatch if we don't have a program.
979 ps
._16PixelDispatchEnable
= true;
982 if (params
->src
.enabled
)
983 ps
.SamplerCount
= 1; /* Up to 4 samplers */
985 switch (params
->fast_clear_op
) {
986 case ISL_AUX_OP_NONE
:
988 case ISL_AUX_OP_FULL_RESOLVE
:
989 ps
.RenderTargetResolveEnable
= true;
991 case ISL_AUX_OP_FAST_CLEAR
:
992 ps
.RenderTargetFastClearEnable
= true;
995 unreachable("Invalid fast clear op");
999 #else /* GEN_GEN <= 6 */
1001 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
1002 wm
.MaximumNumberofThreads
=
1003 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
1005 switch (params
->hiz_op
) {
1006 case ISL_AUX_OP_FAST_CLEAR
:
1007 wm
.DepthBufferClear
= true;
1009 case ISL_AUX_OP_FULL_RESOLVE
:
1010 wm
.DepthBufferResolveEnable
= true;
1012 case ISL_AUX_OP_AMBIGUATE
:
1013 wm
.HierarchicalDepthBufferResolveEnable
= true;
1015 case ISL_AUX_OP_NONE
:
1018 unreachable("not reached");
1022 wm
.ThreadDispatchEnable
= true;
1024 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
1025 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
1026 wm
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
1028 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1029 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 0);
1030 wm
.DispatchGRFStartRegisterForConstantSetupData1
=
1031 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 1);
1032 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1033 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 2);
1035 wm
.KernelStartPointer0
= params
->wm_prog_kernel
+
1036 brw_wm_prog_data_prog_offset(prog_data
, wm
, 0);
1037 wm
.KernelStartPointer1
= params
->wm_prog_kernel
+
1038 brw_wm_prog_data_prog_offset(prog_data
, wm
, 1);
1039 wm
.KernelStartPointer2
= params
->wm_prog_kernel
+
1040 brw_wm_prog_data_prog_offset(prog_data
, wm
, 2);
1042 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
1045 if (params
->src
.enabled
) {
1046 wm
.SamplerCount
= 1; /* Up to 4 samplers */
1047 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
1050 if (params
->num_samples
> 1) {
1051 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1052 wm
.MultisampleDispatchMode
=
1053 (prog_data
&& prog_data
->persample_dispatch
) ?
1054 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
1056 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1057 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1061 #endif /* GEN_GEN */
1065 blorp_emit_blend_state(struct blorp_batch
*batch
,
1066 const struct blorp_params
*params
)
1068 struct GENX(BLEND_STATE
) blend
;
1069 memset(&blend
, 0, sizeof(blend
));
1072 int size
= GENX(BLEND_STATE_length
) * 4;
1073 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
1074 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
1075 uint32_t *pos
= state
;
1077 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
1078 pos
+= GENX(BLEND_STATE_length
);
1080 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
1081 struct GENX(BLEND_STATE_ENTRY
) entry
= {
1082 .PreBlendColorClampEnable
= true,
1083 .PostBlendColorClampEnable
= true,
1084 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
1086 .WriteDisableRed
= params
->color_write_disable
[0],
1087 .WriteDisableGreen
= params
->color_write_disable
[1],
1088 .WriteDisableBlue
= params
->color_write_disable
[2],
1089 .WriteDisableAlpha
= params
->color_write_disable
[3],
1091 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
1092 pos
+= GENX(BLEND_STATE_ENTRY_length
);
1095 blorp_flush_range(batch
, state
, size
);
1098 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
1099 sp
.BlendStatePointer
= offset
;
1101 sp
.BlendStatePointerValid
= true;
1107 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
1108 ps_blend
.HasWriteableRT
= true;
1116 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
1117 UNUSED
const struct blorp_params
*params
)
1120 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
1122 cc
.StencilReferenceValue
= params
->stencil_ref
;
1127 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
1128 sp
.ColorCalcStatePointer
= offset
;
1130 sp
.ColorCalcStatePointerValid
= true;
1139 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
1140 const struct blorp_params
*params
)
1143 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
1144 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
1147 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
1150 if (params
->depth
.enabled
) {
1151 ds
.DepthBufferWriteEnable
= true;
1153 switch (params
->hiz_op
) {
1154 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
1155 * - 7.5.3.1 Depth Buffer Clear
1156 * - 7.5.3.2 Depth Buffer Resolve
1157 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1159 case ISL_AUX_OP_FULL_RESOLVE
:
1160 ds
.DepthTestEnable
= true;
1161 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
1164 case ISL_AUX_OP_NONE
:
1165 case ISL_AUX_OP_FAST_CLEAR
:
1166 case ISL_AUX_OP_AMBIGUATE
:
1167 ds
.DepthTestEnable
= false;
1169 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1170 unreachable("Invalid HIZ op");
1174 if (params
->stencil
.enabled
) {
1175 ds
.StencilBufferWriteEnable
= true;
1176 ds
.StencilTestEnable
= true;
1177 ds
.DoubleSidedStencilEnable
= false;
1179 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1180 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1182 ds
.StencilWriteMask
= params
->stencil_mask
;
1184 ds
.StencilReferenceValue
= params
->stencil_ref
;
1189 uint32_t offset
= 0;
1190 uint32_t *dw
= blorp_emit_dwords(batch
,
1191 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1195 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1198 void *state
= blorp_alloc_dynamic_state(batch
,
1199 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1201 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1202 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1206 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1207 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1215 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1216 const struct blorp_params
*params
)
1218 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1219 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1222 /* The PRM says that this bit is valid only for DX9:
1224 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1225 * should not have any effect by setting or not setting this bit.
1227 ms
.PixelPositionOffsetEnable
= false;
1230 switch (params
->num_samples
) {
1232 GEN_SAMPLE_POS_1X(ms
.Sample
);
1235 GEN_SAMPLE_POS_2X(ms
.Sample
);
1238 GEN_SAMPLE_POS_4X(ms
.Sample
);
1241 GEN_SAMPLE_POS_8X(ms
.Sample
);
1247 GEN_SAMPLE_POS_4X(ms
.Sample
);
1249 ms
.PixelLocation
= CENTER
;
1254 blorp_emit_pipeline(struct blorp_batch
*batch
,
1255 const struct blorp_params
*params
)
1257 uint32_t blend_state_offset
= 0;
1258 uint32_t color_calc_state_offset
;
1259 uint32_t depth_stencil_state_offset
;
1261 enum gen_urb_deref_block_size urb_deref_block_size
;
1262 emit_urb_config(batch
, params
, &urb_deref_block_size
);
1264 if (params
->wm_prog_data
) {
1265 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1267 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1268 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1271 /* 3DSTATE_CC_STATE_POINTERS
1273 * The pointer offsets are relative to
1274 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1276 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1278 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1279 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1280 * one CC_STATE_POINTERS packet so we have to emit that here.
1282 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1283 cc
.BLEND_STATEChange
= true;
1284 cc
.ColorCalcStatePointerValid
= true;
1285 cc
.DEPTH_STENCIL_STATEChange
= true;
1286 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1287 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1288 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1291 (void)blend_state_offset
;
1292 (void)color_calc_state_offset
;
1293 (void)depth_stencil_state_offset
;
1297 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_ALL
), pc
) {
1298 /* Update empty push constants for all stages (bitmask = 11111b) */
1299 pc
.ShaderUpdateEnable
= 0x1f;
1302 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1304 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1305 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1307 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1308 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1311 if (params
->src
.enabled
)
1312 blorp_emit_sampler_state(batch
);
1314 blorp_emit_3dstate_multisample(batch
, params
);
1316 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1317 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1320 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1321 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1323 * [DevSNB] A pipeline flush must be programmed prior to a
1324 * 3DSTATE_VS command that causes the VS Function Enable to
1325 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1326 * command with CS stall bit set and a post sync operation.
1328 * We've already done one at the start of the BLORP operation.
1330 blorp_emit_vs_config(batch
, params
);
1332 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1333 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1334 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1335 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1337 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1339 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1340 clip
.PerspectiveDivideDisable
= true;
1343 blorp_emit_sf_config(batch
, params
, urb_deref_block_size
);
1344 blorp_emit_ps_config(batch
, params
);
1346 blorp_emit_cc_viewport(batch
);
1349 /******** This is the end of the pipeline setup code ********/
1351 #endif /* GEN_GEN >= 6 */
1355 blorp_emit_memcpy(struct blorp_batch
*batch
,
1356 struct blorp_address dst
,
1357 struct blorp_address src
,
1360 assert(size
% 4 == 0);
1362 for (unsigned dw
= 0; dw
< size
; dw
+= 4) {
1364 blorp_emit(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
1365 cp
.DestinationMemoryAddress
= dst
;
1366 cp
.SourceMemoryAddress
= src
;
1369 /* IVB does not have a general purpose register for command streamer
1370 * commands. Therefore, we use an alternate temporary register.
1372 #define BLORP_TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
1373 blorp_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), load
) {
1374 load
.RegisterAddress
= BLORP_TEMP_REG
;
1375 load
.MemoryAddress
= src
;
1377 blorp_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), store
) {
1378 store
.RegisterAddress
= BLORP_TEMP_REG
;
1379 store
.MemoryAddress
= dst
;
1381 #undef BLORP_TEMP_REG
1390 blorp_emit_surface_state(struct blorp_batch
*batch
,
1391 const struct brw_blorp_surface_info
*surface
,
1392 enum isl_aux_op aux_op
,
1393 void *state
, uint32_t state_offset
,
1394 const bool color_write_disables
[4],
1395 bool is_render_target
)
1397 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1398 struct isl_surf surf
= surface
->surf
;
1400 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1401 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1402 assert(surf
.logical_level0_px
.height
== 1);
1403 surf
.dim
= ISL_SURF_DIM_2D
;
1406 if (isl_aux_usage_has_hiz(surface
->aux_usage
)) {
1407 /* BLORP doesn't render with depth so we can't use HiZ */
1408 assert(!is_render_target
);
1409 /* We can't reinterpret HiZ */
1410 assert(surface
->surf
.format
== surface
->view
.format
);
1412 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1414 isl_channel_mask_t write_disable_mask
= 0;
1415 if (is_render_target
&& GEN_GEN
<= 5) {
1416 if (color_write_disables
[0])
1417 write_disable_mask
|= ISL_CHANNEL_RED_BIT
;
1418 if (color_write_disables
[1])
1419 write_disable_mask
|= ISL_CHANNEL_GREEN_BIT
;
1420 if (color_write_disables
[2])
1421 write_disable_mask
|= ISL_CHANNEL_BLUE_BIT
;
1422 if (color_write_disables
[3])
1423 write_disable_mask
|= ISL_CHANNEL_ALPHA_BIT
;
1426 const bool use_clear_address
=
1427 GEN_GEN
>= 10 && (surface
->clear_color_addr
.buffer
!= NULL
);
1429 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1430 .surf
= &surf
, .view
= &surface
->view
,
1431 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1433 blorp_get_surface_address(batch
, surface
->addr
),
1434 .aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
? 0 :
1435 blorp_get_surface_address(batch
, surface
->aux_addr
),
1436 .clear_address
= !use_clear_address
? 0 :
1437 blorp_get_surface_address(batch
,
1438 surface
->clear_color_addr
),
1439 .mocs
= surface
->addr
.mocs
,
1440 .clear_color
= surface
->clear_color
,
1441 .use_clear_address
= use_clear_address
,
1442 .write_disables
= write_disable_mask
);
1444 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1447 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1448 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1449 * used to store other information. This should be ok, however, because
1450 * surface buffer addresses are always 4K page alinged.
1452 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1453 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1454 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1455 surface
->aux_addr
, *aux_addr
);
1458 if (aux_usage
!= ISL_AUX_USAGE_NONE
&& surface
->clear_color_addr
.buffer
) {
1460 assert((surface
->clear_color_addr
.offset
& 0x3f) == 0);
1461 uint32_t *clear_addr
= state
+ isl_dev
->ss
.clear_color_state_offset
;
1462 blorp_surface_reloc(batch
, state_offset
+
1463 isl_dev
->ss
.clear_color_state_offset
,
1464 surface
->clear_color_addr
, *clear_addr
);
1466 /* Fast clears just whack the AUX surface and don't actually use the
1467 * clear color for anything. We can avoid the MI memcpy on that case.
1469 if (aux_op
!= ISL_AUX_OP_FAST_CLEAR
) {
1470 struct blorp_address dst_addr
= blorp_get_surface_base_address(batch
);
1471 dst_addr
.offset
+= state_offset
+ isl_dev
->ss
.clear_value_offset
;
1472 blorp_emit_memcpy(batch
, dst_addr
, surface
->clear_color_addr
,
1473 isl_dev
->ss
.clear_value_size
);
1476 unreachable("Fast clears are only supported on gen7+");
1480 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1484 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1485 const struct brw_blorp_surface_info
*surface
,
1488 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1489 .SurfaceType
= SURFTYPE_NULL
,
1490 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1491 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1492 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1493 .MIPCountLOD
= surface
->view
.base_level
,
1494 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1495 .Depth
= surface
->view
.array_len
- 1,
1496 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1498 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1502 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1508 .TiledSurface
= true,
1512 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1514 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1518 blorp_emit_surface_states(struct blorp_batch
*batch
,
1519 const struct blorp_params
*params
)
1521 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1522 uint32_t bind_offset
= 0, surface_offsets
[2];
1523 void *surface_maps
[2];
1525 UNUSED
bool has_indirect_clear_color
= false;
1526 if (params
->use_pre_baked_binding_table
) {
1527 bind_offset
= params
->pre_baked_binding_table_offset
;
1529 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1530 blorp_alloc_binding_table(batch
, num_surfaces
,
1531 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1532 &bind_offset
, surface_offsets
, surface_maps
);
1534 if (params
->dst
.enabled
) {
1535 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1536 params
->fast_clear_op
,
1537 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1538 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1539 params
->color_write_disable
, true);
1540 if (params
->dst
.clear_color_addr
.buffer
!= NULL
)
1541 has_indirect_clear_color
= true;
1543 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1544 const struct brw_blorp_surface_info
*surface
=
1545 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1546 blorp_emit_null_surface_state(batch
, surface
,
1547 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1550 if (params
->src
.enabled
) {
1551 blorp_emit_surface_state(batch
, ¶ms
->src
,
1552 params
->fast_clear_op
,
1553 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1554 surface_offsets
[BLORP_TEXTURE_BT_INDEX
],
1556 if (params
->src
.clear_color_addr
.buffer
!= NULL
)
1557 has_indirect_clear_color
= true;
1562 if (has_indirect_clear_color
) {
1563 /* Updating a surface state object may require that the state cache be
1564 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1567 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1568 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1569 * modified [...], the L1 state cache must be invalidated to ensure
1570 * the new surface or sampler state is fetched from system memory.
1572 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1573 pipe
.StateCacheInvalidationEnable
= true;
1575 pipe
.TileCacheFlushEnable
= true;
1582 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1583 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1584 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1585 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1587 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1588 bt
.PointertoPSBindingTable
= bind_offset
;
1591 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1592 bt
.PSBindingTableChange
= true;
1593 bt
.PointertoPSBindingTable
= bind_offset
;
1596 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1597 bt
.PointertoPSBindingTable
= bind_offset
;
1603 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
1604 const struct blorp_params
*params
)
1606 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1608 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
1612 struct isl_depth_stencil_hiz_emit_info info
= { };
1614 if (params
->depth
.enabled
) {
1615 info
.view
= ¶ms
->depth
.view
;
1616 info
.mocs
= params
->depth
.addr
.mocs
;
1617 } else if (params
->stencil
.enabled
) {
1618 info
.view
= ¶ms
->stencil
.view
;
1619 info
.mocs
= params
->stencil
.addr
.mocs
;
1622 if (params
->depth
.enabled
) {
1623 info
.depth_surf
= ¶ms
->depth
.surf
;
1625 info
.depth_address
=
1626 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
1627 params
->depth
.addr
, 0);
1629 info
.hiz_usage
= params
->depth
.aux_usage
;
1630 if (isl_aux_usage_has_hiz(info
.hiz_usage
)) {
1631 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
1633 struct blorp_address hiz_address
= params
->depth
.aux_addr
;
1635 /* Sandy bridge hardware does not technically support mipmapped HiZ.
1636 * However, we have a special layout that allows us to make it work
1637 * anyway by manually offsetting to the specified miplevel.
1639 assert(info
.hiz_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1641 isl_surf_get_image_offset_B_tile_sa(info
.hiz_surf
,
1642 info
.view
->base_level
, 0, 0,
1643 &offset_B
, NULL
, NULL
);
1644 hiz_address
.offset
+= offset_B
;
1648 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
1651 info
.depth_clear_value
= params
->depth
.clear_color
.f32
[0];
1655 if (params
->stencil
.enabled
) {
1656 info
.stencil_surf
= ¶ms
->stencil
.surf
;
1658 info
.stencil_aux_usage
= params
->stencil
.aux_usage
;
1659 struct blorp_address stencil_address
= params
->stencil
.addr
;
1661 /* Sandy bridge hardware does not technically support mipmapped stencil.
1662 * However, we have a special layout that allows us to make it work
1663 * anyway by manually offsetting to the specified miplevel.
1665 assert(info
.stencil_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1667 isl_surf_get_image_offset_B_tile_sa(info
.stencil_surf
,
1668 info
.view
->base_level
, 0, 0,
1669 &offset_B
, NULL
, NULL
);
1670 stencil_address
.offset
+= offset_B
;
1673 info
.stencil_address
=
1674 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
1675 stencil_address
, 0);
1678 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
1681 /* GEN:BUG:1408224581
1683 * Workaround: Gen12LP Astep only An additional pipe control with
1684 * post-sync = store dword operation would be required.( w/a is to
1685 * have an additional pipe control after the stencil state whenever
1686 * the surface state bits of this state is changing).
1688 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1689 pc
.PostSyncOperation
= WriteImmediateData
;
1690 pc
.Address
= blorp_get_workaround_page(batch
);
1696 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1697 * depth/stencil buffer extents are ignored to handle APIs which perform
1698 * clearing operations without such information.
1701 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1702 const struct blorp_params
*params
)
1704 /* We should be performing an operation on a depth or stencil buffer.
1706 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1708 /* The stencil buffer should only be enabled on GEN == 12, if a fast clear
1709 * or full resolve operation is requested. On rest of the GEN, if a fast
1710 * clear operation is requested.
1712 if (params
->stencil
.enabled
) {
1714 assert(params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
||
1715 params
->hiz_op
== ISL_AUX_OP_FULL_RESOLVE
);
1717 assert(params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
);
1721 /* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
1723 * 3DSTATE_MULTISAMPLE packet must be used prior to this packet to change
1724 * the Number of Multisamples. This packet must not be used to change
1725 * Number of Multisamples in a rendering sequence.
1727 * Since HIZ may be the first thing in a batch buffer, play safe and always
1728 * emit 3DSTATE_MULTISAMPLE.
1730 blorp_emit_3dstate_multisample(batch
, params
);
1732 /* From the BDW PRM Volume 7, Depth Buffer Clear:
1734 * The clear value must be between the min and max depth values
1735 * (inclusive) defined in the CC_VIEWPORT. If the depth buffer format is
1736 * D32_FLOAT, then +/-DENORM values are also allowed.
1738 * Set the bounds to match our hardware limits, [0.0, 1.0].
1740 if (params
->depth
.enabled
&& params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
) {
1741 assert(params
->depth
.clear_color
.f32
[0] >= 0.0f
);
1742 assert(params
->depth
.clear_color
.f32
[0] <= 1.0f
);
1743 blorp_emit_cc_viewport(batch
);
1746 /* According to the SKL PRM formula for WM_INT::ThreadDispatchEnable, the
1747 * 3DSTATE_WM::ForceThreadDispatchEnable field can force WM thread dispatch
1748 * even when WM_HZ_OP is active. However, WM thread dispatch is normally
1749 * disabled for HiZ ops and it appears that force-enabling it can lead to
1750 * GPU hangs on at least Skylake. Since we don't know the current state of
1751 * the 3DSTATE_WM packet, just emit a dummy one prior to 3DSTATE_WM_HZ_OP.
1753 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
1755 /* If we can't alter the depth stencil config and multiple layers are
1756 * involved, the HiZ op will fail. This is because the op requires that a
1757 * new config is emitted for each additional layer.
1759 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1760 assert(params
->num_layers
<= 1);
1762 blorp_emit_depth_stencil_config(batch
, params
);
1765 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1766 switch (params
->hiz_op
) {
1767 case ISL_AUX_OP_FAST_CLEAR
:
1768 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1769 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1770 hzp
.StencilClearValue
= params
->stencil_ref
;
1771 hzp
.FullSurfaceDepthandStencilClear
= params
->full_surface_hiz_op
;
1773 case ISL_AUX_OP_FULL_RESOLVE
:
1774 assert(params
->full_surface_hiz_op
);
1775 hzp
.DepthBufferResolveEnable
= params
->depth
.enabled
;
1777 if (params
->stencil
.enabled
) {
1778 assert(params
->stencil
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
1779 hzp
.StencilBufferResolveEnable
= true;
1783 case ISL_AUX_OP_AMBIGUATE
:
1784 assert(params
->full_surface_hiz_op
);
1785 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1787 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1788 case ISL_AUX_OP_NONE
:
1789 unreachable("Invalid HIZ op");
1792 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1793 hzp
.SampleMask
= 0xFFFF;
1795 /* Due to a hardware issue, this bit MBZ */
1796 assert(hzp
.ScissorRectangleEnable
== false);
1798 /* Contrary to the HW docs both fields are inclusive */
1799 hzp
.ClearRectangleXMin
= params
->x0
;
1800 hzp
.ClearRectangleYMin
= params
->y0
;
1802 /* Contrary to the HW docs both fields are exclusive */
1803 hzp
.ClearRectangleXMax
= params
->x1
;
1804 hzp
.ClearRectangleYMax
= params
->y1
;
1807 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1808 * to “Write Immediate Data” enabled.
1810 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1811 pc
.PostSyncOperation
= WriteImmediateData
;
1812 pc
.Address
= blorp_get_workaround_page(batch
);
1815 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1820 blorp_update_clear_color(struct blorp_batch
*batch
,
1821 const struct brw_blorp_surface_info
*info
,
1824 if (info
->clear_color_addr
.buffer
&& op
== ISL_AUX_OP_FAST_CLEAR
) {
1826 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1827 pipe
.CommandStreamerStallEnable
= true;
1831 const unsigned inlinedata_dw
= 2 * 2;
1832 const unsigned num_dwords
= GENX(MI_ATOMIC_length
) + inlinedata_dw
;
1834 struct blorp_address clear_addr
= info
->clear_color_addr
;
1835 uint32_t *dw
= blorp_emitn(batch
, GENX(MI_ATOMIC
), num_dwords
,
1836 .DataSize
= MI_ATOMIC_QWORD
,
1837 .ATOMICOPCODE
= MI_ATOMIC_OP_MOVE8B
,
1839 .MemoryAddress
= clear_addr
);
1840 /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
1841 dw
[2] = info
->clear_color
.u32
[0];
1843 dw
[4] = info
->clear_color
.u32
[1];
1846 clear_addr
.offset
+= 8;
1847 dw
= blorp_emitn(batch
, GENX(MI_ATOMIC
), num_dwords
,
1848 .DataSize
= MI_ATOMIC_QWORD
,
1849 .ATOMICOPCODE
= MI_ATOMIC_OP_MOVE8B
,
1851 .ReturnDataControl
= true,
1853 .MemoryAddress
= clear_addr
);
1854 /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
1855 dw
[2] = info
->clear_color
.u32
[2];
1857 dw
[4] = info
->clear_color
.u32
[3];
1860 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1861 pipe
.StateCacheInvalidationEnable
= true;
1862 pipe
.TextureCacheInvalidationEnable
= true;
1866 /* According to GEN:BUG:2201730850, in the Clear Color Programming Note
1867 * under the Red channel, "Software shall write the converted Depth
1868 * Clear to this dword." The only depth formats listed under the red
1869 * channel are IEEE_FP and UNORM24_X8. These two requirements are
1870 * incompatible with the UNORM16 depth format, so just ignore that case
1871 * and simply perform the conversion for all depth formats.
1873 union isl_color_value fixed_color
= info
->clear_color
;
1874 if (GEN_GEN
== 12 && isl_surf_usage_is_depth(info
->surf
.usage
)) {
1875 isl_color_value_pack(&info
->clear_color
, info
->surf
.format
,
1879 for (int i
= 0; i
< 4; i
++) {
1880 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1881 sdi
.Address
= info
->clear_color_addr
;
1882 sdi
.Address
.offset
+= i
* 4;
1883 sdi
.ImmediateData
= fixed_color
.u32
[i
];
1886 sdi
.ForceWriteCompletionCheck
= true;
1891 /* The RENDER_SURFACE_STATE::ClearColor field states that software should
1892 * write the converted depth value 16B after the clear address:
1894 * 3D Sampler will always fetch clear depth from the location 16-bytes
1895 * above this address, where the clear depth, converted to native
1896 * surface format by software, will be stored.
1900 if (isl_surf_usage_is_depth(info
->surf
.usage
)) {
1901 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1902 sdi
.Address
= info
->clear_color_addr
;
1903 sdi
.Address
.offset
+= 4 * 4;
1904 sdi
.ImmediateData
= fixed_color
.u32
[0];
1905 sdi
.ForceWriteCompletionCheck
= true;
1911 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1912 sdi
.Address
= info
->clear_color_addr
;
1913 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
1914 ISL_CHANNEL_SELECT_GREEN
<< 22 |
1915 ISL_CHANNEL_SELECT_BLUE
<< 19 |
1916 ISL_CHANNEL_SELECT_ALPHA
<< 16;
1917 if (isl_format_has_int_channel(info
->view
.format
)) {
1918 for (unsigned i
= 0; i
< 4; i
++) {
1919 assert(info
->clear_color
.u32
[i
] == 0 ||
1920 info
->clear_color
.u32
[i
] == 1);
1922 sdi
.ImmediateData
|= (info
->clear_color
.u32
[0] != 0) << 31;
1923 sdi
.ImmediateData
|= (info
->clear_color
.u32
[1] != 0) << 30;
1924 sdi
.ImmediateData
|= (info
->clear_color
.u32
[2] != 0) << 29;
1925 sdi
.ImmediateData
|= (info
->clear_color
.u32
[3] != 0) << 28;
1927 for (unsigned i
= 0; i
< 4; i
++) {
1928 assert(info
->clear_color
.f32
[i
] == 0.0f
||
1929 info
->clear_color
.f32
[i
] == 1.0f
);
1931 sdi
.ImmediateData
|= (info
->clear_color
.f32
[0] != 0.0f
) << 31;
1932 sdi
.ImmediateData
|= (info
->clear_color
.f32
[1] != 0.0f
) << 30;
1933 sdi
.ImmediateData
|= (info
->clear_color
.f32
[2] != 0.0f
) << 29;
1934 sdi
.ImmediateData
|= (info
->clear_color
.f32
[3] != 0.0f
) << 28;
1942 * \brief Execute a blit or render pass operation.
1944 * To execute the operation, this function manually constructs and emits a
1945 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1946 * constructing and after emitting the batch.
1948 * This function alters no GL state.
1951 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1953 if (!(batch
->flags
& BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
)) {
1954 blorp_update_clear_color(batch
, ¶ms
->dst
, params
->fast_clear_op
);
1955 blorp_update_clear_color(batch
, ¶ms
->depth
, params
->hiz_op
);
1959 if (params
->hiz_op
!= ISL_AUX_OP_NONE
) {
1960 blorp_emit_gen8_hiz_op(batch
, params
);
1965 blorp_emit_vertex_buffers(batch
, params
);
1966 blorp_emit_vertex_elements(batch
, params
);
1968 blorp_emit_pipeline(batch
, params
);
1970 blorp_emit_surface_states(batch
, params
);
1972 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1973 blorp_emit_depth_stencil_config(batch
, params
);
1975 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1976 prim
.VertexAccessType
= SEQUENTIAL
;
1977 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1979 prim
.PredicateEnable
= batch
->flags
& BLORP_BATCH_PREDICATE_ENABLE
;
1981 prim
.VertexCountPerInstance
= 3;
1982 prim
.InstanceCount
= params
->num_layers
;
1986 #endif /* BLORP_GENX_EXEC_H */