2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "common/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "intel_aub.h"
33 * This file provides the blorp pipeline setup and execution functionality.
34 * It defines the following function:
37 * blorp_exec(struct blorp_context *blorp, void *batch_data,
38 * const struct blorp_params *params);
40 * It is the job of whoever includes this header to wrap this in something
41 * to get an externally visible symbol.
43 * In order for the blorp_exec function to work, the driver must provide
44 * implementations of the following static helper functions.
48 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
51 blorp_emit_reloc(struct blorp_batch
*batch
,
52 void *location
, struct blorp_address address
, uint32_t delta
);
55 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
56 enum aub_state_struct_type type
,
61 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
62 struct blorp_address
*addr
);
65 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
66 unsigned state_size
, unsigned state_alignment
,
67 uint32_t *bt_offset
, uint32_t *surface_offsets
,
70 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
71 struct blorp_address address
, uint32_t delta
);
74 blorp_emit_urb_config(struct blorp_batch
*batch
, unsigned vs_entry_size
);
76 /***** BEGIN blorp_exec implementation ******/
78 #include "genxml/gen_macros.h"
81 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
82 struct blorp_address address
, uint32_t delta
)
84 if (address
.buffer
== NULL
) {
85 return address
.offset
+ delta
;
87 return blorp_emit_reloc(batch
, location
, address
, delta
);
91 #define __gen_address_type struct blorp_address
92 #define __gen_user_data struct blorp_batch
93 #define __gen_combine_address _blorp_combine_address
95 #include "genxml/genX_pack.h"
97 #define _blorp_cmd_length(cmd) cmd ## _length
98 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
99 #define _blorp_cmd_header(cmd) cmd ## _header
100 #define _blorp_cmd_pack(cmd) cmd ## _pack
102 #define blorp_emit(batch, cmd, name) \
103 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
104 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
105 __builtin_expect(_dst != NULL, 1); \
106 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
109 #define blorp_emitn(batch, cmd, n) ({ \
110 uint32_t *_dw = blorp_emit_dwords(batch, n); \
111 struct cmd template = { \
112 _blorp_cmd_header(cmd), \
113 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
115 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
116 _dw + 1; /* Array starts at dw[1] */ \
125 * Assign the entire URB to the VS. Even though the VS disabled, URB space
126 * is still needed because the clipper loads the VUE's from the URB. From
127 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
128 * Dword 1.15:0 "VS Number of URB Entries":
129 * This field is always used (even if VS Function Enable is DISABLED).
131 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
132 * safely ignore it because this batch contains only one draw call.
133 * Because of URB corruption caused by allocating a previous GS unit
134 * URB entry to the VS unit, software is required to send a “GS NULL
135 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
136 * plus a dummy DRAW call before any case where VS will be taking over
139 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
140 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
142 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
143 * programmed in order for the programming of this state to be
147 emit_urb_config(struct blorp_batch
*batch
,
148 const struct blorp_params
*params
)
150 /* Once vertex fetcher has written full VUE entries with complete
151 * header the space requirement is as follows per vertex (in bytes):
153 * Header Position Program constants
154 * +--------+------------+-------------------+
155 * | 16 | 16 | n x 16 |
156 * +--------+------------+-------------------+
158 * where 'n' stands for number of varying inputs expressed as vec4s.
160 const unsigned num_varyings
=
161 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
162 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
164 /* The URB size is expressed in units of 64 bytes (512 bits) */
165 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
167 blorp_emit_urb_config(batch
, vs_entry_size
);
171 blorp_emit_vertex_data(struct blorp_batch
*batch
,
172 const struct blorp_params
*params
,
173 struct blorp_address
*addr
,
176 const float vertices
[] = {
177 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
178 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
179 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
182 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
183 memcpy(data
, vertices
, sizeof(vertices
));
184 *size
= sizeof(vertices
);
188 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
189 const struct blorp_params
*params
,
190 struct blorp_address
*addr
,
193 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
194 const unsigned max_num_varyings
=
195 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
196 const unsigned num_varyings
= params
->wm_prog_data
->num_varying_inputs
;
198 *size
= num_varyings
* vec4_size_in_bytes
;
200 const float *const inputs_src
= (const float *)¶ms
->wm_inputs
;
201 float *inputs
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
203 /* Walk over the attribute slots, determine if the attribute is used by
204 * the program and when necessary copy the values from the input storage to
205 * the vertex data buffer.
207 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
208 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
210 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
214 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
221 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
222 const struct blorp_params
*params
)
224 struct GENX(VERTEX_BUFFER_STATE
) vb
[2];
225 memset(vb
, 0, sizeof(vb
));
227 unsigned num_buffers
= 1;
230 blorp_emit_vertex_data(batch
, params
, &vb
[0].BufferStartingAddress
, &size
);
231 vb
[0].VertexBufferIndex
= 0;
232 vb
[0].BufferPitch
= 3 * sizeof(float);
233 vb
[0].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
235 vb
[0].AddressModifyEnable
= true;
238 vb
[0].BufferSize
= size
;
240 vb
[0].BufferAccessType
= VERTEXDATA
;
241 vb
[0].EndAddress
= vb
[0].BufferStartingAddress
;
242 vb
[0].EndAddress
.offset
+= size
- 1;
245 if (params
->wm_prog_data
&& params
->wm_prog_data
->num_varying_inputs
) {
246 blorp_emit_input_varying_data(batch
, params
,
247 &vb
[1].BufferStartingAddress
, &size
);
248 vb
[1].VertexBufferIndex
= 1;
249 vb
[1].BufferPitch
= 0;
250 vb
[1].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
252 vb
[1].AddressModifyEnable
= true;
255 vb
[1].BufferSize
= size
;
257 vb
[1].BufferAccessType
= INSTANCEDATA
;
258 vb
[1].EndAddress
= vb
[1].BufferStartingAddress
;
259 vb
[1].EndAddress
.offset
+= size
- 1;
264 const unsigned num_dwords
=
265 1 + GENX(VERTEX_BUFFER_STATE_length
) * num_buffers
;
266 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
268 for (unsigned i
= 0; i
< num_buffers
; i
++) {
269 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
270 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
275 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
276 const struct blorp_params
*params
)
278 const unsigned num_varyings
=
279 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
280 const unsigned num_elements
= 2 + num_varyings
;
282 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
283 memset(ve
, 0, num_elements
* sizeof(*ve
));
285 /* Setup VBO for the rectangle primitive..
287 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
288 * vertices. The vertices reside in screen space with DirectX
289 * coordinates (that is, (0, 0) is the upper left corner).
296 * Since the VS is disabled, the clipper loads each VUE directly from
297 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
298 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
299 * dw0: Reserved, MBZ.
300 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
301 * to assign this with primitive instance identifier which will be
302 * used for layered clears. All other renders have only one instance
303 * and therefore the value will be effectively zero.
304 * dw2: Viewport Index. The HiZ op disables viewport mapping and
305 * scissoring, so set the dword to 0.
306 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
307 * so set the dword to 0.
308 * dw4: Vertex Position X.
309 * dw5: Vertex Position Y.
310 * dw6: Vertex Position Z.
311 * dw7: Vertex Position W.
313 * dw8: Flat vertex input 0
314 * dw9: Flat vertex input 1
316 * dwn: Flat vertex input n - 8
318 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
319 * "Vertex URB Entry (VUE) Formats".
321 * Only vertex position X and Y are going to be variable, Z is fixed to
322 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
323 * include the fixed values in the vertex buffer. Vertex fetcher can be
324 * instructed to fill vertex elements with constant values of one and zero
325 * instead of reading them from the buffer.
326 * Flat inputs are program constants that are not interpolated. Moreover
327 * their values will be the same between vertices.
329 * See the vertex element setup below.
331 ve
[0].VertexBufferIndex
= 0;
333 ve
[0].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
334 ve
[0].SourceElementOffset
= 0;
335 ve
[0].Component0Control
= VFCOMP_STORE_0
;
337 /* From Gen8 onwards hardware is no more instructed to overwrite components
338 * using an element specifier. Instead one has separate 3DSTATE_VF_SGVS
339 * (System Generated Value Setup) state packet for it.
342 ve
[0].Component1Control
= VFCOMP_STORE_0
;
344 ve
[0].Component1Control
= VFCOMP_STORE_IID
;
346 ve
[0].Component2Control
= VFCOMP_STORE_0
;
347 ve
[0].Component3Control
= VFCOMP_STORE_0
;
349 ve
[1].VertexBufferIndex
= 0;
351 ve
[1].SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
;
352 ve
[1].SourceElementOffset
= 0;
353 ve
[1].Component0Control
= VFCOMP_STORE_SRC
;
354 ve
[1].Component1Control
= VFCOMP_STORE_SRC
;
355 ve
[1].Component2Control
= VFCOMP_STORE_SRC
;
356 ve
[1].Component3Control
= VFCOMP_STORE_1_FP
;
358 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
359 ve
[i
+ 2].VertexBufferIndex
= 1;
360 ve
[i
+ 2].Valid
= true;
361 ve
[i
+ 2].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
362 ve
[i
+ 2].SourceElementOffset
= i
* 4 * sizeof(float);
363 ve
[i
+ 2].Component0Control
= VFCOMP_STORE_SRC
;
364 ve
[i
+ 2].Component1Control
= VFCOMP_STORE_SRC
;
365 ve
[i
+ 2].Component2Control
= VFCOMP_STORE_SRC
;
366 ve
[i
+ 2].Component3Control
= VFCOMP_STORE_SRC
;
369 const unsigned num_dwords
=
370 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
371 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
373 for (unsigned i
= 0; i
< num_elements
; i
++) {
374 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
375 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
379 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
380 * primitive instance identifier. This is used for layered clears.
382 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
383 sgvs
.InstanceIDEnable
= true;
384 sgvs
.InstanceIDComponentNumber
= COMP_1
;
385 sgvs
.InstanceIDElementOffset
= 0;
388 for (unsigned i
= 0; i
< num_elements
; i
++) {
389 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
390 vf
.VertexElementIndex
= i
;
391 vf
.InstancingEnable
= false;
395 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
396 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
402 blorp_emit_sf_config(struct blorp_batch
*batch
,
403 const struct blorp_params
*params
)
405 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
409 * Disable ViewportTransformEnable (dw2.1)
411 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
412 * Primitives Overview":
413 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
414 * use of screen- space coordinates).
416 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
417 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
419 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
420 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
421 * SOLID: Any triangle or rectangle object found to be front-facing
422 * is rendered as a solid object. This setting is required when
423 * (rendering rectangle (RECTLIST) objects.
428 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
430 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
431 raster
.CullMode
= CULLMODE_NONE
;
434 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
435 sbe
.VertexURBEntryReadOffset
= 1;
437 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
438 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
439 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
441 sbe
.NumberofSFOutputAttributes
= 0;
442 sbe
.VertexURBEntryReadLength
= 1;
444 sbe
.ForceVertexURBEntryReadLength
= true;
445 sbe
.ForceVertexURBEntryReadOffset
= true;
448 for (unsigned i
= 0; i
< 32; i
++)
449 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
455 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
456 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
457 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
459 sf
.MultisampleRasterizationMode
= params
->dst
.surf
.samples
> 1 ?
460 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
463 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
467 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
468 sbe
.VertexURBEntryReadOffset
= 1;
470 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
471 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
472 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
474 sbe
.NumberofSFOutputAttributes
= 0;
475 sbe
.VertexURBEntryReadLength
= 1;
479 #else /* GEN_GEN <= 6 */
481 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
482 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
483 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
485 sf
.MultisampleRasterizationMode
= params
->dst
.surf
.samples
> 1 ?
486 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
488 sf
.VertexURBEntryReadOffset
= 1;
490 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
491 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
492 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
494 sf
.NumberofSFOutputAttributes
= 0;
495 sf
.VertexURBEntryReadLength
= 1;
503 blorp_emit_ps_config(struct blorp_batch
*batch
,
504 const struct blorp_params
*params
)
506 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
508 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
509 * nonzero to prevent the GPU from hanging. While the documentation doesn't
510 * mention this explicitly, it notes that the valid range for the field is
511 * [1,39] = [2,40] threads, which excludes zero.
513 * To be safe (and to minimize extraneous code) we go ahead and fully
514 * configure the WM state whether or not there is a WM program.
519 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
521 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
522 if (params
->src
.enabled
) {
523 ps
.SamplerCount
= 1; /* Up to 4 samplers */
524 ps
.BindingTableEntryCount
= 2;
526 ps
.BindingTableEntryCount
= 1;
530 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
531 prog_data
->base
.dispatch_grf_start_reg
;
532 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
533 prog_data
->dispatch_grf_start_reg_2
;
535 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
536 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
538 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
539 ps
.KernelStartPointer2
=
540 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
543 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
544 * it implicitly scales for different GT levels (which have some # of
547 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
550 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
552 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
554 switch (params
->fast_clear_op
) {
555 case BLORP_FAST_CLEAR_OP_NONE
:
558 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
559 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
561 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
562 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
565 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
566 ps
.RenderTargetResolveEnable
= true;
569 case BLORP_FAST_CLEAR_OP_CLEAR
:
570 ps
.RenderTargetFastClearEnable
= true;
573 unreachable("Invalid fast clear op");
577 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
579 psx
.PixelShaderValid
= true;
580 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
581 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
584 if (params
->src
.enabled
)
585 psx
.PixelShaderKillsPixel
= true;
590 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
591 switch (params
->hiz_op
) {
592 case BLORP_HIZ_OP_DEPTH_CLEAR
:
593 wm
.DepthBufferClear
= true;
595 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
596 wm
.DepthBufferResolveEnable
= true;
598 case BLORP_HIZ_OP_HIZ_RESOLVE
:
599 wm
.HierarchicalDepthBufferResolveEnable
= true;
601 case BLORP_HIZ_OP_NONE
:
604 unreachable("not reached");
608 wm
.ThreadDispatchEnable
= true;
610 if (params
->src
.enabled
)
611 wm
.PixelShaderKillPixel
= true;
613 if (params
->dst
.surf
.samples
> 1) {
614 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
615 wm
.MultisampleDispatchMode
=
616 (prog_data
&& prog_data
->persample_dispatch
) ?
617 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
619 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
620 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
624 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
625 ps
.MaximumNumberofThreads
=
626 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
633 ps
.DispatchGRFStartRegisterforConstantSetupData0
=
634 prog_data
->base
.dispatch_grf_start_reg
;
635 ps
.DispatchGRFStartRegisterforConstantSetupData2
=
636 prog_data
->dispatch_grf_start_reg_2
;
638 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
639 ps
.KernelStartPointer2
=
640 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
642 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
643 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
645 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
647 /* Gen7 hardware gets angry if we don't enable at least one dispatch
648 * mode, so just enable 16-pixel dispatch if we don't have a program.
650 ps
._16PixelDispatchEnable
= true;
653 if (params
->src
.enabled
)
654 ps
.SamplerCount
= 1; /* Up to 4 samplers */
656 switch (params
->fast_clear_op
) {
657 case BLORP_FAST_CLEAR_OP_NONE
:
659 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
660 ps
.RenderTargetResolveEnable
= true;
662 case BLORP_FAST_CLEAR_OP_CLEAR
:
663 ps
.RenderTargetFastClearEnable
= true;
666 unreachable("Invalid fast clear op");
670 #else /* GEN_GEN <= 6 */
672 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
673 wm
.MaximumNumberofThreads
=
674 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
676 switch (params
->hiz_op
) {
677 case BLORP_HIZ_OP_DEPTH_CLEAR
:
678 wm
.DepthBufferClear
= true;
680 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
681 wm
.DepthBufferResolveEnable
= true;
683 case BLORP_HIZ_OP_HIZ_RESOLVE
:
684 wm
.HierarchicalDepthBufferResolveEnable
= true;
686 case BLORP_HIZ_OP_NONE
:
689 unreachable("not reached");
693 wm
.ThreadDispatchEnable
= true;
695 wm
.DispatchGRFStartRegisterforConstantSetupData0
=
696 prog_data
->base
.dispatch_grf_start_reg
;
697 wm
.DispatchGRFStartRegisterforConstantSetupData2
=
698 prog_data
->dispatch_grf_start_reg_2
;
700 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
701 wm
.KernelStartPointer2
=
702 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
704 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
705 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
707 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
710 if (params
->src
.enabled
) {
711 wm
.SamplerCount
= 1; /* Up to 4 samplers */
712 wm
.PixelShaderKillPixel
= true; /* TODO: temporarily smash on */
715 if (params
->dst
.surf
.samples
> 1) {
716 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
717 wm
.MultisampleDispatchMode
=
718 (prog_data
&& prog_data
->persample_dispatch
) ?
719 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
721 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
722 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
729 static const uint32_t isl_to_gen_ds_surftype
[] = {
731 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
733 * "If depth/stencil is enabled with 1D render target, depth/stencil
734 * surface type needs to be set to 2D surface type and height set to 1.
735 * Depth will use (legacy) TileY and stencil will use TileW. For this
736 * case only, the Surface Type of the depth buffer can be 2D while the
737 * Surface Type of the render target(s) are 1D, representing an
738 * exception to a programming note above.
740 [ISL_SURF_DIM_1D
] = SURFTYPE_2D
,
742 [ISL_SURF_DIM_1D
] = SURFTYPE_1D
,
744 [ISL_SURF_DIM_2D
] = SURFTYPE_2D
,
745 [ISL_SURF_DIM_3D
] = SURFTYPE_3D
,
749 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
750 const struct blorp_params
*params
)
753 const uint32_t mocs
= 1; /* GEN7_MOCS_L3 */
755 const uint32_t mocs
= 0;
758 blorp_emit(batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
760 db
.DepthWriteEnable
= params
->depth
.enabled
;
761 db
.StencilWriteEnable
= params
->stencil
.enabled
;
765 db
.SeparateStencilBufferEnable
= true;
768 if (params
->depth
.enabled
) {
769 db
.SurfaceFormat
= params
->depth_format
;
770 db
.SurfaceType
= isl_to_gen_ds_surftype
[params
->depth
.surf
.dim
];
773 db
.TiledSurface
= true;
774 db
.TileWalk
= TILEWALK_YMAJOR
;
775 db
.MIPMapLayoutMode
= MIPLAYOUT_BELOW
;
778 db
.HierarchicalDepthBufferEnable
=
779 params
->depth
.aux_usage
== ISL_AUX_USAGE_HIZ
;
781 db
.Width
= params
->depth
.surf
.logical_level0_px
.width
- 1;
782 db
.Height
= params
->depth
.surf
.logical_level0_px
.height
- 1;
783 db
.RenderTargetViewExtent
= db
.Depth
=
784 params
->depth
.view
.array_len
- 1;
786 db
.LOD
= params
->depth
.view
.base_level
;
787 db
.MinimumArrayElement
= params
->depth
.view
.base_array_layer
;
789 db
.SurfacePitch
= params
->depth
.surf
.row_pitch
- 1;
792 isl_surf_get_array_pitch_el_rows(¶ms
->depth
.surf
) >> 2,
795 db
.SurfaceBaseAddress
= params
->depth
.addr
;
796 db
.DepthBufferMOCS
= mocs
;
797 } else if (params
->stencil
.enabled
) {
798 db
.SurfaceFormat
= D32_FLOAT
;
799 db
.SurfaceType
= isl_to_gen_ds_surftype
[params
->stencil
.surf
.dim
];
801 db
.Width
= params
->stencil
.surf
.logical_level0_px
.width
- 1;
802 db
.Height
= params
->stencil
.surf
.logical_level0_px
.height
- 1;
803 db
.RenderTargetViewExtent
= db
.Depth
=
804 params
->stencil
.view
.array_len
- 1;
806 db
.LOD
= params
->stencil
.view
.base_level
;
807 db
.MinimumArrayElement
= params
->stencil
.view
.base_array_layer
;
809 db
.SurfaceType
= SURFTYPE_NULL
;
810 db
.SurfaceFormat
= D32_FLOAT
;
814 blorp_emit(batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hiz
) {
815 if (params
->depth
.aux_usage
== ISL_AUX_USAGE_HIZ
) {
816 hiz
.SurfacePitch
= params
->depth
.aux_surf
.row_pitch
- 1;
817 hiz
.SurfaceBaseAddress
= params
->depth
.aux_addr
;
818 hiz
.HierarchicalDepthBufferMOCS
= mocs
;
821 isl_surf_get_array_pitch_sa_rows(¶ms
->depth
.aux_surf
) >> 2;
826 blorp_emit(batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
827 if (params
->stencil
.enabled
) {
828 #if GEN_GEN >= 8 || GEN_IS_HASWELL
829 sb
.StencilBufferEnable
= true;
832 sb
.SurfacePitch
= params
->stencil
.surf
.row_pitch
- 1,
835 isl_surf_get_array_pitch_el_rows(¶ms
->stencil
.surf
) >> 2,
838 sb
.SurfaceBaseAddress
= params
->stencil
.addr
;
839 sb
.StencilBufferMOCS
= batch
->blorp
->mocs
.tex
;
843 /* 3DSTATE_CLEAR_PARAMS
845 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
846 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
847 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
849 blorp_emit(batch
, GENX(3DSTATE_CLEAR_PARAMS
), clear
) {
850 clear
.DepthClearValueValid
= true;
851 clear
.DepthClearValue
= params
->depth
.clear_color
.u32
[0];
856 blorp_emit_blend_state(struct blorp_batch
*batch
,
857 const struct blorp_params
*params
)
859 struct GENX(BLEND_STATE
) blend
;
860 memset(&blend
, 0, sizeof(blend
));
862 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
863 blend
.Entry
[i
].PreBlendColorClampEnable
= true;
864 blend
.Entry
[i
].PostBlendColorClampEnable
= true;
865 blend
.Entry
[i
].ColorClampRange
= COLORCLAMP_RTFORMAT
;
867 blend
.Entry
[i
].WriteDisableRed
= params
->color_write_disable
[0];
868 blend
.Entry
[i
].WriteDisableGreen
= params
->color_write_disable
[1];
869 blend
.Entry
[i
].WriteDisableBlue
= params
->color_write_disable
[2];
870 blend
.Entry
[i
].WriteDisableAlpha
= params
->color_write_disable
[3];
874 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_BLEND_STATE
,
875 GENX(BLEND_STATE_length
) * 4,
877 GENX(BLEND_STATE_pack
)(NULL
, state
, &blend
);
880 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
881 sp
.BlendStatePointer
= offset
;
883 sp
.BlendStatePointerValid
= true;
889 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
890 ps_blend
.HasWriteableRT
= true;
898 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
899 const struct blorp_params
*params
)
901 struct GENX(COLOR_CALC_STATE
) cc
= { 0 };
904 cc
.StencilReferenceValue
= params
->stencil_ref
;
908 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_CC_STATE
,
909 GENX(COLOR_CALC_STATE_length
) * 4,
911 GENX(COLOR_CALC_STATE_pack
)(NULL
, state
, &cc
);
914 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
915 sp
.ColorCalcStatePointer
= offset
;
917 sp
.ColorCalcStatePointerValid
= true;
926 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
927 const struct blorp_params
*params
)
930 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
931 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
934 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
937 if (params
->depth
.enabled
) {
938 ds
.DepthBufferWriteEnable
= true;
940 switch (params
->hiz_op
) {
941 case BLORP_HIZ_OP_NONE
:
942 ds
.DepthTestEnable
= true;
943 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
946 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
947 * - 7.5.3.1 Depth Buffer Clear
948 * - 7.5.3.2 Depth Buffer Resolve
949 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
951 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
952 ds
.DepthTestEnable
= true;
953 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
956 case BLORP_HIZ_OP_DEPTH_CLEAR
:
957 case BLORP_HIZ_OP_HIZ_RESOLVE
:
958 ds
.DepthTestEnable
= false;
963 if (params
->stencil
.enabled
) {
964 ds
.StencilBufferWriteEnable
= true;
965 ds
.StencilTestEnable
= true;
966 ds
.DoubleSidedStencilEnable
= false;
968 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
969 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
971 ds
.StencilWriteMask
= params
->stencil_mask
;
973 ds
.StencilReferenceValue
= params
->stencil_ref
;
979 uint32_t *dw
= blorp_emit_dwords(batch
,
980 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
981 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
984 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_DEPTH_STENCIL_STATE
,
985 GENX(DEPTH_STENCIL_STATE_length
) * 4,
987 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
991 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
992 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
999 struct surface_state_info
{
1000 unsigned num_dwords
;
1001 unsigned ss_align
; /* Required alignment of RENDER_SURFACE_STATE in bytes */
1003 unsigned aux_reloc_dw
;
1006 static const struct surface_state_info surface_state_infos
[] = {
1007 [6] = {6, 32, 1, 0},
1008 [7] = {8, 32, 1, 6},
1009 [8] = {13, 64, 8, 10},
1010 [9] = {16, 64, 8, 10},
1014 blorp_emit_surface_state(struct blorp_batch
*batch
,
1015 const struct brw_blorp_surface_info
*surface
,
1016 uint32_t *state
, uint32_t state_offset
,
1017 bool is_render_target
)
1019 const struct surface_state_info ss_info
= surface_state_infos
[GEN_GEN
];
1021 struct isl_surf surf
= surface
->surf
;
1023 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1024 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1025 assert(surf
.logical_level0_px
.height
== 1);
1026 surf
.dim
= ISL_SURF_DIM_2D
;
1029 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1030 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1031 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1032 aux_usage
= ISL_AUX_USAGE_NONE
;
1034 const uint32_t mocs
=
1035 is_render_target
? batch
->blorp
->mocs
.rb
: batch
->blorp
->mocs
.tex
;
1037 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1038 .surf
= &surf
, .view
= &surface
->view
,
1039 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1040 .mocs
= mocs
, .clear_color
= surface
->clear_color
);
1042 blorp_surface_reloc(batch
, state_offset
+ ss_info
.reloc_dw
* 4,
1045 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1046 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1047 * used to store other information. This should be ok, however, because
1048 * surface buffer addresses are always 4K page alinged.
1050 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1051 blorp_surface_reloc(batch
, state_offset
+ ss_info
.aux_reloc_dw
* 4,
1052 surface
->aux_addr
, state
[ss_info
.aux_reloc_dw
]);
1057 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1058 const struct brw_blorp_surface_info
*surface
,
1061 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1062 .SurfaceType
= SURFTYPE_NULL
,
1063 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1064 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1065 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1066 .MIPCountLOD
= surface
->view
.base_level
,
1067 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1068 .Depth
= surface
->view
.array_len
- 1,
1069 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1070 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1073 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1079 .TiledSurface
= true,
1083 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1087 blorp_emit_surface_states(struct blorp_batch
*batch
,
1088 const struct blorp_params
*params
)
1090 uint32_t bind_offset
, surface_offsets
[2];
1091 void *surface_maps
[2];
1093 const unsigned ss_size
= GENX(RENDER_SURFACE_STATE_length
) * 4;
1094 const unsigned ss_align
= GENX(RENDER_SURFACE_STATE_length
) > 8 ? 64 : 32;
1096 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1097 blorp_alloc_binding_table(batch
, num_surfaces
, ss_size
, ss_align
,
1098 &bind_offset
, surface_offsets
, surface_maps
);
1100 if (params
->dst
.enabled
) {
1101 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1102 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1103 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1106 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1107 const struct brw_blorp_surface_info
*surface
=
1108 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1109 blorp_emit_null_surface_state(batch
, surface
,
1110 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1113 if (params
->src
.enabled
) {
1114 blorp_emit_surface_state(batch
, ¶ms
->src
,
1115 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1116 surface_offsets
[BLORP_TEXTURE_BT_INDEX
], false);
1120 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1121 bt
.PointertoPSBindingTable
= bind_offset
;
1124 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1125 bt
.PSBindingTableChange
= true;
1126 bt
.PointertoPSBindingTable
= bind_offset
;
1132 blorp_emit_sampler_state(struct blorp_batch
*batch
,
1133 const struct blorp_params
*params
)
1135 struct GENX(SAMPLER_STATE
) sampler
= {
1136 .MipModeFilter
= MIPFILTER_NONE
,
1137 .MagModeFilter
= MAPFILTER_LINEAR
,
1138 .MinModeFilter
= MAPFILTER_LINEAR
,
1141 .TCXAddressControlMode
= TCM_CLAMP
,
1142 .TCYAddressControlMode
= TCM_CLAMP
,
1143 .TCZAddressControlMode
= TCM_CLAMP
,
1144 .MaximumAnisotropy
= RATIO21
,
1145 .RAddressMinFilterRoundingEnable
= true,
1146 .RAddressMagFilterRoundingEnable
= true,
1147 .VAddressMinFilterRoundingEnable
= true,
1148 .VAddressMagFilterRoundingEnable
= true,
1149 .UAddressMinFilterRoundingEnable
= true,
1150 .UAddressMagFilterRoundingEnable
= true,
1151 .NonnormalizedCoordinateEnable
= true,
1155 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_SAMPLER_STATE
,
1156 GENX(SAMPLER_STATE_length
) * 4,
1158 GENX(SAMPLER_STATE_pack
)(NULL
, state
, &sampler
);
1161 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
1162 ssp
.PointertoPSSamplerState
= offset
;
1165 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
1166 ssp
.VSSamplerStateChange
= true;
1167 ssp
.GSSamplerStateChange
= true;
1168 ssp
.PSSamplerStateChange
= true;
1169 ssp
.PointertoPSSamplerState
= offset
;
1175 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1176 const struct blorp_params
*params
)
1178 const unsigned samples
= params
->dst
.surf
.samples
;
1180 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1181 ms
.NumberofMultisamples
= __builtin_ffs(samples
) - 1;
1184 /* The PRM says that this bit is valid only for DX9:
1186 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1187 * should not have any effect by setting or not setting this bit.
1189 ms
.PixelPositionOffsetEnable
= false;
1190 ms
.PixelLocation
= CENTER
;
1192 ms
.PixelLocation
= PIXLOC_CENTER
;
1196 GEN_SAMPLE_POS_1X(ms
.Sample
);
1199 GEN_SAMPLE_POS_2X(ms
.Sample
);
1202 GEN_SAMPLE_POS_4X(ms
.Sample
);
1205 GEN_SAMPLE_POS_8X(ms
.Sample
);
1211 ms
.PixelLocation
= PIXLOC_CENTER
;
1212 GEN_SAMPLE_POS_4X(ms
.Sample
);
1217 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
1219 blorp_emit_viewport_state(struct blorp_batch
*batch
,
1220 const struct blorp_params
*params
)
1222 uint32_t cc_vp_offset
;
1224 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_CC_VP_STATE
,
1225 GENX(CC_VIEWPORT_length
) * 4, 32,
1228 GENX(CC_VIEWPORT_pack
)(batch
, state
,
1229 &(struct GENX(CC_VIEWPORT
)) {
1230 .MinimumDepth
= 0.0,
1231 .MaximumDepth
= 1.0,
1235 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
1236 vsp
.CCViewportPointer
= cc_vp_offset
;
1239 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
1240 vsp
.CCViewportStateChange
= true;
1241 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
1248 * \brief Execute a blit or render pass operation.
1250 * To execute the operation, this function manually constructs and emits a
1251 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1252 * constructing and after emitting the batch.
1254 * This function alters no GL state.
1257 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1259 uint32_t blend_state_offset
= 0;
1260 uint32_t color_calc_state_offset
= 0;
1261 uint32_t depth_stencil_state_offset
;
1263 blorp_emit_vertex_buffers(batch
, params
);
1264 blorp_emit_vertex_elements(batch
, params
);
1266 emit_urb_config(batch
, params
);
1268 if (params
->wm_prog_data
) {
1269 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1271 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1272 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1275 /* 3DSTATE_CC_STATE_POINTERS
1277 * The pointer offsets are relative to
1278 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1280 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1282 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1283 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1284 * one CC_STATE_POINTERS packet so we have to emit that here.
1286 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1287 cc
.BLEND_STATEChange
= true;
1288 cc
.COLOR_CALC_STATEChange
= true;
1289 cc
.DEPTH_STENCIL_STATEChange
= true;
1290 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1291 cc
.PointertoCOLOR_CALC_STATE
= color_calc_state_offset
;
1292 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1295 (void)blend_state_offset
;
1296 (void)color_calc_state_offset
;
1297 (void)depth_stencil_state_offset
;
1300 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1302 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1303 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1305 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1306 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1308 blorp_emit_surface_states(batch
, params
);
1310 if (params
->src
.enabled
)
1311 blorp_emit_sampler_state(batch
, params
);
1313 blorp_emit_3dstate_multisample(batch
, params
);
1315 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1316 mask
.SampleMask
= (1 << params
->dst
.surf
.samples
) - 1;
1319 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1320 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1322 * [DevSNB] A pipeline flush must be programmed prior to a
1323 * 3DSTATE_VS command that causes the VS Function Enable to
1324 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1325 * command with CS stall bit set and a post sync operation.
1327 * We've already done one at the start of the BLORP operation.
1329 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
);
1331 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1332 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1333 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1334 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1336 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1338 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1339 clip
.PerspectiveDivideDisable
= true;
1342 blorp_emit_sf_config(batch
, params
);
1343 blorp_emit_ps_config(batch
, params
);
1345 blorp_emit_viewport_state(batch
, params
);
1347 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1348 blorp_emit_depth_stencil_config(batch
, params
);
1350 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1351 prim
.VertexAccessType
= SEQUENTIAL
;
1352 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1353 prim
.VertexCountPerInstance
= 3;
1354 prim
.InstanceCount
= params
->num_layers
;
1358 #endif /* BLORP_GENX_EXEC_H */