2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "common/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
32 * This file provides the blorp pipeline setup and execution functionality.
33 * It defines the following function:
36 * blorp_exec(struct blorp_context *blorp, void *batch_data,
37 * const struct blorp_params *params);
39 * It is the job of whoever includes this header to wrap this in something
40 * to get an externally visible symbol.
42 * In order for the blorp_exec function to work, the driver must provide
43 * implementations of the following static helper functions.
47 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
50 blorp_emit_reloc(struct blorp_batch
*batch
,
51 void *location
, struct blorp_address address
, uint32_t delta
);
54 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
59 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
60 struct blorp_address
*addr
);
63 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
64 unsigned state_size
, unsigned state_alignment
,
65 uint32_t *bt_offset
, uint32_t *surface_offsets
,
69 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
72 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
73 struct blorp_address address
, uint32_t delta
);
76 blorp_emit_urb_config(struct blorp_batch
*batch
,
77 unsigned vs_entry_size
, unsigned sf_entry_size
);
80 blorp_emit_pipeline(struct blorp_batch
*batch
,
81 const struct blorp_params
*params
);
83 /***** BEGIN blorp_exec implementation ******/
85 #include "genxml/gen_macros.h"
88 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
89 struct blorp_address address
, uint32_t delta
)
91 if (address
.buffer
== NULL
) {
92 return address
.offset
+ delta
;
94 return blorp_emit_reloc(batch
, location
, address
, delta
);
98 #define __gen_address_type struct blorp_address
99 #define __gen_user_data struct blorp_batch
100 #define __gen_combine_address _blorp_combine_address
102 #include "genxml/genX_pack.h"
104 #define _blorp_cmd_length(cmd) cmd ## _length
105 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
106 #define _blorp_cmd_header(cmd) cmd ## _header
107 #define _blorp_cmd_pack(cmd) cmd ## _pack
109 #define blorp_emit(batch, cmd, name) \
110 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
111 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
112 __builtin_expect(_dst != NULL, 1); \
113 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
116 #define blorp_emitn(batch, cmd, n) ({ \
117 uint32_t *_dw = blorp_emit_dwords(batch, n); \
119 struct cmd template = { \
120 _blorp_cmd_header(cmd), \
121 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
123 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
125 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
128 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
130 #define blorp_emit_dynamic(batch, state, name, align, offset) \
131 for (struct state name = STRUCT_ZERO(state), \
132 *_dst = blorp_alloc_dynamic_state(batch, \
133 _blorp_cmd_length(state) * 4, \
135 __builtin_expect(_dst != NULL, 1); \
136 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
137 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
146 * Assign the entire URB to the VS. Even though the VS disabled, URB space
147 * is still needed because the clipper loads the VUE's from the URB. From
148 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
149 * Dword 1.15:0 "VS Number of URB Entries":
150 * This field is always used (even if VS Function Enable is DISABLED).
152 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
153 * safely ignore it because this batch contains only one draw call.
154 * Because of URB corruption caused by allocating a previous GS unit
155 * URB entry to the VS unit, software is required to send a “GS NULL
156 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
157 * plus a dummy DRAW call before any case where VS will be taking over
160 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
161 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
163 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
164 * programmed in order for the programming of this state to be
168 emit_urb_config(struct blorp_batch
*batch
,
169 const struct blorp_params
*params
)
171 /* Once vertex fetcher has written full VUE entries with complete
172 * header the space requirement is as follows per vertex (in bytes):
174 * Header Position Program constants
175 * +--------+------------+-------------------+
176 * | 16 | 16 | n x 16 |
177 * +--------+------------+-------------------+
179 * where 'n' stands for number of varying inputs expressed as vec4s.
181 const unsigned num_varyings
=
182 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
183 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
185 /* The URB size is expressed in units of 64 bytes (512 bits) */
186 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
188 const unsigned sf_entry_size
=
189 params
->sf_prog_data
? params
->sf_prog_data
->urb_entry_size
: 0;
191 blorp_emit_urb_config(batch
, vs_entry_size
, sf_entry_size
);
195 blorp_emit_vertex_data(struct blorp_batch
*batch
,
196 const struct blorp_params
*params
,
197 struct blorp_address
*addr
,
200 const float vertices
[] = {
201 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
202 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
203 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
206 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
207 memcpy(data
, vertices
, sizeof(vertices
));
208 *size
= sizeof(vertices
);
209 blorp_flush_range(batch
, data
, *size
);
213 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
214 const struct blorp_params
*params
,
215 struct blorp_address
*addr
,
218 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
219 const unsigned max_num_varyings
=
220 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
221 const unsigned num_varyings
=
222 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
224 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
226 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
227 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
228 uint32_t *inputs
= data
;
230 /* Copy in the VS inputs */
231 assert(sizeof(params
->vs_inputs
) == 16);
232 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
235 if (params
->wm_prog_data
) {
236 /* Walk over the attribute slots, determine if the attribute is used by
237 * the program and when necessary copy the values from the input storage
238 * to the vertex data buffer.
240 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
241 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
243 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
247 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
253 blorp_flush_range(batch
, data
, *size
);
257 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
258 const struct blorp_params
*params
)
260 struct GENX(VERTEX_BUFFER_STATE
) vb
[2];
261 memset(vb
, 0, sizeof(vb
));
264 blorp_emit_vertex_data(batch
, params
, &vb
[0].BufferStartingAddress
, &size
);
265 vb
[0].VertexBufferIndex
= 0;
266 vb
[0].BufferPitch
= 3 * sizeof(float);
268 vb
[0].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
271 vb
[0].AddressModifyEnable
= true;
274 vb
[0].BufferSize
= size
;
276 vb
[0].BufferAccessType
= VERTEXDATA
;
277 vb
[0].EndAddress
= vb
[0].BufferStartingAddress
;
278 vb
[0].EndAddress
.offset
+= size
- 1;
280 vb
[0].BufferAccessType
= VERTEXDATA
;
284 blorp_emit_input_varying_data(batch
, params
,
285 &vb
[1].BufferStartingAddress
, &size
);
286 vb
[1].VertexBufferIndex
= 1;
287 vb
[1].BufferPitch
= 0;
289 vb
[1].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
292 vb
[1].AddressModifyEnable
= true;
295 vb
[1].BufferSize
= size
;
297 vb
[1].BufferAccessType
= INSTANCEDATA
;
298 vb
[1].EndAddress
= vb
[1].BufferStartingAddress
;
299 vb
[1].EndAddress
.offset
+= size
- 1;
301 vb
[1].BufferAccessType
= INSTANCEDATA
;
305 const unsigned num_dwords
= 1 + GENX(VERTEX_BUFFER_STATE_length
) * 2;
306 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
310 for (unsigned i
= 0; i
< 2; i
++) {
311 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
312 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
317 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
318 const struct blorp_params
*params
)
320 const unsigned num_varyings
=
321 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
322 bool need_ndc
= batch
->blorp
->compiler
->devinfo
->gen
<= 5;
323 const unsigned num_elements
= 2 + need_ndc
+ num_varyings
;
325 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
326 memset(ve
, 0, num_elements
* sizeof(*ve
));
328 /* Setup VBO for the rectangle primitive..
330 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
331 * vertices. The vertices reside in screen space with DirectX
332 * coordinates (that is, (0, 0) is the upper left corner).
339 * Since the VS is disabled, the clipper loads each VUE directly from
340 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
341 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
342 * dw0: Reserved, MBZ.
343 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
344 * to assign this with primitive instance identifier which will be
345 * used for layered clears. All other renders have only one instance
346 * and therefore the value will be effectively zero.
347 * dw2: Viewport Index. The HiZ op disables viewport mapping and
348 * scissoring, so set the dword to 0.
349 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
350 * so set the dword to 0.
351 * dw4: Vertex Position X.
352 * dw5: Vertex Position Y.
353 * dw6: Vertex Position Z.
354 * dw7: Vertex Position W.
356 * dw8: Flat vertex input 0
357 * dw9: Flat vertex input 1
359 * dwn: Flat vertex input n - 8
361 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
362 * "Vertex URB Entry (VUE) Formats".
364 * Only vertex position X and Y are going to be variable, Z is fixed to
365 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
366 * include the fixed values in the vertex buffer. Vertex fetcher can be
367 * instructed to fill vertex elements with constant values of one and zero
368 * instead of reading them from the buffer.
369 * Flat inputs are program constants that are not interpolated. Moreover
370 * their values will be the same between vertices.
372 * See the vertex element setup below.
376 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
377 .VertexBufferIndex
= 1,
379 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
380 .SourceElementOffset
= 0,
381 .Component0Control
= VFCOMP_STORE_SRC
,
383 /* From Gen8 onwards hardware is no more instructed to overwrite
384 * components using an element specifier. Instead one has separate
385 * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it.
388 .Component1Control
= VFCOMP_STORE_0
,
390 .Component1Control
= VFCOMP_STORE_IID
,
392 .Component1Control
= VFCOMP_STORE_0
,
394 .Component2Control
= VFCOMP_STORE_SRC
,
395 .Component3Control
= VFCOMP_STORE_SRC
,
397 .DestinationElementOffset
= slot
* 4,
403 /* On Iron Lake and earlier, a native device coordinates version of the
404 * position goes right after the normal VUE header and before position.
405 * Since w == 1 for all of our coordinates, this is just a copy of the
408 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
409 .VertexBufferIndex
= 0,
411 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
412 .SourceElementOffset
= 0,
413 .Component0Control
= VFCOMP_STORE_SRC
,
414 .Component1Control
= VFCOMP_STORE_SRC
,
415 .Component2Control
= VFCOMP_STORE_SRC
,
416 .Component3Control
= VFCOMP_STORE_1_FP
,
417 .DestinationElementOffset
= slot
* 4,
422 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
423 .VertexBufferIndex
= 0,
425 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
426 .SourceElementOffset
= 0,
427 .Component0Control
= VFCOMP_STORE_SRC
,
428 .Component1Control
= VFCOMP_STORE_SRC
,
429 .Component2Control
= VFCOMP_STORE_SRC
,
430 .Component3Control
= VFCOMP_STORE_1_FP
,
432 .DestinationElementOffset
= slot
* 4,
437 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
438 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
439 .VertexBufferIndex
= 1,
441 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
442 .SourceElementOffset
= 16 + i
* 4 * sizeof(float),
443 .Component0Control
= VFCOMP_STORE_SRC
,
444 .Component1Control
= VFCOMP_STORE_SRC
,
445 .Component2Control
= VFCOMP_STORE_SRC
,
446 .Component3Control
= VFCOMP_STORE_SRC
,
448 .DestinationElementOffset
= slot
* 4,
454 const unsigned num_dwords
=
455 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
456 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
460 for (unsigned i
= 0; i
< num_elements
; i
++) {
461 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
462 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
466 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
467 * primitive instance identifier. This is used for layered clears.
469 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
470 sgvs
.InstanceIDEnable
= true;
471 sgvs
.InstanceIDComponentNumber
= COMP_1
;
472 sgvs
.InstanceIDElementOffset
= 0;
475 for (unsigned i
= 0; i
< num_elements
; i
++) {
476 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
477 vf
.VertexElementIndex
= i
;
478 vf
.InstancingEnable
= false;
482 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
483 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
488 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
490 blorp_emit_cc_viewport(struct blorp_batch
*batch
,
491 const struct blorp_params
*params
)
493 uint32_t cc_vp_offset
;
494 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
495 vp
.MinimumDepth
= 0.0;
496 vp
.MaximumDepth
= 1.0;
500 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
501 vsp
.CCViewportPointer
= cc_vp_offset
;
504 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
505 vsp
.CCViewportStateChange
= true;
506 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
514 blorp_emit_sampler_state(struct blorp_batch
*batch
,
515 const struct blorp_params
*params
)
518 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
519 sampler
.MipModeFilter
= MIPFILTER_NONE
;
520 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
521 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
524 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
525 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
526 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
527 sampler
.MaximumAnisotropy
= RATIO21
;
528 sampler
.RAddressMinFilterRoundingEnable
= true;
529 sampler
.RAddressMagFilterRoundingEnable
= true;
530 sampler
.VAddressMinFilterRoundingEnable
= true;
531 sampler
.VAddressMagFilterRoundingEnable
= true;
532 sampler
.UAddressMinFilterRoundingEnable
= true;
533 sampler
.UAddressMagFilterRoundingEnable
= true;
535 sampler
.NonnormalizedCoordinateEnable
= true;
540 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
541 ssp
.PointertoPSSamplerState
= offset
;
544 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
545 ssp
.VSSamplerStateChange
= true;
546 ssp
.GSSamplerStateChange
= true;
547 ssp
.PSSamplerStateChange
= true;
548 ssp
.PointertoPSSamplerState
= offset
;
555 /* What follows is the code for setting up a "pipeline" on Sandy Bridge and
556 * later hardware. This file will be included by i965 for gen4-5 as well, so
557 * this code is guarded by GEN_GEN >= 6.
562 blorp_emit_vs_config(struct blorp_batch
*batch
,
563 const struct blorp_params
*params
)
565 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
567 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
571 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
573 vs
.DispatchGRFStartRegisterForURBData
=
574 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
575 vs
.VertexURBEntryReadLength
=
576 vs_prog_data
->base
.urb_read_length
;
577 vs
.VertexURBEntryReadOffset
= 0;
579 vs
.MaximumNumberofThreads
=
580 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
583 vs
.SIMD8DispatchEnable
=
584 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
591 blorp_emit_sf_config(struct blorp_batch
*batch
,
592 const struct blorp_params
*params
)
594 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
598 * Disable ViewportTransformEnable (dw2.1)
600 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
601 * Primitives Overview":
602 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
603 * use of screen- space coordinates).
605 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
606 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
608 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
609 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
610 * SOLID: Any triangle or rectangle object found to be front-facing
611 * is rendered as a solid object. This setting is required when
612 * (rendering rectangle (RECTLIST) objects.
617 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
619 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
620 raster
.CullMode
= CULLMODE_NONE
;
623 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
624 sbe
.VertexURBEntryReadOffset
= 1;
626 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
627 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
628 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
630 sbe
.NumberofSFOutputAttributes
= 0;
631 sbe
.VertexURBEntryReadLength
= 1;
633 sbe
.ForceVertexURBEntryReadLength
= true;
634 sbe
.ForceVertexURBEntryReadOffset
= true;
637 for (unsigned i
= 0; i
< 32; i
++)
638 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
644 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
645 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
646 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
648 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
649 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
652 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
656 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
657 sbe
.VertexURBEntryReadOffset
= 1;
659 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
660 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
661 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
663 sbe
.NumberofSFOutputAttributes
= 0;
664 sbe
.VertexURBEntryReadLength
= 1;
668 #else /* GEN_GEN <= 6 */
670 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
671 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
672 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
674 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
675 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
677 sf
.VertexURBEntryReadOffset
= 1;
679 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
680 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
681 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
683 sf
.NumberofSFOutputAttributes
= 0;
684 sf
.VertexURBEntryReadLength
= 1;
692 blorp_emit_ps_config(struct blorp_batch
*batch
,
693 const struct blorp_params
*params
)
695 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
697 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
698 * nonzero to prevent the GPU from hanging. While the documentation doesn't
699 * mention this explicitly, it notes that the valid range for the field is
700 * [1,39] = [2,40] threads, which excludes zero.
702 * To be safe (and to minimize extraneous code) we go ahead and fully
703 * configure the WM state whether or not there is a WM program.
708 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
710 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
711 if (params
->src
.enabled
) {
712 ps
.SamplerCount
= 1; /* Up to 4 samplers */
713 ps
.BindingTableEntryCount
= 2;
715 ps
.BindingTableEntryCount
= 1;
719 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
720 prog_data
->base
.dispatch_grf_start_reg
;
721 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
722 prog_data
->dispatch_grf_start_reg_2
;
724 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
725 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
727 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
728 ps
.KernelStartPointer2
=
729 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
732 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
733 * it implicitly scales for different GT levels (which have some # of
736 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
739 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
741 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
743 switch (params
->fast_clear_op
) {
744 case BLORP_FAST_CLEAR_OP_NONE
:
747 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
748 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
750 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
751 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
754 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
755 ps
.RenderTargetResolveEnable
= true;
758 case BLORP_FAST_CLEAR_OP_CLEAR
:
759 ps
.RenderTargetFastClearEnable
= true;
762 unreachable("Invalid fast clear op");
766 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
768 psx
.PixelShaderValid
= true;
769 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
770 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
773 if (params
->src
.enabled
)
774 psx
.PixelShaderKillsPixel
= true;
779 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
780 switch (params
->hiz_op
) {
781 case BLORP_HIZ_OP_DEPTH_CLEAR
:
782 wm
.DepthBufferClear
= true;
784 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
785 wm
.DepthBufferResolveEnable
= true;
787 case BLORP_HIZ_OP_HIZ_RESOLVE
:
788 wm
.HierarchicalDepthBufferResolveEnable
= true;
790 case BLORP_HIZ_OP_NONE
:
793 unreachable("not reached");
797 wm
.ThreadDispatchEnable
= true;
799 if (params
->src
.enabled
)
800 wm
.PixelShaderKillsPixel
= true;
802 if (params
->num_samples
> 1) {
803 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
804 wm
.MultisampleDispatchMode
=
805 (prog_data
&& prog_data
->persample_dispatch
) ?
806 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
808 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
809 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
813 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
814 ps
.MaximumNumberofThreads
=
815 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
822 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
823 prog_data
->base
.dispatch_grf_start_reg
;
824 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
825 prog_data
->dispatch_grf_start_reg_2
;
827 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
828 ps
.KernelStartPointer2
=
829 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
831 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
832 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
834 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
836 /* Gen7 hardware gets angry if we don't enable at least one dispatch
837 * mode, so just enable 16-pixel dispatch if we don't have a program.
839 ps
._16PixelDispatchEnable
= true;
842 if (params
->src
.enabled
)
843 ps
.SamplerCount
= 1; /* Up to 4 samplers */
845 switch (params
->fast_clear_op
) {
846 case BLORP_FAST_CLEAR_OP_NONE
:
848 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
849 ps
.RenderTargetResolveEnable
= true;
851 case BLORP_FAST_CLEAR_OP_CLEAR
:
852 ps
.RenderTargetFastClearEnable
= true;
855 unreachable("Invalid fast clear op");
859 #else /* GEN_GEN <= 6 */
861 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
862 wm
.MaximumNumberofThreads
=
863 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
865 switch (params
->hiz_op
) {
866 case BLORP_HIZ_OP_DEPTH_CLEAR
:
867 wm
.DepthBufferClear
= true;
869 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
870 wm
.DepthBufferResolveEnable
= true;
872 case BLORP_HIZ_OP_HIZ_RESOLVE
:
873 wm
.HierarchicalDepthBufferResolveEnable
= true;
875 case BLORP_HIZ_OP_NONE
:
878 unreachable("not reached");
882 wm
.ThreadDispatchEnable
= true;
884 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
885 prog_data
->base
.dispatch_grf_start_reg
;
886 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
887 prog_data
->dispatch_grf_start_reg_2
;
889 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
890 wm
.KernelStartPointer2
=
891 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
893 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
894 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
896 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
899 if (params
->src
.enabled
) {
900 wm
.SamplerCount
= 1; /* Up to 4 samplers */
901 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
904 if (params
->num_samples
> 1) {
905 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
906 wm
.MultisampleDispatchMode
=
907 (prog_data
&& prog_data
->persample_dispatch
) ?
908 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
910 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
911 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
919 blorp_emit_blend_state(struct blorp_batch
*batch
,
920 const struct blorp_params
*params
)
922 struct GENX(BLEND_STATE
) blend
;
923 memset(&blend
, 0, sizeof(blend
));
926 int size
= GENX(BLEND_STATE_length
) * 4;
927 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
928 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
929 uint32_t *pos
= state
;
931 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
932 pos
+= GENX(BLEND_STATE_length
);
934 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
935 struct GENX(BLEND_STATE_ENTRY
) entry
= {
936 .PreBlendColorClampEnable
= true,
937 .PostBlendColorClampEnable
= true,
938 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
940 .WriteDisableRed
= params
->color_write_disable
[0],
941 .WriteDisableGreen
= params
->color_write_disable
[1],
942 .WriteDisableBlue
= params
->color_write_disable
[2],
943 .WriteDisableAlpha
= params
->color_write_disable
[3],
945 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
946 pos
+= GENX(BLEND_STATE_ENTRY_length
);
949 blorp_flush_range(batch
, state
, size
);
952 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
953 sp
.BlendStatePointer
= offset
;
955 sp
.BlendStatePointerValid
= true;
961 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
962 ps_blend
.HasWriteableRT
= true;
970 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
971 const struct blorp_params
*params
)
974 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
976 cc
.StencilReferenceValue
= params
->stencil_ref
;
981 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
982 sp
.ColorCalcStatePointer
= offset
;
984 sp
.ColorCalcStatePointerValid
= true;
993 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
994 const struct blorp_params
*params
)
997 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
998 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
1001 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
1004 if (params
->depth
.enabled
) {
1005 ds
.DepthBufferWriteEnable
= true;
1007 switch (params
->hiz_op
) {
1008 case BLORP_HIZ_OP_NONE
:
1009 ds
.DepthTestEnable
= true;
1010 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
1013 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
1014 * - 7.5.3.1 Depth Buffer Clear
1015 * - 7.5.3.2 Depth Buffer Resolve
1016 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1018 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1019 ds
.DepthTestEnable
= true;
1020 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
1023 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1024 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1025 ds
.DepthTestEnable
= false;
1030 if (params
->stencil
.enabled
) {
1031 ds
.StencilBufferWriteEnable
= true;
1032 ds
.StencilTestEnable
= true;
1033 ds
.DoubleSidedStencilEnable
= false;
1035 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1036 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1038 ds
.StencilWriteMask
= params
->stencil_mask
;
1040 ds
.StencilReferenceValue
= params
->stencil_ref
;
1045 uint32_t offset
= 0;
1046 uint32_t *dw
= blorp_emit_dwords(batch
,
1047 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1051 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1054 void *state
= blorp_alloc_dynamic_state(batch
,
1055 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1057 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1058 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1062 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1063 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1071 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1072 const struct blorp_params
*params
)
1074 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1075 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1078 /* The PRM says that this bit is valid only for DX9:
1080 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1081 * should not have any effect by setting or not setting this bit.
1083 ms
.PixelPositionOffsetEnable
= false;
1086 switch (params
->num_samples
) {
1088 GEN_SAMPLE_POS_1X(ms
.Sample
);
1091 GEN_SAMPLE_POS_2X(ms
.Sample
);
1094 GEN_SAMPLE_POS_4X(ms
.Sample
);
1097 GEN_SAMPLE_POS_8X(ms
.Sample
);
1103 GEN_SAMPLE_POS_4X(ms
.Sample
);
1105 ms
.PixelLocation
= CENTER
;
1110 blorp_emit_pipeline(struct blorp_batch
*batch
,
1111 const struct blorp_params
*params
)
1113 uint32_t blend_state_offset
= 0;
1114 uint32_t color_calc_state_offset
;
1115 uint32_t depth_stencil_state_offset
;
1117 emit_urb_config(batch
, params
);
1119 if (params
->wm_prog_data
) {
1120 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1122 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1123 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1126 /* 3DSTATE_CC_STATE_POINTERS
1128 * The pointer offsets are relative to
1129 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1131 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1133 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1134 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1135 * one CC_STATE_POINTERS packet so we have to emit that here.
1137 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1138 cc
.BLEND_STATEChange
= true;
1139 cc
.ColorCalcStatePointerValid
= true;
1140 cc
.DEPTH_STENCIL_STATEChange
= true;
1141 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1142 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1143 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1146 (void)blend_state_offset
;
1147 (void)color_calc_state_offset
;
1148 (void)depth_stencil_state_offset
;
1151 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1153 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1154 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1156 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1157 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1159 if (params
->src
.enabled
)
1160 blorp_emit_sampler_state(batch
, params
);
1162 blorp_emit_3dstate_multisample(batch
, params
);
1164 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1165 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1168 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1169 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1171 * [DevSNB] A pipeline flush must be programmed prior to a
1172 * 3DSTATE_VS command that causes the VS Function Enable to
1173 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1174 * command with CS stall bit set and a post sync operation.
1176 * We've already done one at the start of the BLORP operation.
1178 blorp_emit_vs_config(batch
, params
);
1180 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1181 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1182 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1183 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1185 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1187 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1188 clip
.PerspectiveDivideDisable
= true;
1191 blorp_emit_sf_config(batch
, params
);
1192 blorp_emit_ps_config(batch
, params
);
1194 blorp_emit_cc_viewport(batch
, params
);
1197 /******** This is the end of the pipeline setup code ********/
1199 #endif /* GEN_GEN >= 6 */
1202 blorp_emit_surface_state(struct blorp_batch
*batch
,
1203 const struct brw_blorp_surface_info
*surface
,
1204 void *state
, uint32_t state_offset
,
1205 const bool color_write_disables
[4],
1206 bool is_render_target
)
1208 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1209 struct isl_surf surf
= surface
->surf
;
1211 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1212 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1213 assert(surf
.logical_level0_px
.height
== 1);
1214 surf
.dim
= ISL_SURF_DIM_2D
;
1217 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1218 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1219 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1220 aux_usage
= ISL_AUX_USAGE_NONE
;
1222 isl_channel_mask_t write_disable_mask
= 0;
1223 if (is_render_target
&& GEN_GEN
<= 5) {
1224 if (color_write_disables
[0])
1225 write_disable_mask
|= ISL_CHANNEL_RED_BIT
;
1226 if (color_write_disables
[1])
1227 write_disable_mask
|= ISL_CHANNEL_GREEN_BIT
;
1228 if (color_write_disables
[2])
1229 write_disable_mask
|= ISL_CHANNEL_BLUE_BIT
;
1230 if (color_write_disables
[3])
1231 write_disable_mask
|= ISL_CHANNEL_ALPHA_BIT
;
1234 const uint32_t mocs
=
1235 is_render_target
? batch
->blorp
->mocs
.rb
: batch
->blorp
->mocs
.tex
;
1237 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1238 .surf
= &surf
, .view
= &surface
->view
,
1239 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1240 .mocs
= mocs
, .clear_color
= surface
->clear_color
,
1241 .write_disables
= write_disable_mask
);
1243 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1246 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1247 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1248 * used to store other information. This should be ok, however, because
1249 * surface buffer addresses are always 4K page alinged.
1251 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1252 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1253 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1254 surface
->aux_addr
, *aux_addr
);
1257 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1261 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1262 const struct brw_blorp_surface_info
*surface
,
1265 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1266 .SurfaceType
= SURFTYPE_NULL
,
1267 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1268 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1269 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1270 .MIPCountLOD
= surface
->view
.base_level
,
1271 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1272 .Depth
= surface
->view
.array_len
- 1,
1273 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1275 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1279 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1285 .TiledSurface
= true,
1289 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1291 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1295 blorp_emit_surface_states(struct blorp_batch
*batch
,
1296 const struct blorp_params
*params
)
1298 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1299 uint32_t bind_offset
, surface_offsets
[2];
1300 void *surface_maps
[2];
1302 if (params
->use_pre_baked_binding_table
) {
1303 bind_offset
= params
->pre_baked_binding_table_offset
;
1305 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1306 blorp_alloc_binding_table(batch
, num_surfaces
,
1307 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1308 &bind_offset
, surface_offsets
, surface_maps
);
1310 if (params
->dst
.enabled
) {
1311 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1312 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1313 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1314 params
->color_write_disable
, true);
1316 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1317 const struct brw_blorp_surface_info
*surface
=
1318 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1319 blorp_emit_null_surface_state(batch
, surface
,
1320 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1323 if (params
->src
.enabled
) {
1324 blorp_emit_surface_state(batch
, ¶ms
->src
,
1325 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1326 surface_offsets
[BLORP_TEXTURE_BT_INDEX
],
1332 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1333 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1334 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1335 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1337 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1338 bt
.PointertoPSBindingTable
= bind_offset
;
1341 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1342 bt
.PSBindingTableChange
= true;
1343 bt
.PointertoPSBindingTable
= bind_offset
;
1346 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1347 bt
.PointertoPSBindingTable
= bind_offset
;
1353 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
1354 const struct blorp_params
*params
)
1356 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1358 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
1362 struct isl_depth_stencil_hiz_emit_info info
= {
1364 .mocs
= 1, /* GEN7_MOCS_L3 */
1370 if (params
->depth
.enabled
) {
1371 info
.view
= ¶ms
->depth
.view
;
1372 } else if (params
->stencil
.enabled
) {
1373 info
.view
= ¶ms
->stencil
.view
;
1376 if (params
->depth
.enabled
) {
1377 info
.depth_surf
= ¶ms
->depth
.surf
;
1379 info
.depth_address
=
1380 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
1381 params
->depth
.addr
, 0);
1383 info
.hiz_usage
= params
->depth
.aux_usage
;
1384 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
1385 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
1387 struct blorp_address hiz_address
= params
->depth
.aux_addr
;
1389 /* Sandy bridge hardware does not technically support mipmapped HiZ.
1390 * However, we have a special layout that allows us to make it work
1391 * anyway by manually offsetting to the specified miplevel.
1393 assert(info
.hiz_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1395 isl_surf_get_image_offset_B_tile_sa(info
.hiz_surf
,
1396 info
.view
->base_level
, 0, 0,
1397 &offset_B
, NULL
, NULL
);
1398 hiz_address
.offset
+= offset_B
;
1402 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
1405 info
.depth_clear_value
= params
->depth
.clear_color
.f32
[0];
1409 if (params
->stencil
.enabled
) {
1410 info
.stencil_surf
= ¶ms
->stencil
.surf
;
1412 struct blorp_address stencil_address
= params
->stencil
.addr
;
1414 /* Sandy bridge hardware does not technically support mipmapped stencil.
1415 * However, we have a special layout that allows us to make it work
1416 * anyway by manually offsetting to the specified miplevel.
1418 assert(info
.stencil_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1420 isl_surf_get_image_offset_B_tile_sa(info
.stencil_surf
,
1421 info
.view
->base_level
, 0, 0,
1422 &offset_B
, NULL
, NULL
);
1423 stencil_address
.offset
+= offset_B
;
1426 info
.stencil_address
=
1427 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
1428 stencil_address
, 0);
1431 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
1435 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1436 * depth/stencil buffer extents are ignored to handle APIs which perform
1437 * clearing operations without such information.
1440 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1441 const struct blorp_params
*params
)
1443 /* We should be performing an operation on a depth or stencil buffer.
1445 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1447 /* The stencil buffer should only be enabled if a fast clear operation is
1450 if (params
->stencil
.enabled
)
1451 assert(params
->hiz_op
== BLORP_HIZ_OP_DEPTH_CLEAR
);
1453 /* If we can't alter the depth stencil config and multiple layers are
1454 * involved, the HiZ op will fail. This is because the op requires that a
1455 * new config is emitted for each additional layer.
1457 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1458 assert(params
->num_layers
<= 1);
1460 blorp_emit_depth_stencil_config(batch
, params
);
1463 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1464 switch (params
->hiz_op
) {
1465 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1466 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1467 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1468 hzp
.StencilClearValue
= params
->stencil_ref
;
1470 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1471 hzp
.DepthBufferResolveEnable
= true;
1473 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1474 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1476 case BLORP_HIZ_OP_NONE
:
1477 unreachable("Invalid HIZ op");
1480 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1481 hzp
.SampleMask
= 0xFFFF;
1483 /* Due to a hardware issue, this bit MBZ */
1484 assert(hzp
.ScissorRectangleEnable
== false);
1486 /* Contrary to the HW docs both fields are inclusive */
1487 hzp
.ClearRectangleXMin
= params
->x0
;
1488 hzp
.ClearRectangleYMin
= params
->y0
;
1490 /* Contrary to the HW docs both fields are exclusive */
1491 hzp
.ClearRectangleXMax
= params
->x1
;
1492 hzp
.ClearRectangleYMax
= params
->y1
;
1495 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1496 * to “Write Immediate Data” enabled.
1498 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1499 pc
.PostSyncOperation
= WriteImmediateData
;
1502 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1507 * \brief Execute a blit or render pass operation.
1509 * To execute the operation, this function manually constructs and emits a
1510 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1511 * constructing and after emitting the batch.
1513 * This function alters no GL state.
1516 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1519 if (params
->hiz_op
!= BLORP_HIZ_OP_NONE
) {
1520 blorp_emit_gen8_hiz_op(batch
, params
);
1525 blorp_emit_vertex_buffers(batch
, params
);
1526 blorp_emit_vertex_elements(batch
, params
);
1528 blorp_emit_pipeline(batch
, params
);
1530 blorp_emit_surface_states(batch
, params
);
1532 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1533 blorp_emit_depth_stencil_config(batch
, params
);
1535 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1536 prim
.VertexAccessType
= SEQUENTIAL
;
1537 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1538 prim
.VertexCountPerInstance
= 3;
1539 prim
.InstanceCount
= params
->num_layers
;
1543 #endif /* BLORP_GENX_EXEC_H */