2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "common/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
32 * This file provides the blorp pipeline setup and execution functionality.
33 * It defines the following function:
36 * blorp_exec(struct blorp_context *blorp, void *batch_data,
37 * const struct blorp_params *params);
39 * It is the job of whoever includes this header to wrap this in something
40 * to get an externally visible symbol.
42 * In order for the blorp_exec function to work, the driver must provide
43 * implementations of the following static helper functions.
47 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
50 blorp_emit_reloc(struct blorp_batch
*batch
,
51 void *location
, struct blorp_address address
, uint32_t delta
);
54 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
59 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
60 struct blorp_address
*addr
);
63 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
64 unsigned state_size
, unsigned state_alignment
,
65 uint32_t *bt_offset
, uint32_t *surface_offsets
,
69 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
72 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
73 struct blorp_address address
, uint32_t delta
);
76 blorp_emit_urb_config(struct blorp_batch
*batch
, unsigned vs_entry_size
);
78 /***** BEGIN blorp_exec implementation ******/
80 #include "genxml/gen_macros.h"
83 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
84 struct blorp_address address
, uint32_t delta
)
86 if (address
.buffer
== NULL
) {
87 return address
.offset
+ delta
;
89 return blorp_emit_reloc(batch
, location
, address
, delta
);
93 #define __gen_address_type struct blorp_address
94 #define __gen_user_data struct blorp_batch
95 #define __gen_combine_address _blorp_combine_address
97 #include "genxml/genX_pack.h"
99 #define _blorp_cmd_length(cmd) cmd ## _length
100 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
101 #define _blorp_cmd_header(cmd) cmd ## _header
102 #define _blorp_cmd_pack(cmd) cmd ## _pack
104 #define blorp_emit(batch, cmd, name) \
105 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
106 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
107 __builtin_expect(_dst != NULL, 1); \
108 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
111 #define blorp_emitn(batch, cmd, n) ({ \
112 uint32_t *_dw = blorp_emit_dwords(batch, n); \
114 struct cmd template = { \
115 _blorp_cmd_header(cmd), \
116 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
118 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
120 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
123 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
125 #define blorp_emit_dynamic(batch, state, name, align, offset) \
126 for (struct state name = STRUCT_ZERO(state), \
127 *_dst = blorp_alloc_dynamic_state(batch, \
128 _blorp_cmd_length(state) * 4, \
130 __builtin_expect(_dst != NULL, 1); \
131 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
132 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
141 * Assign the entire URB to the VS. Even though the VS disabled, URB space
142 * is still needed because the clipper loads the VUE's from the URB. From
143 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
144 * Dword 1.15:0 "VS Number of URB Entries":
145 * This field is always used (even if VS Function Enable is DISABLED).
147 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
148 * safely ignore it because this batch contains only one draw call.
149 * Because of URB corruption caused by allocating a previous GS unit
150 * URB entry to the VS unit, software is required to send a “GS NULL
151 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
152 * plus a dummy DRAW call before any case where VS will be taking over
155 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
156 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
158 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
159 * programmed in order for the programming of this state to be
163 emit_urb_config(struct blorp_batch
*batch
,
164 const struct blorp_params
*params
)
166 /* Once vertex fetcher has written full VUE entries with complete
167 * header the space requirement is as follows per vertex (in bytes):
169 * Header Position Program constants
170 * +--------+------------+-------------------+
171 * | 16 | 16 | n x 16 |
172 * +--------+------------+-------------------+
174 * where 'n' stands for number of varying inputs expressed as vec4s.
176 const unsigned num_varyings
=
177 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
178 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
180 /* The URB size is expressed in units of 64 bytes (512 bits) */
181 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
183 blorp_emit_urb_config(batch
, vs_entry_size
);
187 blorp_emit_vertex_data(struct blorp_batch
*batch
,
188 const struct blorp_params
*params
,
189 struct blorp_address
*addr
,
192 const float vertices
[] = {
193 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
194 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
195 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
198 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
199 memcpy(data
, vertices
, sizeof(vertices
));
200 *size
= sizeof(vertices
);
201 blorp_flush_range(batch
, data
, *size
);
205 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
206 const struct blorp_params
*params
,
207 struct blorp_address
*addr
,
210 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
211 const unsigned max_num_varyings
=
212 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
213 const unsigned num_varyings
=
214 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
216 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
218 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
219 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
220 uint32_t *inputs
= data
;
222 /* Copy in the VS inputs */
223 assert(sizeof(params
->vs_inputs
) == 16);
224 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
227 if (params
->wm_prog_data
) {
228 /* Walk over the attribute slots, determine if the attribute is used by
229 * the program and when necessary copy the values from the input storage
230 * to the vertex data buffer.
232 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
233 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
235 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
239 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
245 blorp_flush_range(batch
, data
, *size
);
249 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
250 const struct blorp_params
*params
)
252 struct GENX(VERTEX_BUFFER_STATE
) vb
[2];
253 memset(vb
, 0, sizeof(vb
));
256 blorp_emit_vertex_data(batch
, params
, &vb
[0].BufferStartingAddress
, &size
);
257 vb
[0].VertexBufferIndex
= 0;
258 vb
[0].BufferPitch
= 3 * sizeof(float);
260 vb
[0].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
263 vb
[0].AddressModifyEnable
= true;
266 vb
[0].BufferSize
= size
;
268 vb
[0].BufferAccessType
= VERTEXDATA
;
269 vb
[0].EndAddress
= vb
[0].BufferStartingAddress
;
270 vb
[0].EndAddress
.offset
+= size
- 1;
273 blorp_emit_input_varying_data(batch
, params
,
274 &vb
[1].BufferStartingAddress
, &size
);
275 vb
[1].VertexBufferIndex
= 1;
276 vb
[1].BufferPitch
= 0;
278 vb
[1].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
281 vb
[1].AddressModifyEnable
= true;
284 vb
[1].BufferSize
= size
;
286 vb
[1].BufferAccessType
= INSTANCEDATA
;
287 vb
[1].EndAddress
= vb
[1].BufferStartingAddress
;
288 vb
[1].EndAddress
.offset
+= size
- 1;
291 const unsigned num_dwords
= 1 + GENX(VERTEX_BUFFER_STATE_length
) * 2;
292 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
296 for (unsigned i
= 0; i
< 2; i
++) {
297 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
298 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
303 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
304 const struct blorp_params
*params
)
306 const unsigned num_varyings
=
307 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
308 const unsigned num_elements
= 2 + num_varyings
;
310 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
311 memset(ve
, 0, num_elements
* sizeof(*ve
));
313 /* Setup VBO for the rectangle primitive..
315 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
316 * vertices. The vertices reside in screen space with DirectX
317 * coordinates (that is, (0, 0) is the upper left corner).
324 * Since the VS is disabled, the clipper loads each VUE directly from
325 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
326 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
327 * dw0: Reserved, MBZ.
328 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
329 * to assign this with primitive instance identifier which will be
330 * used for layered clears. All other renders have only one instance
331 * and therefore the value will be effectively zero.
332 * dw2: Viewport Index. The HiZ op disables viewport mapping and
333 * scissoring, so set the dword to 0.
334 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
335 * so set the dword to 0.
336 * dw4: Vertex Position X.
337 * dw5: Vertex Position Y.
338 * dw6: Vertex Position Z.
339 * dw7: Vertex Position W.
341 * dw8: Flat vertex input 0
342 * dw9: Flat vertex input 1
344 * dwn: Flat vertex input n - 8
346 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
347 * "Vertex URB Entry (VUE) Formats".
349 * Only vertex position X and Y are going to be variable, Z is fixed to
350 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
351 * include the fixed values in the vertex buffer. Vertex fetcher can be
352 * instructed to fill vertex elements with constant values of one and zero
353 * instead of reading them from the buffer.
354 * Flat inputs are program constants that are not interpolated. Moreover
355 * their values will be the same between vertices.
357 * See the vertex element setup below.
359 ve
[0].VertexBufferIndex
= 1;
361 ve
[0].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
362 ve
[0].SourceElementOffset
= 0;
363 ve
[0].Component0Control
= VFCOMP_STORE_SRC
;
365 /* From Gen8 onwards hardware is no more instructed to overwrite components
366 * using an element specifier. Instead one has separate 3DSTATE_VF_SGVS
367 * (System Generated Value Setup) state packet for it.
370 ve
[0].Component1Control
= VFCOMP_STORE_0
;
372 ve
[0].Component1Control
= VFCOMP_STORE_IID
;
374 ve
[0].Component1Control
= VFCOMP_STORE_0
;
376 ve
[0].Component2Control
= VFCOMP_STORE_SRC
;
377 ve
[0].Component3Control
= VFCOMP_STORE_SRC
;
379 ve
[1].VertexBufferIndex
= 0;
381 ve
[1].SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
;
382 ve
[1].SourceElementOffset
= 0;
383 ve
[1].Component0Control
= VFCOMP_STORE_SRC
;
384 ve
[1].Component1Control
= VFCOMP_STORE_SRC
;
385 ve
[1].Component2Control
= VFCOMP_STORE_SRC
;
386 ve
[1].Component3Control
= VFCOMP_STORE_1_FP
;
388 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
389 ve
[i
+ 2].VertexBufferIndex
= 1;
390 ve
[i
+ 2].Valid
= true;
391 ve
[i
+ 2].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
392 ve
[i
+ 2].SourceElementOffset
= 16 + i
* 4 * sizeof(float);
393 ve
[i
+ 2].Component0Control
= VFCOMP_STORE_SRC
;
394 ve
[i
+ 2].Component1Control
= VFCOMP_STORE_SRC
;
395 ve
[i
+ 2].Component2Control
= VFCOMP_STORE_SRC
;
396 ve
[i
+ 2].Component3Control
= VFCOMP_STORE_SRC
;
399 const unsigned num_dwords
=
400 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
401 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
405 for (unsigned i
= 0; i
< num_elements
; i
++) {
406 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
407 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
411 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
412 * primitive instance identifier. This is used for layered clears.
414 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
415 sgvs
.InstanceIDEnable
= true;
416 sgvs
.InstanceIDComponentNumber
= COMP_1
;
417 sgvs
.InstanceIDElementOffset
= 0;
420 for (unsigned i
= 0; i
< num_elements
; i
++) {
421 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
422 vf
.VertexElementIndex
= i
;
423 vf
.InstancingEnable
= false;
427 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
428 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
433 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
435 blorp_emit_viewport_state(struct blorp_batch
*batch
,
436 const struct blorp_params
*params
)
438 uint32_t cc_vp_offset
;
439 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
440 vp
.MinimumDepth
= 0.0;
441 vp
.MaximumDepth
= 1.0;
445 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
446 vsp
.CCViewportPointer
= cc_vp_offset
;
449 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
450 vsp
.CCViewportStateChange
= true;
451 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
459 blorp_emit_sampler_state(struct blorp_batch
*batch
,
460 const struct blorp_params
*params
)
463 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
464 sampler
.MipModeFilter
= MIPFILTER_NONE
;
465 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
466 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
469 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
470 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
471 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
472 sampler
.MaximumAnisotropy
= RATIO21
;
473 sampler
.RAddressMinFilterRoundingEnable
= true;
474 sampler
.RAddressMagFilterRoundingEnable
= true;
475 sampler
.VAddressMinFilterRoundingEnable
= true;
476 sampler
.VAddressMagFilterRoundingEnable
= true;
477 sampler
.UAddressMinFilterRoundingEnable
= true;
478 sampler
.UAddressMagFilterRoundingEnable
= true;
480 sampler
.NonnormalizedCoordinateEnable
= true;
485 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
486 ssp
.PointertoPSSamplerState
= offset
;
489 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
490 ssp
.VSSamplerStateChange
= true;
491 ssp
.GSSamplerStateChange
= true;
492 ssp
.PSSamplerStateChange
= true;
493 ssp
.PointertoPSSamplerState
= offset
;
500 /* What follows is the code for setting up a "pipeline" on Sandy Bridge and
501 * later hardware. This file will be included by i965 for gen4-5 as well, so
502 * this code is guarded by GEN_GEN >= 6.
507 blorp_emit_vs_config(struct blorp_batch
*batch
,
508 const struct blorp_params
*params
)
510 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
512 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
516 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
518 vs
.DispatchGRFStartRegisterForURBData
=
519 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
520 vs
.VertexURBEntryReadLength
=
521 vs_prog_data
->base
.urb_read_length
;
522 vs
.VertexURBEntryReadOffset
= 0;
524 vs
.MaximumNumberofThreads
=
525 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
528 vs
.SIMD8DispatchEnable
=
529 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
536 blorp_emit_sf_config(struct blorp_batch
*batch
,
537 const struct blorp_params
*params
)
539 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
543 * Disable ViewportTransformEnable (dw2.1)
545 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
546 * Primitives Overview":
547 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
548 * use of screen- space coordinates).
550 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
551 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
553 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
554 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
555 * SOLID: Any triangle or rectangle object found to be front-facing
556 * is rendered as a solid object. This setting is required when
557 * (rendering rectangle (RECTLIST) objects.
562 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
564 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
565 raster
.CullMode
= CULLMODE_NONE
;
568 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
569 sbe
.VertexURBEntryReadOffset
= 1;
571 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
572 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
573 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
575 sbe
.NumberofSFOutputAttributes
= 0;
576 sbe
.VertexURBEntryReadLength
= 1;
578 sbe
.ForceVertexURBEntryReadLength
= true;
579 sbe
.ForceVertexURBEntryReadOffset
= true;
582 for (unsigned i
= 0; i
< 32; i
++)
583 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
589 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
590 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
591 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
593 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
594 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
597 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
601 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
602 sbe
.VertexURBEntryReadOffset
= 1;
604 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
605 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
606 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
608 sbe
.NumberofSFOutputAttributes
= 0;
609 sbe
.VertexURBEntryReadLength
= 1;
613 #else /* GEN_GEN <= 6 */
615 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
616 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
617 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
619 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
620 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
622 sf
.VertexURBEntryReadOffset
= 1;
624 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
625 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
626 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
628 sf
.NumberofSFOutputAttributes
= 0;
629 sf
.VertexURBEntryReadLength
= 1;
637 blorp_emit_ps_config(struct blorp_batch
*batch
,
638 const struct blorp_params
*params
)
640 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
642 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
643 * nonzero to prevent the GPU from hanging. While the documentation doesn't
644 * mention this explicitly, it notes that the valid range for the field is
645 * [1,39] = [2,40] threads, which excludes zero.
647 * To be safe (and to minimize extraneous code) we go ahead and fully
648 * configure the WM state whether or not there is a WM program.
653 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
655 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
656 if (params
->src
.enabled
) {
657 ps
.SamplerCount
= 1; /* Up to 4 samplers */
658 ps
.BindingTableEntryCount
= 2;
660 ps
.BindingTableEntryCount
= 1;
664 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
665 prog_data
->base
.dispatch_grf_start_reg
;
666 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
667 prog_data
->dispatch_grf_start_reg_2
;
669 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
670 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
672 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
673 ps
.KernelStartPointer2
=
674 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
677 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
678 * it implicitly scales for different GT levels (which have some # of
681 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
684 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
686 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
688 switch (params
->fast_clear_op
) {
689 case BLORP_FAST_CLEAR_OP_NONE
:
692 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
693 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
695 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
696 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
699 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
700 ps
.RenderTargetResolveEnable
= true;
703 case BLORP_FAST_CLEAR_OP_CLEAR
:
704 ps
.RenderTargetFastClearEnable
= true;
707 unreachable("Invalid fast clear op");
711 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
713 psx
.PixelShaderValid
= true;
714 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
715 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
718 if (params
->src
.enabled
)
719 psx
.PixelShaderKillsPixel
= true;
724 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
725 switch (params
->hiz_op
) {
726 case BLORP_HIZ_OP_DEPTH_CLEAR
:
727 wm
.DepthBufferClear
= true;
729 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
730 wm
.DepthBufferResolveEnable
= true;
732 case BLORP_HIZ_OP_HIZ_RESOLVE
:
733 wm
.HierarchicalDepthBufferResolveEnable
= true;
735 case BLORP_HIZ_OP_NONE
:
738 unreachable("not reached");
742 wm
.ThreadDispatchEnable
= true;
744 if (params
->src
.enabled
)
745 wm
.PixelShaderKillsPixel
= true;
747 if (params
->num_samples
> 1) {
748 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
749 wm
.MultisampleDispatchMode
=
750 (prog_data
&& prog_data
->persample_dispatch
) ?
751 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
753 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
754 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
758 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
759 ps
.MaximumNumberofThreads
=
760 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
767 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
768 prog_data
->base
.dispatch_grf_start_reg
;
769 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
770 prog_data
->dispatch_grf_start_reg_2
;
772 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
773 ps
.KernelStartPointer2
=
774 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
776 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
777 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
779 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
781 /* Gen7 hardware gets angry if we don't enable at least one dispatch
782 * mode, so just enable 16-pixel dispatch if we don't have a program.
784 ps
._16PixelDispatchEnable
= true;
787 if (params
->src
.enabled
)
788 ps
.SamplerCount
= 1; /* Up to 4 samplers */
790 switch (params
->fast_clear_op
) {
791 case BLORP_FAST_CLEAR_OP_NONE
:
793 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
794 ps
.RenderTargetResolveEnable
= true;
796 case BLORP_FAST_CLEAR_OP_CLEAR
:
797 ps
.RenderTargetFastClearEnable
= true;
800 unreachable("Invalid fast clear op");
804 #else /* GEN_GEN <= 6 */
806 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
807 wm
.MaximumNumberofThreads
=
808 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
810 switch (params
->hiz_op
) {
811 case BLORP_HIZ_OP_DEPTH_CLEAR
:
812 wm
.DepthBufferClear
= true;
814 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
815 wm
.DepthBufferResolveEnable
= true;
817 case BLORP_HIZ_OP_HIZ_RESOLVE
:
818 wm
.HierarchicalDepthBufferResolveEnable
= true;
820 case BLORP_HIZ_OP_NONE
:
823 unreachable("not reached");
827 wm
.ThreadDispatchEnable
= true;
829 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
830 prog_data
->base
.dispatch_grf_start_reg
;
831 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
832 prog_data
->dispatch_grf_start_reg_2
;
834 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
835 wm
.KernelStartPointer2
=
836 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
838 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
839 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
841 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
844 if (params
->src
.enabled
) {
845 wm
.SamplerCount
= 1; /* Up to 4 samplers */
846 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
849 if (params
->num_samples
> 1) {
850 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
851 wm
.MultisampleDispatchMode
=
852 (prog_data
&& prog_data
->persample_dispatch
) ?
853 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
855 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
856 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
864 blorp_emit_blend_state(struct blorp_batch
*batch
,
865 const struct blorp_params
*params
)
867 struct GENX(BLEND_STATE
) blend
;
868 memset(&blend
, 0, sizeof(blend
));
871 int size
= GENX(BLEND_STATE_length
) * 4;
872 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
873 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
874 uint32_t *pos
= state
;
876 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
877 pos
+= GENX(BLEND_STATE_length
);
879 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
880 struct GENX(BLEND_STATE_ENTRY
) entry
= {
881 .PreBlendColorClampEnable
= true,
882 .PostBlendColorClampEnable
= true,
883 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
885 .WriteDisableRed
= params
->color_write_disable
[0],
886 .WriteDisableGreen
= params
->color_write_disable
[1],
887 .WriteDisableBlue
= params
->color_write_disable
[2],
888 .WriteDisableAlpha
= params
->color_write_disable
[3],
890 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
891 pos
+= GENX(BLEND_STATE_ENTRY_length
);
894 blorp_flush_range(batch
, state
, size
);
897 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
898 sp
.BlendStatePointer
= offset
;
900 sp
.BlendStatePointerValid
= true;
906 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
907 ps_blend
.HasWriteableRT
= true;
915 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
916 const struct blorp_params
*params
)
919 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
921 cc
.StencilReferenceValue
= params
->stencil_ref
;
926 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
927 sp
.ColorCalcStatePointer
= offset
;
929 sp
.ColorCalcStatePointerValid
= true;
938 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
939 const struct blorp_params
*params
)
942 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
943 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
946 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
949 if (params
->depth
.enabled
) {
950 ds
.DepthBufferWriteEnable
= true;
952 switch (params
->hiz_op
) {
953 case BLORP_HIZ_OP_NONE
:
954 ds
.DepthTestEnable
= true;
955 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
958 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
959 * - 7.5.3.1 Depth Buffer Clear
960 * - 7.5.3.2 Depth Buffer Resolve
961 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
963 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
964 ds
.DepthTestEnable
= true;
965 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
968 case BLORP_HIZ_OP_DEPTH_CLEAR
:
969 case BLORP_HIZ_OP_HIZ_RESOLVE
:
970 ds
.DepthTestEnable
= false;
975 if (params
->stencil
.enabled
) {
976 ds
.StencilBufferWriteEnable
= true;
977 ds
.StencilTestEnable
= true;
978 ds
.DoubleSidedStencilEnable
= false;
980 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
981 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
983 ds
.StencilWriteMask
= params
->stencil_mask
;
985 ds
.StencilReferenceValue
= params
->stencil_ref
;
991 uint32_t *dw
= blorp_emit_dwords(batch
,
992 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
996 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
999 void *state
= blorp_alloc_dynamic_state(batch
,
1000 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1002 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1003 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1007 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1008 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1016 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1017 const struct blorp_params
*params
)
1019 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1020 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1023 /* The PRM says that this bit is valid only for DX9:
1025 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1026 * should not have any effect by setting or not setting this bit.
1028 ms
.PixelPositionOffsetEnable
= false;
1031 switch (params
->num_samples
) {
1033 GEN_SAMPLE_POS_1X(ms
.Sample
);
1036 GEN_SAMPLE_POS_2X(ms
.Sample
);
1039 GEN_SAMPLE_POS_4X(ms
.Sample
);
1042 GEN_SAMPLE_POS_8X(ms
.Sample
);
1048 GEN_SAMPLE_POS_4X(ms
.Sample
);
1050 ms
.PixelLocation
= CENTER
;
1055 blorp_emit_pipeline(struct blorp_batch
*batch
,
1056 const struct blorp_params
*params
)
1058 uint32_t blend_state_offset
= 0;
1059 uint32_t color_calc_state_offset
;
1060 uint32_t depth_stencil_state_offset
;
1062 emit_urb_config(batch
, params
);
1064 if (params
->wm_prog_data
) {
1065 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1067 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1068 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1071 /* 3DSTATE_CC_STATE_POINTERS
1073 * The pointer offsets are relative to
1074 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1076 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1078 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1079 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1080 * one CC_STATE_POINTERS packet so we have to emit that here.
1082 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1083 cc
.BLEND_STATEChange
= true;
1084 cc
.ColorCalcStatePointerValid
= true;
1085 cc
.DEPTH_STENCIL_STATEChange
= true;
1086 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1087 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1088 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1091 (void)blend_state_offset
;
1092 (void)color_calc_state_offset
;
1093 (void)depth_stencil_state_offset
;
1096 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1098 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1099 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1101 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1102 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1104 if (params
->src
.enabled
)
1105 blorp_emit_sampler_state(batch
, params
);
1107 blorp_emit_3dstate_multisample(batch
, params
);
1109 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1110 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1113 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1114 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1116 * [DevSNB] A pipeline flush must be programmed prior to a
1117 * 3DSTATE_VS command that causes the VS Function Enable to
1118 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1119 * command with CS stall bit set and a post sync operation.
1121 * We've already done one at the start of the BLORP operation.
1123 blorp_emit_vs_config(batch
, params
);
1125 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1126 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1127 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1128 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1130 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1132 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1133 clip
.PerspectiveDivideDisable
= true;
1136 blorp_emit_sf_config(batch
, params
);
1137 blorp_emit_ps_config(batch
, params
);
1139 blorp_emit_viewport_state(batch
, params
);
1142 /******** This is the end of the pipeline setup code ********/
1144 #endif /* GEN_GEN >= 6 */
1147 blorp_emit_surface_state(struct blorp_batch
*batch
,
1148 const struct brw_blorp_surface_info
*surface
,
1149 void *state
, uint32_t state_offset
,
1150 bool is_render_target
)
1152 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1153 struct isl_surf surf
= surface
->surf
;
1155 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1156 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1157 assert(surf
.logical_level0_px
.height
== 1);
1158 surf
.dim
= ISL_SURF_DIM_2D
;
1161 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1162 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1163 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1164 aux_usage
= ISL_AUX_USAGE_NONE
;
1166 const uint32_t mocs
=
1167 is_render_target
? batch
->blorp
->mocs
.rb
: batch
->blorp
->mocs
.tex
;
1169 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1170 .surf
= &surf
, .view
= &surface
->view
,
1171 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1172 .mocs
= mocs
, .clear_color
= surface
->clear_color
);
1174 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1177 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1178 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1179 * used to store other information. This should be ok, however, because
1180 * surface buffer addresses are always 4K page alinged.
1182 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1183 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1184 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1185 surface
->aux_addr
, *aux_addr
);
1188 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1192 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1193 const struct brw_blorp_surface_info
*surface
,
1196 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1197 .SurfaceType
= SURFTYPE_NULL
,
1198 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1199 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1200 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1201 .MIPCountLOD
= surface
->view
.base_level
,
1202 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1203 .Depth
= surface
->view
.array_len
- 1,
1204 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1206 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1210 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1216 .TiledSurface
= true,
1220 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1222 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1226 blorp_emit_surface_states(struct blorp_batch
*batch
,
1227 const struct blorp_params
*params
)
1229 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1230 uint32_t bind_offset
, surface_offsets
[2];
1231 void *surface_maps
[2];
1233 if (params
->use_pre_baked_binding_table
) {
1234 bind_offset
= params
->pre_baked_binding_table_offset
;
1236 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1237 blorp_alloc_binding_table(batch
, num_surfaces
,
1238 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1239 &bind_offset
, surface_offsets
, surface_maps
);
1241 if (params
->dst
.enabled
) {
1242 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1243 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1244 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1247 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1248 const struct brw_blorp_surface_info
*surface
=
1249 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1250 blorp_emit_null_surface_state(batch
, surface
,
1251 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1254 if (params
->src
.enabled
) {
1255 blorp_emit_surface_state(batch
, ¶ms
->src
,
1256 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1257 surface_offsets
[BLORP_TEXTURE_BT_INDEX
], false);
1262 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1263 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1264 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1265 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1267 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1268 bt
.PointertoPSBindingTable
= bind_offset
;
1271 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1272 bt
.PSBindingTableChange
= true;
1273 bt
.PointertoPSBindingTable
= bind_offset
;
1276 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1277 bt
.PointertoPSBindingTable
= bind_offset
;
1283 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
1284 const struct blorp_params
*params
)
1286 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1288 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
1292 struct isl_depth_stencil_hiz_emit_info info
= {
1294 .mocs
= 1, /* GEN7_MOCS_L3 */
1300 if (params
->depth
.enabled
) {
1301 info
.view
= ¶ms
->depth
.view
;
1302 } else if (params
->stencil
.enabled
) {
1303 info
.view
= ¶ms
->stencil
.view
;
1306 if (params
->depth
.enabled
) {
1307 info
.depth_surf
= ¶ms
->depth
.surf
;
1309 info
.depth_address
=
1310 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
1311 params
->depth
.addr
, 0);
1313 info
.hiz_usage
= params
->depth
.aux_usage
;
1314 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
1315 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
1318 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
1319 params
->depth
.aux_addr
, 0);
1321 info
.depth_clear_value
= params
->depth
.clear_color
.u32
[0];
1325 if (params
->stencil
.enabled
) {
1326 info
.stencil_surf
= ¶ms
->stencil
.surf
;
1328 info
.stencil_address
=
1329 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
1330 params
->stencil
.addr
, 0);
1333 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
1337 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1338 * depth/stencil buffer extents are ignored to handle APIs which perform
1339 * clearing operations without such information.
1342 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1343 const struct blorp_params
*params
)
1345 /* We should be performing an operation on a depth or stencil buffer.
1347 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1349 /* The stencil buffer should only be enabled if a fast clear operation is
1352 if (params
->stencil
.enabled
)
1353 assert(params
->hiz_op
== BLORP_HIZ_OP_DEPTH_CLEAR
);
1355 /* If we can't alter the depth stencil config and multiple layers are
1356 * involved, the HiZ op will fail. This is because the op requires that a
1357 * new config is emitted for each additional layer.
1359 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1360 assert(params
->num_layers
<= 1);
1362 blorp_emit_depth_stencil_config(batch
, params
);
1365 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1366 switch (params
->hiz_op
) {
1367 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1368 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1369 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1370 hzp
.StencilClearValue
= params
->stencil_ref
;
1372 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1373 hzp
.DepthBufferResolveEnable
= true;
1375 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1376 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1378 case BLORP_HIZ_OP_NONE
:
1379 unreachable("Invalid HIZ op");
1382 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1383 hzp
.SampleMask
= 0xFFFF;
1385 /* Due to a hardware issue, this bit MBZ */
1386 assert(hzp
.ScissorRectangleEnable
== false);
1388 /* Contrary to the HW docs both fields are inclusive */
1389 hzp
.ClearRectangleXMin
= params
->x0
;
1390 hzp
.ClearRectangleYMin
= params
->y0
;
1392 /* Contrary to the HW docs both fields are exclusive */
1393 hzp
.ClearRectangleXMax
= params
->x1
;
1394 hzp
.ClearRectangleYMax
= params
->y1
;
1397 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1398 * to “Write Immediate Data” enabled.
1400 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1401 pc
.PostSyncOperation
= WriteImmediateData
;
1404 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1406 /* Perform depth clear specific flushing */
1407 if (params
->hiz_op
== BLORP_HIZ_OP_DEPTH_CLEAR
&& params
->depth
.enabled
) {
1408 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1409 pc
.DepthStallEnable
= true;
1410 pc
.DepthCacheFlushEnable
= true;
1417 * \brief Execute a blit or render pass operation.
1419 * To execute the operation, this function manually constructs and emits a
1420 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1421 * constructing and after emitting the batch.
1423 * This function alters no GL state.
1426 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1429 if (params
->hiz_op
!= BLORP_HIZ_OP_NONE
) {
1430 blorp_emit_gen8_hiz_op(batch
, params
);
1435 blorp_emit_vertex_buffers(batch
, params
);
1436 blorp_emit_vertex_elements(batch
, params
);
1438 blorp_emit_pipeline(batch
, params
);
1440 blorp_emit_surface_states(batch
, params
);
1442 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1443 blorp_emit_depth_stencil_config(batch
, params
);
1445 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1446 prim
.VertexAccessType
= SEQUENTIAL
;
1447 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1448 prim
.VertexCountPerInstance
= 3;
1449 prim
.InstanceCount
= params
->num_layers
;
1453 #endif /* BLORP_GENX_EXEC_H */