2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "common/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "genxml/gen_macros.h"
33 * This file provides the blorp pipeline setup and execution functionality.
34 * It defines the following function:
37 * blorp_exec(struct blorp_context *blorp, void *batch_data,
38 * const struct blorp_params *params);
40 * It is the job of whoever includes this header to wrap this in something
41 * to get an externally visible symbol.
43 * In order for the blorp_exec function to work, the driver must provide
44 * implementations of the following static helper functions.
48 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
51 blorp_emit_reloc(struct blorp_batch
*batch
,
52 void *location
, struct blorp_address address
, uint32_t delta
);
55 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
60 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
61 struct blorp_address
*addr
);
64 static struct blorp_address
65 blorp_get_workaround_page(struct blorp_batch
*batch
);
69 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
70 unsigned state_size
, unsigned state_alignment
,
71 uint32_t *bt_offset
, uint32_t *surface_offsets
,
75 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
78 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
79 struct blorp_address address
, uint32_t delta
);
82 blorp_emit_urb_config(struct blorp_batch
*batch
,
83 unsigned vs_entry_size
, unsigned sf_entry_size
);
86 blorp_emit_pipeline(struct blorp_batch
*batch
,
87 const struct blorp_params
*params
);
89 /***** BEGIN blorp_exec implementation ******/
92 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
93 struct blorp_address address
, uint32_t delta
)
95 if (address
.buffer
== NULL
) {
96 return address
.offset
+ delta
;
98 return blorp_emit_reloc(batch
, location
, address
, delta
);
102 #define __gen_address_type struct blorp_address
103 #define __gen_user_data struct blorp_batch
104 #define __gen_combine_address _blorp_combine_address
106 #include "genxml/genX_pack.h"
108 #define _blorp_cmd_length(cmd) cmd ## _length
109 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
110 #define _blorp_cmd_header(cmd) cmd ## _header
111 #define _blorp_cmd_pack(cmd) cmd ## _pack
113 #define blorp_emit(batch, cmd, name) \
114 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
115 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
116 __builtin_expect(_dst != NULL, 1); \
117 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
120 #define blorp_emitn(batch, cmd, n) ({ \
121 uint32_t *_dw = blorp_emit_dwords(batch, n); \
123 struct cmd template = { \
124 _blorp_cmd_header(cmd), \
125 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
127 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
129 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
132 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
134 #define blorp_emit_dynamic(batch, state, name, align, offset) \
135 for (struct state name = STRUCT_ZERO(state), \
136 *_dst = blorp_alloc_dynamic_state(batch, \
137 _blorp_cmd_length(state) * 4, \
139 __builtin_expect(_dst != NULL, 1); \
140 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
141 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
150 * Assign the entire URB to the VS. Even though the VS disabled, URB space
151 * is still needed because the clipper loads the VUE's from the URB. From
152 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
153 * Dword 1.15:0 "VS Number of URB Entries":
154 * This field is always used (even if VS Function Enable is DISABLED).
156 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
157 * safely ignore it because this batch contains only one draw call.
158 * Because of URB corruption caused by allocating a previous GS unit
159 * URB entry to the VS unit, software is required to send a “GS NULL
160 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
161 * plus a dummy DRAW call before any case where VS will be taking over
164 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
165 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
167 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
168 * programmed in order for the programming of this state to be
172 emit_urb_config(struct blorp_batch
*batch
,
173 const struct blorp_params
*params
)
175 /* Once vertex fetcher has written full VUE entries with complete
176 * header the space requirement is as follows per vertex (in bytes):
178 * Header Position Program constants
179 * +--------+------------+-------------------+
180 * | 16 | 16 | n x 16 |
181 * +--------+------------+-------------------+
183 * where 'n' stands for number of varying inputs expressed as vec4s.
185 const unsigned num_varyings
=
186 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
187 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
189 /* The URB size is expressed in units of 64 bytes (512 bits) */
190 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
192 const unsigned sf_entry_size
=
193 params
->sf_prog_data
? params
->sf_prog_data
->urb_entry_size
: 0;
195 blorp_emit_urb_config(batch
, vs_entry_size
, sf_entry_size
);
199 blorp_emit_vertex_data(struct blorp_batch
*batch
,
200 const struct blorp_params
*params
,
201 struct blorp_address
*addr
,
204 const float vertices
[] = {
205 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
206 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
207 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
210 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
211 memcpy(data
, vertices
, sizeof(vertices
));
212 *size
= sizeof(vertices
);
213 blorp_flush_range(batch
, data
, *size
);
217 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
218 const struct blorp_params
*params
,
219 struct blorp_address
*addr
,
222 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
223 const unsigned max_num_varyings
=
224 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
225 const unsigned num_varyings
=
226 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
228 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
230 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
231 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
232 uint32_t *inputs
= data
;
234 /* Copy in the VS inputs */
235 assert(sizeof(params
->vs_inputs
) == 16);
236 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
239 if (params
->wm_prog_data
) {
240 /* Walk over the attribute slots, determine if the attribute is used by
241 * the program and when necessary copy the values from the input storage
242 * to the vertex data buffer.
244 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
245 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
247 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
251 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
257 blorp_flush_range(batch
, data
, *size
);
261 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
262 const struct blorp_params
*params
)
264 struct GENX(VERTEX_BUFFER_STATE
) vb
[2];
265 memset(vb
, 0, sizeof(vb
));
268 blorp_emit_vertex_data(batch
, params
, &vb
[0].BufferStartingAddress
, &size
);
269 vb
[0].VertexBufferIndex
= 0;
270 vb
[0].BufferPitch
= 3 * sizeof(float);
272 vb
[0].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
275 vb
[0].AddressModifyEnable
= true;
278 vb
[0].BufferSize
= size
;
280 vb
[0].BufferAccessType
= VERTEXDATA
;
281 vb
[0].EndAddress
= vb
[0].BufferStartingAddress
;
282 vb
[0].EndAddress
.offset
+= size
- 1;
284 vb
[0].BufferAccessType
= VERTEXDATA
;
288 blorp_emit_input_varying_data(batch
, params
,
289 &vb
[1].BufferStartingAddress
, &size
);
290 vb
[1].VertexBufferIndex
= 1;
291 vb
[1].BufferPitch
= 0;
293 vb
[1].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
296 vb
[1].AddressModifyEnable
= true;
299 vb
[1].BufferSize
= size
;
301 vb
[1].BufferAccessType
= INSTANCEDATA
;
302 vb
[1].EndAddress
= vb
[1].BufferStartingAddress
;
303 vb
[1].EndAddress
.offset
+= size
- 1;
305 vb
[1].BufferAccessType
= INSTANCEDATA
;
309 const unsigned num_dwords
= 1 + GENX(VERTEX_BUFFER_STATE_length
) * 2;
310 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
314 for (unsigned i
= 0; i
< 2; i
++) {
315 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
316 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
321 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
322 const struct blorp_params
*params
)
324 const unsigned num_varyings
=
325 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
326 bool need_ndc
= batch
->blorp
->compiler
->devinfo
->gen
<= 5;
327 const unsigned num_elements
= 2 + need_ndc
+ num_varyings
;
329 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
330 memset(ve
, 0, num_elements
* sizeof(*ve
));
332 /* Setup VBO for the rectangle primitive..
334 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
335 * vertices. The vertices reside in screen space with DirectX
336 * coordinates (that is, (0, 0) is the upper left corner).
343 * Since the VS is disabled, the clipper loads each VUE directly from
344 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
345 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
346 * dw0: Reserved, MBZ.
347 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
348 * to assign this with primitive instance identifier which will be
349 * used for layered clears. All other renders have only one instance
350 * and therefore the value will be effectively zero.
351 * dw2: Viewport Index. The HiZ op disables viewport mapping and
352 * scissoring, so set the dword to 0.
353 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
354 * so set the dword to 0.
355 * dw4: Vertex Position X.
356 * dw5: Vertex Position Y.
357 * dw6: Vertex Position Z.
358 * dw7: Vertex Position W.
360 * dw8: Flat vertex input 0
361 * dw9: Flat vertex input 1
363 * dwn: Flat vertex input n - 8
365 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
366 * "Vertex URB Entry (VUE) Formats".
368 * Only vertex position X and Y are going to be variable, Z is fixed to
369 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
370 * include the fixed values in the vertex buffer. Vertex fetcher can be
371 * instructed to fill vertex elements with constant values of one and zero
372 * instead of reading them from the buffer.
373 * Flat inputs are program constants that are not interpolated. Moreover
374 * their values will be the same between vertices.
376 * See the vertex element setup below.
380 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
381 .VertexBufferIndex
= 1,
383 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
384 .SourceElementOffset
= 0,
385 .Component0Control
= VFCOMP_STORE_SRC
,
387 /* From Gen8 onwards hardware is no more instructed to overwrite
388 * components using an element specifier. Instead one has separate
389 * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it.
392 .Component1Control
= VFCOMP_STORE_0
,
394 .Component1Control
= VFCOMP_STORE_IID
,
396 .Component1Control
= VFCOMP_STORE_0
,
398 .Component2Control
= VFCOMP_STORE_0
,
399 .Component3Control
= VFCOMP_STORE_0
,
401 .DestinationElementOffset
= slot
* 4,
407 /* On Iron Lake and earlier, a native device coordinates version of the
408 * position goes right after the normal VUE header and before position.
409 * Since w == 1 for all of our coordinates, this is just a copy of the
412 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
413 .VertexBufferIndex
= 0,
415 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
416 .SourceElementOffset
= 0,
417 .Component0Control
= VFCOMP_STORE_SRC
,
418 .Component1Control
= VFCOMP_STORE_SRC
,
419 .Component2Control
= VFCOMP_STORE_SRC
,
420 .Component3Control
= VFCOMP_STORE_1_FP
,
421 .DestinationElementOffset
= slot
* 4,
426 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
427 .VertexBufferIndex
= 0,
429 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
430 .SourceElementOffset
= 0,
431 .Component0Control
= VFCOMP_STORE_SRC
,
432 .Component1Control
= VFCOMP_STORE_SRC
,
433 .Component2Control
= VFCOMP_STORE_SRC
,
434 .Component3Control
= VFCOMP_STORE_1_FP
,
436 .DestinationElementOffset
= slot
* 4,
441 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
442 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
443 .VertexBufferIndex
= 1,
445 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
446 .SourceElementOffset
= 16 + i
* 4 * sizeof(float),
447 .Component0Control
= VFCOMP_STORE_SRC
,
448 .Component1Control
= VFCOMP_STORE_SRC
,
449 .Component2Control
= VFCOMP_STORE_SRC
,
450 .Component3Control
= VFCOMP_STORE_SRC
,
452 .DestinationElementOffset
= slot
* 4,
458 const unsigned num_dwords
=
459 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
460 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
464 for (unsigned i
= 0; i
< num_elements
; i
++) {
465 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
466 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
470 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
471 * primitive instance identifier. This is used for layered clears.
473 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
474 sgvs
.InstanceIDEnable
= true;
475 sgvs
.InstanceIDComponentNumber
= COMP_1
;
476 sgvs
.InstanceIDElementOffset
= 0;
479 for (unsigned i
= 0; i
< num_elements
; i
++) {
480 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
481 vf
.VertexElementIndex
= i
;
482 vf
.InstancingEnable
= false;
486 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
487 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
492 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
494 blorp_emit_cc_viewport(struct blorp_batch
*batch
,
495 const struct blorp_params
*params
)
497 uint32_t cc_vp_offset
;
498 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
499 vp
.MinimumDepth
= 0.0;
500 vp
.MaximumDepth
= 1.0;
504 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
505 vsp
.CCViewportPointer
= cc_vp_offset
;
508 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
509 vsp
.CCViewportStateChange
= true;
510 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
518 blorp_emit_sampler_state(struct blorp_batch
*batch
,
519 const struct blorp_params
*params
)
522 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
523 sampler
.MipModeFilter
= MIPFILTER_NONE
;
524 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
525 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
528 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
529 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
530 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
531 sampler
.MaximumAnisotropy
= RATIO21
;
532 sampler
.RAddressMinFilterRoundingEnable
= true;
533 sampler
.RAddressMagFilterRoundingEnable
= true;
534 sampler
.VAddressMinFilterRoundingEnable
= true;
535 sampler
.VAddressMagFilterRoundingEnable
= true;
536 sampler
.UAddressMinFilterRoundingEnable
= true;
537 sampler
.UAddressMagFilterRoundingEnable
= true;
539 sampler
.NonnormalizedCoordinateEnable
= true;
544 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
545 ssp
.PointertoPSSamplerState
= offset
;
548 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
549 ssp
.VSSamplerStateChange
= true;
550 ssp
.GSSamplerStateChange
= true;
551 ssp
.PSSamplerStateChange
= true;
552 ssp
.PointertoPSSamplerState
= offset
;
559 /* What follows is the code for setting up a "pipeline" on Sandy Bridge and
560 * later hardware. This file will be included by i965 for gen4-5 as well, so
561 * this code is guarded by GEN_GEN >= 6.
566 blorp_emit_vs_config(struct blorp_batch
*batch
,
567 const struct blorp_params
*params
)
569 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
571 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
575 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
577 vs
.DispatchGRFStartRegisterForURBData
=
578 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
579 vs
.VertexURBEntryReadLength
=
580 vs_prog_data
->base
.urb_read_length
;
581 vs
.VertexURBEntryReadOffset
= 0;
583 vs
.MaximumNumberofThreads
=
584 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
587 vs
.SIMD8DispatchEnable
=
588 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
595 blorp_emit_sf_config(struct blorp_batch
*batch
,
596 const struct blorp_params
*params
)
598 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
602 * Disable ViewportTransformEnable (dw2.1)
604 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
605 * Primitives Overview":
606 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
607 * use of screen- space coordinates).
609 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
610 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
612 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
613 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
614 * SOLID: Any triangle or rectangle object found to be front-facing
615 * is rendered as a solid object. This setting is required when
616 * (rendering rectangle (RECTLIST) objects.
621 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
623 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
624 raster
.CullMode
= CULLMODE_NONE
;
627 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
628 sbe
.VertexURBEntryReadOffset
= 1;
630 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
631 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
632 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
634 sbe
.NumberofSFOutputAttributes
= 0;
635 sbe
.VertexURBEntryReadLength
= 1;
637 sbe
.ForceVertexURBEntryReadLength
= true;
638 sbe
.ForceVertexURBEntryReadOffset
= true;
641 for (unsigned i
= 0; i
< 32; i
++)
642 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
648 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
649 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
650 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
652 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
653 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
656 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
660 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
661 sbe
.VertexURBEntryReadOffset
= 1;
663 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
664 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
665 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
667 sbe
.NumberofSFOutputAttributes
= 0;
668 sbe
.VertexURBEntryReadLength
= 1;
672 #else /* GEN_GEN <= 6 */
674 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
675 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
676 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
678 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
679 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
681 sf
.VertexURBEntryReadOffset
= 1;
683 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
684 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
685 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
687 sf
.NumberofSFOutputAttributes
= 0;
688 sf
.VertexURBEntryReadLength
= 1;
696 blorp_emit_ps_config(struct blorp_batch
*batch
,
697 const struct blorp_params
*params
)
699 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
701 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
702 * nonzero to prevent the GPU from hanging. While the documentation doesn't
703 * mention this explicitly, it notes that the valid range for the field is
704 * [1,39] = [2,40] threads, which excludes zero.
706 * To be safe (and to minimize extraneous code) we go ahead and fully
707 * configure the WM state whether or not there is a WM program.
712 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
714 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
715 if (params
->src
.enabled
) {
716 ps
.SamplerCount
= 1; /* Up to 4 samplers */
717 ps
.BindingTableEntryCount
= 2;
719 ps
.BindingTableEntryCount
= 1;
723 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
724 prog_data
->base
.dispatch_grf_start_reg
;
725 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
726 prog_data
->dispatch_grf_start_reg_2
;
728 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
729 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
731 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
732 ps
.KernelStartPointer2
=
733 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
736 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
737 * it implicitly scales for different GT levels (which have some # of
740 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
743 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
745 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
747 switch (params
->fast_clear_op
) {
748 case BLORP_FAST_CLEAR_OP_NONE
:
751 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
752 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
754 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
755 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
758 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
759 ps
.RenderTargetResolveEnable
= true;
762 case BLORP_FAST_CLEAR_OP_CLEAR
:
763 ps
.RenderTargetFastClearEnable
= true;
766 unreachable("Invalid fast clear op");
770 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
772 psx
.PixelShaderValid
= true;
773 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
774 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
777 if (params
->src
.enabled
)
778 psx
.PixelShaderKillsPixel
= true;
783 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
784 switch (params
->hiz_op
) {
785 case BLORP_HIZ_OP_DEPTH_CLEAR
:
786 wm
.DepthBufferClear
= true;
788 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
789 wm
.DepthBufferResolveEnable
= true;
791 case BLORP_HIZ_OP_HIZ_RESOLVE
:
792 wm
.HierarchicalDepthBufferResolveEnable
= true;
794 case BLORP_HIZ_OP_NONE
:
797 unreachable("not reached");
801 wm
.ThreadDispatchEnable
= true;
803 if (params
->src
.enabled
)
804 wm
.PixelShaderKillsPixel
= true;
806 if (params
->num_samples
> 1) {
807 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
808 wm
.MultisampleDispatchMode
=
809 (prog_data
&& prog_data
->persample_dispatch
) ?
810 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
812 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
813 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
817 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
818 ps
.MaximumNumberofThreads
=
819 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
826 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
827 prog_data
->base
.dispatch_grf_start_reg
;
828 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
829 prog_data
->dispatch_grf_start_reg_2
;
831 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
832 ps
.KernelStartPointer2
=
833 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
835 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
836 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
838 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
840 /* Gen7 hardware gets angry if we don't enable at least one dispatch
841 * mode, so just enable 16-pixel dispatch if we don't have a program.
843 ps
._16PixelDispatchEnable
= true;
846 if (params
->src
.enabled
)
847 ps
.SamplerCount
= 1; /* Up to 4 samplers */
849 switch (params
->fast_clear_op
) {
850 case BLORP_FAST_CLEAR_OP_NONE
:
852 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
853 ps
.RenderTargetResolveEnable
= true;
855 case BLORP_FAST_CLEAR_OP_CLEAR
:
856 ps
.RenderTargetFastClearEnable
= true;
859 unreachable("Invalid fast clear op");
863 #else /* GEN_GEN <= 6 */
865 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
866 wm
.MaximumNumberofThreads
=
867 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
869 switch (params
->hiz_op
) {
870 case BLORP_HIZ_OP_DEPTH_CLEAR
:
871 wm
.DepthBufferClear
= true;
873 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
874 wm
.DepthBufferResolveEnable
= true;
876 case BLORP_HIZ_OP_HIZ_RESOLVE
:
877 wm
.HierarchicalDepthBufferResolveEnable
= true;
879 case BLORP_HIZ_OP_NONE
:
882 unreachable("not reached");
886 wm
.ThreadDispatchEnable
= true;
888 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
889 prog_data
->base
.dispatch_grf_start_reg
;
890 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
891 prog_data
->dispatch_grf_start_reg_2
;
893 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
894 wm
.KernelStartPointer2
=
895 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
897 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
898 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
900 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
903 if (params
->src
.enabled
) {
904 wm
.SamplerCount
= 1; /* Up to 4 samplers */
905 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
908 if (params
->num_samples
> 1) {
909 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
910 wm
.MultisampleDispatchMode
=
911 (prog_data
&& prog_data
->persample_dispatch
) ?
912 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
914 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
915 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
923 blorp_emit_blend_state(struct blorp_batch
*batch
,
924 const struct blorp_params
*params
)
926 struct GENX(BLEND_STATE
) blend
;
927 memset(&blend
, 0, sizeof(blend
));
930 int size
= GENX(BLEND_STATE_length
) * 4;
931 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
932 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
933 uint32_t *pos
= state
;
935 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
936 pos
+= GENX(BLEND_STATE_length
);
938 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
939 struct GENX(BLEND_STATE_ENTRY
) entry
= {
940 .PreBlendColorClampEnable
= true,
941 .PostBlendColorClampEnable
= true,
942 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
944 .WriteDisableRed
= params
->color_write_disable
[0],
945 .WriteDisableGreen
= params
->color_write_disable
[1],
946 .WriteDisableBlue
= params
->color_write_disable
[2],
947 .WriteDisableAlpha
= params
->color_write_disable
[3],
949 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
950 pos
+= GENX(BLEND_STATE_ENTRY_length
);
953 blorp_flush_range(batch
, state
, size
);
956 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
957 sp
.BlendStatePointer
= offset
;
959 sp
.BlendStatePointerValid
= true;
965 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
966 ps_blend
.HasWriteableRT
= true;
974 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
975 const struct blorp_params
*params
)
978 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
980 cc
.StencilReferenceValue
= params
->stencil_ref
;
985 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
986 sp
.ColorCalcStatePointer
= offset
;
988 sp
.ColorCalcStatePointerValid
= true;
997 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
998 const struct blorp_params
*params
)
1001 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
1002 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
1005 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
1008 if (params
->depth
.enabled
) {
1009 ds
.DepthBufferWriteEnable
= true;
1011 switch (params
->hiz_op
) {
1012 case BLORP_HIZ_OP_NONE
:
1013 ds
.DepthTestEnable
= true;
1014 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
1017 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
1018 * - 7.5.3.1 Depth Buffer Clear
1019 * - 7.5.3.2 Depth Buffer Resolve
1020 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1022 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1023 ds
.DepthTestEnable
= true;
1024 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
1027 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1028 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1029 ds
.DepthTestEnable
= false;
1034 if (params
->stencil
.enabled
) {
1035 ds
.StencilBufferWriteEnable
= true;
1036 ds
.StencilTestEnable
= true;
1037 ds
.DoubleSidedStencilEnable
= false;
1039 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1040 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1042 ds
.StencilWriteMask
= params
->stencil_mask
;
1044 ds
.StencilReferenceValue
= params
->stencil_ref
;
1049 uint32_t offset
= 0;
1050 uint32_t *dw
= blorp_emit_dwords(batch
,
1051 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1055 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1058 void *state
= blorp_alloc_dynamic_state(batch
,
1059 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1061 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1062 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1066 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1067 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1075 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1076 const struct blorp_params
*params
)
1078 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1079 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1082 /* The PRM says that this bit is valid only for DX9:
1084 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1085 * should not have any effect by setting or not setting this bit.
1087 ms
.PixelPositionOffsetEnable
= false;
1090 switch (params
->num_samples
) {
1092 GEN_SAMPLE_POS_1X(ms
.Sample
);
1095 GEN_SAMPLE_POS_2X(ms
.Sample
);
1098 GEN_SAMPLE_POS_4X(ms
.Sample
);
1101 GEN_SAMPLE_POS_8X(ms
.Sample
);
1107 GEN_SAMPLE_POS_4X(ms
.Sample
);
1109 ms
.PixelLocation
= CENTER
;
1114 blorp_emit_pipeline(struct blorp_batch
*batch
,
1115 const struct blorp_params
*params
)
1117 uint32_t blend_state_offset
= 0;
1118 uint32_t color_calc_state_offset
;
1119 uint32_t depth_stencil_state_offset
;
1121 emit_urb_config(batch
, params
);
1123 if (params
->wm_prog_data
) {
1124 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1126 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1127 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1130 /* 3DSTATE_CC_STATE_POINTERS
1132 * The pointer offsets are relative to
1133 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1135 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1137 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1138 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1139 * one CC_STATE_POINTERS packet so we have to emit that here.
1141 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1142 cc
.BLEND_STATEChange
= true;
1143 cc
.ColorCalcStatePointerValid
= true;
1144 cc
.DEPTH_STENCIL_STATEChange
= true;
1145 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1146 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1147 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1150 (void)blend_state_offset
;
1151 (void)color_calc_state_offset
;
1152 (void)depth_stencil_state_offset
;
1155 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1157 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1158 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1160 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1161 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1163 if (params
->src
.enabled
)
1164 blorp_emit_sampler_state(batch
, params
);
1166 blorp_emit_3dstate_multisample(batch
, params
);
1168 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1169 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1172 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1173 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1175 * [DevSNB] A pipeline flush must be programmed prior to a
1176 * 3DSTATE_VS command that causes the VS Function Enable to
1177 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1178 * command with CS stall bit set and a post sync operation.
1180 * We've already done one at the start of the BLORP operation.
1182 blorp_emit_vs_config(batch
, params
);
1184 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1185 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1186 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1187 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1189 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1191 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1192 clip
.PerspectiveDivideDisable
= true;
1195 blorp_emit_sf_config(batch
, params
);
1196 blorp_emit_ps_config(batch
, params
);
1198 blorp_emit_cc_viewport(batch
, params
);
1201 /******** This is the end of the pipeline setup code ********/
1203 #endif /* GEN_GEN >= 6 */
1206 blorp_emit_surface_state(struct blorp_batch
*batch
,
1207 const struct brw_blorp_surface_info
*surface
,
1208 void *state
, uint32_t state_offset
,
1209 const bool color_write_disables
[4],
1210 bool is_render_target
)
1212 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1213 struct isl_surf surf
= surface
->surf
;
1215 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1216 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1217 assert(surf
.logical_level0_px
.height
== 1);
1218 surf
.dim
= ISL_SURF_DIM_2D
;
1221 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1222 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1223 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1224 aux_usage
= ISL_AUX_USAGE_NONE
;
1226 isl_channel_mask_t write_disable_mask
= 0;
1227 if (is_render_target
&& GEN_GEN
<= 5) {
1228 if (color_write_disables
[0])
1229 write_disable_mask
|= ISL_CHANNEL_RED_BIT
;
1230 if (color_write_disables
[1])
1231 write_disable_mask
|= ISL_CHANNEL_GREEN_BIT
;
1232 if (color_write_disables
[2])
1233 write_disable_mask
|= ISL_CHANNEL_BLUE_BIT
;
1234 if (color_write_disables
[3])
1235 write_disable_mask
|= ISL_CHANNEL_ALPHA_BIT
;
1238 const uint32_t mocs
=
1239 is_render_target
? batch
->blorp
->mocs
.rb
: batch
->blorp
->mocs
.tex
;
1241 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1242 .surf
= &surf
, .view
= &surface
->view
,
1243 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1244 .mocs
= mocs
, .clear_color
= surface
->clear_color
,
1245 .write_disables
= write_disable_mask
);
1247 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1250 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1251 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1252 * used to store other information. This should be ok, however, because
1253 * surface buffer addresses are always 4K page alinged.
1255 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1256 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1257 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1258 surface
->aux_addr
, *aux_addr
);
1261 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1265 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1266 const struct brw_blorp_surface_info
*surface
,
1269 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1270 .SurfaceType
= SURFTYPE_NULL
,
1271 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1272 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1273 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1274 .MIPCountLOD
= surface
->view
.base_level
,
1275 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1276 .Depth
= surface
->view
.array_len
- 1,
1277 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1279 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1283 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1289 .TiledSurface
= true,
1293 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1295 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1299 blorp_emit_surface_states(struct blorp_batch
*batch
,
1300 const struct blorp_params
*params
)
1302 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1303 uint32_t bind_offset
, surface_offsets
[2];
1304 void *surface_maps
[2];
1306 if (params
->use_pre_baked_binding_table
) {
1307 bind_offset
= params
->pre_baked_binding_table_offset
;
1309 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1310 blorp_alloc_binding_table(batch
, num_surfaces
,
1311 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1312 &bind_offset
, surface_offsets
, surface_maps
);
1314 if (params
->dst
.enabled
) {
1315 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1316 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1317 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1318 params
->color_write_disable
, true);
1320 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1321 const struct brw_blorp_surface_info
*surface
=
1322 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1323 blorp_emit_null_surface_state(batch
, surface
,
1324 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1327 if (params
->src
.enabled
) {
1328 blorp_emit_surface_state(batch
, ¶ms
->src
,
1329 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1330 surface_offsets
[BLORP_TEXTURE_BT_INDEX
],
1336 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1337 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1338 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1339 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1341 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1342 bt
.PointertoPSBindingTable
= bind_offset
;
1345 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1346 bt
.PSBindingTableChange
= true;
1347 bt
.PointertoPSBindingTable
= bind_offset
;
1350 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1351 bt
.PointertoPSBindingTable
= bind_offset
;
1357 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
1358 const struct blorp_params
*params
)
1360 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1362 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
1366 struct isl_depth_stencil_hiz_emit_info info
= {
1368 .mocs
= 1, /* GEN7_MOCS_L3 */
1374 if (params
->depth
.enabled
) {
1375 info
.view
= ¶ms
->depth
.view
;
1376 } else if (params
->stencil
.enabled
) {
1377 info
.view
= ¶ms
->stencil
.view
;
1380 if (params
->depth
.enabled
) {
1381 info
.depth_surf
= ¶ms
->depth
.surf
;
1383 info
.depth_address
=
1384 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
1385 params
->depth
.addr
, 0);
1387 info
.hiz_usage
= params
->depth
.aux_usage
;
1388 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
1389 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
1391 struct blorp_address hiz_address
= params
->depth
.aux_addr
;
1393 /* Sandy bridge hardware does not technically support mipmapped HiZ.
1394 * However, we have a special layout that allows us to make it work
1395 * anyway by manually offsetting to the specified miplevel.
1397 assert(info
.hiz_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1399 isl_surf_get_image_offset_B_tile_sa(info
.hiz_surf
,
1400 info
.view
->base_level
, 0, 0,
1401 &offset_B
, NULL
, NULL
);
1402 hiz_address
.offset
+= offset_B
;
1406 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
1409 info
.depth_clear_value
= params
->depth
.clear_color
.f32
[0];
1413 if (params
->stencil
.enabled
) {
1414 info
.stencil_surf
= ¶ms
->stencil
.surf
;
1416 struct blorp_address stencil_address
= params
->stencil
.addr
;
1418 /* Sandy bridge hardware does not technically support mipmapped stencil.
1419 * However, we have a special layout that allows us to make it work
1420 * anyway by manually offsetting to the specified miplevel.
1422 assert(info
.stencil_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1424 isl_surf_get_image_offset_B_tile_sa(info
.stencil_surf
,
1425 info
.view
->base_level
, 0, 0,
1426 &offset_B
, NULL
, NULL
);
1427 stencil_address
.offset
+= offset_B
;
1430 info
.stencil_address
=
1431 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
1432 stencil_address
, 0);
1435 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
1439 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1440 * depth/stencil buffer extents are ignored to handle APIs which perform
1441 * clearing operations without such information.
1444 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1445 const struct blorp_params
*params
)
1447 /* We should be performing an operation on a depth or stencil buffer.
1449 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1451 /* The stencil buffer should only be enabled if a fast clear operation is
1454 if (params
->stencil
.enabled
)
1455 assert(params
->hiz_op
== BLORP_HIZ_OP_DEPTH_CLEAR
);
1457 /* If we can't alter the depth stencil config and multiple layers are
1458 * involved, the HiZ op will fail. This is because the op requires that a
1459 * new config is emitted for each additional layer.
1461 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1462 assert(params
->num_layers
<= 1);
1464 blorp_emit_depth_stencil_config(batch
, params
);
1467 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1468 switch (params
->hiz_op
) {
1469 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1470 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1471 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1472 hzp
.StencilClearValue
= params
->stencil_ref
;
1473 hzp
.FullSurfaceDepthandStencilClear
= params
->full_surface_hiz_op
;
1475 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1476 assert(params
->full_surface_hiz_op
);
1477 hzp
.DepthBufferResolveEnable
= true;
1479 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1480 assert(params
->full_surface_hiz_op
);
1481 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1483 case BLORP_HIZ_OP_NONE
:
1484 unreachable("Invalid HIZ op");
1487 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1488 hzp
.SampleMask
= 0xFFFF;
1490 /* Due to a hardware issue, this bit MBZ */
1491 assert(hzp
.ScissorRectangleEnable
== false);
1493 /* Contrary to the HW docs both fields are inclusive */
1494 hzp
.ClearRectangleXMin
= params
->x0
;
1495 hzp
.ClearRectangleYMin
= params
->y0
;
1497 /* Contrary to the HW docs both fields are exclusive */
1498 hzp
.ClearRectangleXMax
= params
->x1
;
1499 hzp
.ClearRectangleYMax
= params
->y1
;
1502 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1503 * to “Write Immediate Data” enabled.
1505 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1506 pc
.PostSyncOperation
= WriteImmediateData
;
1507 pc
.Address
= blorp_get_workaround_page(batch
);
1510 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1515 * \brief Execute a blit or render pass operation.
1517 * To execute the operation, this function manually constructs and emits a
1518 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1519 * constructing and after emitting the batch.
1521 * This function alters no GL state.
1524 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1527 if (params
->hiz_op
!= BLORP_HIZ_OP_NONE
) {
1528 blorp_emit_gen8_hiz_op(batch
, params
);
1533 blorp_emit_vertex_buffers(batch
, params
);
1534 blorp_emit_vertex_elements(batch
, params
);
1536 blorp_emit_pipeline(batch
, params
);
1538 blorp_emit_surface_states(batch
, params
);
1540 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1541 blorp_emit_depth_stencil_config(batch
, params
);
1543 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1544 prim
.VertexAccessType
= SEQUENTIAL
;
1545 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1547 prim
.PredicateEnable
= batch
->flags
& BLORP_BATCH_PREDICATE_ENABLE
;
1549 prim
.VertexCountPerInstance
= 3;
1550 prim
.InstanceCount
= params
->num_layers
;
1554 #endif /* BLORP_GENX_EXEC_H */