2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "common/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "intel_aub.h"
33 * This file provides the blorp pipeline setup and execution functionality.
34 * It defines the following function:
37 * blorp_exec(struct blorp_context *blorp, void *batch_data,
38 * const struct blorp_params *params);
40 * It is the job of whoever includes this header to wrap this in something
41 * to get an externally visible symbol.
43 * In order for the blorp_exec function to work, the driver must provide
44 * implementations of the following static helper functions.
48 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
51 blorp_emit_reloc(struct blorp_batch
*batch
,
52 void *location
, struct blorp_address address
, uint32_t delta
);
55 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
56 enum aub_state_struct_type type
,
61 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
62 struct blorp_address
*addr
);
65 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
66 unsigned state_size
, unsigned state_alignment
,
67 uint32_t *bt_offset
, uint32_t *surface_offsets
,
70 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
71 struct blorp_address address
, uint32_t delta
);
74 blorp_emit_urb_config(struct blorp_batch
*batch
, unsigned vs_entry_size
);
76 /***** BEGIN blorp_exec implementation ******/
78 #include "genxml/gen_macros.h"
81 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
82 struct blorp_address address
, uint32_t delta
)
84 if (address
.buffer
== NULL
) {
85 return address
.offset
+ delta
;
87 return blorp_emit_reloc(batch
, location
, address
, delta
);
91 #define __gen_address_type struct blorp_address
92 #define __gen_user_data struct blorp_batch
93 #define __gen_combine_address _blorp_combine_address
95 #include "genxml/genX_pack.h"
97 #define _blorp_cmd_length(cmd) cmd ## _length
98 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
99 #define _blorp_cmd_header(cmd) cmd ## _header
100 #define _blorp_cmd_pack(cmd) cmd ## _pack
102 #define blorp_emit(batch, cmd, name) \
103 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
104 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
105 __builtin_expect(_dst != NULL, 1); \
106 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
109 #define blorp_emitn(batch, cmd, n) ({ \
110 uint32_t *_dw = blorp_emit_dwords(batch, n); \
111 struct cmd template = { \
112 _blorp_cmd_header(cmd), \
113 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
115 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
116 _dw + 1; /* Array starts at dw[1] */ \
125 * Assign the entire URB to the VS. Even though the VS disabled, URB space
126 * is still needed because the clipper loads the VUE's from the URB. From
127 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
128 * Dword 1.15:0 "VS Number of URB Entries":
129 * This field is always used (even if VS Function Enable is DISABLED).
131 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
132 * safely ignore it because this batch contains only one draw call.
133 * Because of URB corruption caused by allocating a previous GS unit
134 * URB entry to the VS unit, software is required to send a “GS NULL
135 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
136 * plus a dummy DRAW call before any case where VS will be taking over
139 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
140 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
142 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
143 * programmed in order for the programming of this state to be
147 emit_urb_config(struct blorp_batch
*batch
,
148 const struct blorp_params
*params
)
150 /* Once vertex fetcher has written full VUE entries with complete
151 * header the space requirement is as follows per vertex (in bytes):
153 * Header Position Program constants
154 * +--------+------------+-------------------+
155 * | 16 | 16 | n x 16 |
156 * +--------+------------+-------------------+
158 * where 'n' stands for number of varying inputs expressed as vec4s.
160 const unsigned num_varyings
=
161 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
162 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
164 /* The URB size is expressed in units of 64 bytes (512 bits) */
165 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
167 blorp_emit_urb_config(batch
, vs_entry_size
);
171 blorp_emit_vertex_data(struct blorp_batch
*batch
,
172 const struct blorp_params
*params
,
173 struct blorp_address
*addr
,
176 const float vertices
[] = {
177 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
178 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
179 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
182 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
183 memcpy(data
, vertices
, sizeof(vertices
));
184 *size
= sizeof(vertices
);
188 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
189 const struct blorp_params
*params
,
190 struct blorp_address
*addr
,
193 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
194 const unsigned max_num_varyings
=
195 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
196 const unsigned num_varyings
=
197 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
199 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
201 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
202 uint32_t *inputs
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
204 /* Copy in the VS inputs */
205 assert(sizeof(params
->vs_inputs
) == 16);
206 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
209 if (params
->wm_prog_data
) {
210 /* Walk over the attribute slots, determine if the attribute is used by
211 * the program and when necessary copy the values from the input storage
212 * to the vertex data buffer.
214 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
215 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
217 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
221 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
229 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
230 const struct blorp_params
*params
)
232 struct GENX(VERTEX_BUFFER_STATE
) vb
[2];
233 memset(vb
, 0, sizeof(vb
));
236 blorp_emit_vertex_data(batch
, params
, &vb
[0].BufferStartingAddress
, &size
);
237 vb
[0].VertexBufferIndex
= 0;
238 vb
[0].BufferPitch
= 3 * sizeof(float);
239 vb
[0].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
241 vb
[0].AddressModifyEnable
= true;
244 vb
[0].BufferSize
= size
;
246 vb
[0].BufferAccessType
= VERTEXDATA
;
247 vb
[0].EndAddress
= vb
[0].BufferStartingAddress
;
248 vb
[0].EndAddress
.offset
+= size
- 1;
251 blorp_emit_input_varying_data(batch
, params
,
252 &vb
[1].BufferStartingAddress
, &size
);
253 vb
[1].VertexBufferIndex
= 1;
254 vb
[1].BufferPitch
= 0;
255 vb
[1].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
257 vb
[1].AddressModifyEnable
= true;
260 vb
[1].BufferSize
= size
;
262 vb
[1].BufferAccessType
= INSTANCEDATA
;
263 vb
[1].EndAddress
= vb
[1].BufferStartingAddress
;
264 vb
[1].EndAddress
.offset
+= size
- 1;
267 const unsigned num_dwords
= 1 + GENX(VERTEX_BUFFER_STATE_length
) * 2;
268 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
270 for (unsigned i
= 0; i
< 2; i
++) {
271 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
272 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
277 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
278 const struct blorp_params
*params
)
280 const unsigned num_varyings
=
281 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
282 const unsigned num_elements
= 2 + num_varyings
;
284 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
285 memset(ve
, 0, num_elements
* sizeof(*ve
));
287 /* Setup VBO for the rectangle primitive..
289 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
290 * vertices. The vertices reside in screen space with DirectX
291 * coordinates (that is, (0, 0) is the upper left corner).
298 * Since the VS is disabled, the clipper loads each VUE directly from
299 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
300 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
301 * dw0: Reserved, MBZ.
302 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
303 * to assign this with primitive instance identifier which will be
304 * used for layered clears. All other renders have only one instance
305 * and therefore the value will be effectively zero.
306 * dw2: Viewport Index. The HiZ op disables viewport mapping and
307 * scissoring, so set the dword to 0.
308 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
309 * so set the dword to 0.
310 * dw4: Vertex Position X.
311 * dw5: Vertex Position Y.
312 * dw6: Vertex Position Z.
313 * dw7: Vertex Position W.
315 * dw8: Flat vertex input 0
316 * dw9: Flat vertex input 1
318 * dwn: Flat vertex input n - 8
320 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
321 * "Vertex URB Entry (VUE) Formats".
323 * Only vertex position X and Y are going to be variable, Z is fixed to
324 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
325 * include the fixed values in the vertex buffer. Vertex fetcher can be
326 * instructed to fill vertex elements with constant values of one and zero
327 * instead of reading them from the buffer.
328 * Flat inputs are program constants that are not interpolated. Moreover
329 * their values will be the same between vertices.
331 * See the vertex element setup below.
333 ve
[0].VertexBufferIndex
= 1;
335 ve
[0].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
336 ve
[0].SourceElementOffset
= 0;
337 ve
[0].Component0Control
= VFCOMP_STORE_SRC
;
339 /* From Gen8 onwards hardware is no more instructed to overwrite components
340 * using an element specifier. Instead one has separate 3DSTATE_VF_SGVS
341 * (System Generated Value Setup) state packet for it.
344 ve
[0].Component1Control
= VFCOMP_STORE_0
;
346 ve
[0].Component1Control
= VFCOMP_STORE_IID
;
348 ve
[0].Component2Control
= VFCOMP_STORE_SRC
;
349 ve
[0].Component3Control
= VFCOMP_STORE_SRC
;
351 ve
[1].VertexBufferIndex
= 0;
353 ve
[1].SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
;
354 ve
[1].SourceElementOffset
= 0;
355 ve
[1].Component0Control
= VFCOMP_STORE_SRC
;
356 ve
[1].Component1Control
= VFCOMP_STORE_SRC
;
357 ve
[1].Component2Control
= VFCOMP_STORE_SRC
;
358 ve
[1].Component3Control
= VFCOMP_STORE_1_FP
;
360 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
361 ve
[i
+ 2].VertexBufferIndex
= 1;
362 ve
[i
+ 2].Valid
= true;
363 ve
[i
+ 2].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
364 ve
[i
+ 2].SourceElementOffset
= 16 + i
* 4 * sizeof(float);
365 ve
[i
+ 2].Component0Control
= VFCOMP_STORE_SRC
;
366 ve
[i
+ 2].Component1Control
= VFCOMP_STORE_SRC
;
367 ve
[i
+ 2].Component2Control
= VFCOMP_STORE_SRC
;
368 ve
[i
+ 2].Component3Control
= VFCOMP_STORE_SRC
;
371 const unsigned num_dwords
=
372 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
373 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
375 for (unsigned i
= 0; i
< num_elements
; i
++) {
376 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
377 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
381 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
382 * primitive instance identifier. This is used for layered clears.
384 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
385 sgvs
.InstanceIDEnable
= true;
386 sgvs
.InstanceIDComponentNumber
= COMP_1
;
387 sgvs
.InstanceIDElementOffset
= 0;
390 for (unsigned i
= 0; i
< num_elements
; i
++) {
391 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
392 vf
.VertexElementIndex
= i
;
393 vf
.InstancingEnable
= false;
397 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
398 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
404 blorp_emit_vs_config(struct blorp_batch
*batch
,
405 const struct blorp_params
*params
)
407 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
409 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
411 vs
.FunctionEnable
= true;
413 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
415 vs
.DispatchGRFStartRegisterForURBData
=
416 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
417 vs
.VertexURBEntryReadLength
=
418 vs_prog_data
->base
.urb_read_length
;
419 vs
.VertexURBEntryReadOffset
= 0;
421 vs
.MaximumNumberofThreads
=
422 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
425 vs
.SIMD8DispatchEnable
=
426 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
433 blorp_emit_sf_config(struct blorp_batch
*batch
,
434 const struct blorp_params
*params
)
436 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
440 * Disable ViewportTransformEnable (dw2.1)
442 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
443 * Primitives Overview":
444 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
445 * use of screen- space coordinates).
447 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
448 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
450 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
451 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
452 * SOLID: Any triangle or rectangle object found to be front-facing
453 * is rendered as a solid object. This setting is required when
454 * (rendering rectangle (RECTLIST) objects.
459 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
461 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
462 raster
.CullMode
= CULLMODE_NONE
;
465 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
466 sbe
.VertexURBEntryReadOffset
= 1;
468 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
469 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
470 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
472 sbe
.NumberofSFOutputAttributes
= 0;
473 sbe
.VertexURBEntryReadLength
= 1;
475 sbe
.ForceVertexURBEntryReadLength
= true;
476 sbe
.ForceVertexURBEntryReadOffset
= true;
479 for (unsigned i
= 0; i
< 32; i
++)
480 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
486 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
487 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
488 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
490 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
491 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
494 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
498 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
499 sbe
.VertexURBEntryReadOffset
= 1;
501 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
502 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
503 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
505 sbe
.NumberofSFOutputAttributes
= 0;
506 sbe
.VertexURBEntryReadLength
= 1;
510 #else /* GEN_GEN <= 6 */
512 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
513 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
514 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
516 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
517 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
519 sf
.VertexURBEntryReadOffset
= 1;
521 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
522 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
523 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
525 sf
.NumberofSFOutputAttributes
= 0;
526 sf
.VertexURBEntryReadLength
= 1;
534 blorp_emit_ps_config(struct blorp_batch
*batch
,
535 const struct blorp_params
*params
)
537 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
539 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
540 * nonzero to prevent the GPU from hanging. While the documentation doesn't
541 * mention this explicitly, it notes that the valid range for the field is
542 * [1,39] = [2,40] threads, which excludes zero.
544 * To be safe (and to minimize extraneous code) we go ahead and fully
545 * configure the WM state whether or not there is a WM program.
550 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
552 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
553 if (params
->src
.enabled
) {
554 ps
.SamplerCount
= 1; /* Up to 4 samplers */
555 ps
.BindingTableEntryCount
= 2;
557 ps
.BindingTableEntryCount
= 1;
561 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
562 prog_data
->base
.dispatch_grf_start_reg
;
563 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
564 prog_data
->dispatch_grf_start_reg_2
;
566 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
567 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
569 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
570 ps
.KernelStartPointer2
=
571 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
574 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
575 * it implicitly scales for different GT levels (which have some # of
578 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
581 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
583 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
585 switch (params
->fast_clear_op
) {
586 case BLORP_FAST_CLEAR_OP_NONE
:
589 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
590 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
592 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
593 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
596 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
597 ps
.RenderTargetResolveEnable
= true;
600 case BLORP_FAST_CLEAR_OP_CLEAR
:
601 ps
.RenderTargetFastClearEnable
= true;
604 unreachable("Invalid fast clear op");
608 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
610 psx
.PixelShaderValid
= true;
611 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
612 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
615 if (params
->src
.enabled
)
616 psx
.PixelShaderKillsPixel
= true;
621 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
622 switch (params
->hiz_op
) {
623 case BLORP_HIZ_OP_DEPTH_CLEAR
:
624 wm
.DepthBufferClear
= true;
626 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
627 wm
.DepthBufferResolveEnable
= true;
629 case BLORP_HIZ_OP_HIZ_RESOLVE
:
630 wm
.HierarchicalDepthBufferResolveEnable
= true;
632 case BLORP_HIZ_OP_NONE
:
635 unreachable("not reached");
639 wm
.ThreadDispatchEnable
= true;
641 if (params
->src
.enabled
)
642 wm
.PixelShaderKillsPixel
= true;
644 if (params
->num_samples
> 1) {
645 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
646 wm
.MultisampleDispatchMode
=
647 (prog_data
&& prog_data
->persample_dispatch
) ?
648 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
650 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
651 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
655 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
656 ps
.MaximumNumberofThreads
=
657 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
664 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
665 prog_data
->base
.dispatch_grf_start_reg
;
666 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
667 prog_data
->dispatch_grf_start_reg_2
;
669 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
670 ps
.KernelStartPointer2
=
671 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
673 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
674 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
676 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
678 /* Gen7 hardware gets angry if we don't enable at least one dispatch
679 * mode, so just enable 16-pixel dispatch if we don't have a program.
681 ps
._16PixelDispatchEnable
= true;
684 if (params
->src
.enabled
)
685 ps
.SamplerCount
= 1; /* Up to 4 samplers */
687 switch (params
->fast_clear_op
) {
688 case BLORP_FAST_CLEAR_OP_NONE
:
690 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
691 ps
.RenderTargetResolveEnable
= true;
693 case BLORP_FAST_CLEAR_OP_CLEAR
:
694 ps
.RenderTargetFastClearEnable
= true;
697 unreachable("Invalid fast clear op");
701 #else /* GEN_GEN <= 6 */
703 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
704 wm
.MaximumNumberofThreads
=
705 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
707 switch (params
->hiz_op
) {
708 case BLORP_HIZ_OP_DEPTH_CLEAR
:
709 wm
.DepthBufferClear
= true;
711 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
712 wm
.DepthBufferResolveEnable
= true;
714 case BLORP_HIZ_OP_HIZ_RESOLVE
:
715 wm
.HierarchicalDepthBufferResolveEnable
= true;
717 case BLORP_HIZ_OP_NONE
:
720 unreachable("not reached");
724 wm
.ThreadDispatchEnable
= true;
726 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
727 prog_data
->base
.dispatch_grf_start_reg
;
728 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
729 prog_data
->dispatch_grf_start_reg_2
;
731 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
732 wm
.KernelStartPointer2
=
733 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
735 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
736 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
738 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
741 if (params
->src
.enabled
) {
742 wm
.SamplerCount
= 1; /* Up to 4 samplers */
743 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
746 if (params
->num_samples
> 1) {
747 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
748 wm
.MultisampleDispatchMode
=
749 (prog_data
&& prog_data
->persample_dispatch
) ?
750 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
752 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
753 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
760 static const uint32_t isl_to_gen_ds_surftype
[] = {
762 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
764 * "If depth/stencil is enabled with 1D render target, depth/stencil
765 * surface type needs to be set to 2D surface type and height set to 1.
766 * Depth will use (legacy) TileY and stencil will use TileW. For this
767 * case only, the Surface Type of the depth buffer can be 2D while the
768 * Surface Type of the render target(s) are 1D, representing an
769 * exception to a programming note above.
771 [ISL_SURF_DIM_1D
] = SURFTYPE_2D
,
773 [ISL_SURF_DIM_1D
] = SURFTYPE_1D
,
775 [ISL_SURF_DIM_2D
] = SURFTYPE_2D
,
776 [ISL_SURF_DIM_3D
] = SURFTYPE_3D
,
780 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
781 const struct blorp_params
*params
)
784 const uint32_t mocs
= 1; /* GEN7_MOCS_L3 */
786 const uint32_t mocs
= 0;
789 blorp_emit(batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
791 db
.DepthWriteEnable
= params
->depth
.enabled
;
792 db
.StencilWriteEnable
= params
->stencil
.enabled
;
796 db
.SeparateStencilBufferEnable
= true;
799 if (params
->depth
.enabled
) {
800 db
.SurfaceFormat
= params
->depth_format
;
801 db
.SurfaceType
= isl_to_gen_ds_surftype
[params
->depth
.surf
.dim
];
804 db
.TiledSurface
= true;
805 db
.TileWalk
= TILEWALK_YMAJOR
;
806 db
.MIPMapLayoutMode
= MIPLAYOUT_BELOW
;
809 db
.HierarchicalDepthBufferEnable
=
810 params
->depth
.aux_usage
== ISL_AUX_USAGE_HIZ
;
812 db
.Width
= params
->depth
.surf
.logical_level0_px
.width
- 1;
813 db
.Height
= params
->depth
.surf
.logical_level0_px
.height
- 1;
814 db
.RenderTargetViewExtent
= db
.Depth
=
815 params
->depth
.view
.array_len
- 1;
817 db
.LOD
= params
->depth
.view
.base_level
;
818 db
.MinimumArrayElement
= params
->depth
.view
.base_array_layer
;
820 db
.SurfacePitch
= params
->depth
.surf
.row_pitch
- 1;
823 isl_surf_get_array_pitch_el_rows(¶ms
->depth
.surf
) >> 2,
826 db
.SurfaceBaseAddress
= params
->depth
.addr
;
827 db
.DepthBufferMOCS
= mocs
;
828 } else if (params
->stencil
.enabled
) {
829 db
.SurfaceFormat
= D32_FLOAT
;
830 db
.SurfaceType
= isl_to_gen_ds_surftype
[params
->stencil
.surf
.dim
];
832 db
.Width
= params
->stencil
.surf
.logical_level0_px
.width
- 1;
833 db
.Height
= params
->stencil
.surf
.logical_level0_px
.height
- 1;
834 db
.RenderTargetViewExtent
= db
.Depth
=
835 params
->stencil
.view
.array_len
- 1;
837 db
.LOD
= params
->stencil
.view
.base_level
;
838 db
.MinimumArrayElement
= params
->stencil
.view
.base_array_layer
;
840 db
.SurfaceType
= SURFTYPE_NULL
;
841 db
.SurfaceFormat
= D32_FLOAT
;
845 blorp_emit(batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hiz
) {
846 if (params
->depth
.aux_usage
== ISL_AUX_USAGE_HIZ
) {
847 hiz
.SurfacePitch
= params
->depth
.aux_surf
.row_pitch
- 1;
848 hiz
.SurfaceBaseAddress
= params
->depth
.aux_addr
;
849 hiz
.HierarchicalDepthBufferMOCS
= mocs
;
852 isl_surf_get_array_pitch_sa_rows(¶ms
->depth
.aux_surf
) >> 2;
857 blorp_emit(batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
858 if (params
->stencil
.enabled
) {
859 #if GEN_GEN >= 8 || GEN_IS_HASWELL
860 sb
.StencilBufferEnable
= true;
863 sb
.SurfacePitch
= params
->stencil
.surf
.row_pitch
- 1,
866 isl_surf_get_array_pitch_el_rows(¶ms
->stencil
.surf
) >> 2,
869 sb
.SurfaceBaseAddress
= params
->stencil
.addr
;
870 sb
.StencilBufferMOCS
= batch
->blorp
->mocs
.tex
;
874 /* 3DSTATE_CLEAR_PARAMS
876 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
877 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
878 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
880 blorp_emit(batch
, GENX(3DSTATE_CLEAR_PARAMS
), clear
) {
881 clear
.DepthClearValueValid
= true;
882 clear
.DepthClearValue
= params
->depth
.clear_color
.u32
[0];
887 blorp_emit_blend_state(struct blorp_batch
*batch
,
888 const struct blorp_params
*params
)
890 struct GENX(BLEND_STATE
) blend
;
891 memset(&blend
, 0, sizeof(blend
));
893 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
894 blend
.Entry
[i
].PreBlendColorClampEnable
= true;
895 blend
.Entry
[i
].PostBlendColorClampEnable
= true;
896 blend
.Entry
[i
].ColorClampRange
= COLORCLAMP_RTFORMAT
;
898 blend
.Entry
[i
].WriteDisableRed
= params
->color_write_disable
[0];
899 blend
.Entry
[i
].WriteDisableGreen
= params
->color_write_disable
[1];
900 blend
.Entry
[i
].WriteDisableBlue
= params
->color_write_disable
[2];
901 blend
.Entry
[i
].WriteDisableAlpha
= params
->color_write_disable
[3];
905 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_BLEND_STATE
,
906 GENX(BLEND_STATE_length
) * 4,
908 GENX(BLEND_STATE_pack
)(NULL
, state
, &blend
);
911 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
912 sp
.BlendStatePointer
= offset
;
914 sp
.BlendStatePointerValid
= true;
920 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
921 ps_blend
.HasWriteableRT
= true;
929 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
930 const struct blorp_params
*params
)
932 struct GENX(COLOR_CALC_STATE
) cc
= { 0 };
935 cc
.StencilReferenceValue
= params
->stencil_ref
;
939 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_CC_STATE
,
940 GENX(COLOR_CALC_STATE_length
) * 4,
942 GENX(COLOR_CALC_STATE_pack
)(NULL
, state
, &cc
);
945 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
946 sp
.ColorCalcStatePointer
= offset
;
948 sp
.ColorCalcStatePointerValid
= true;
957 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
958 const struct blorp_params
*params
)
961 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
962 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
965 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
968 if (params
->depth
.enabled
) {
969 ds
.DepthBufferWriteEnable
= true;
971 switch (params
->hiz_op
) {
972 case BLORP_HIZ_OP_NONE
:
973 ds
.DepthTestEnable
= true;
974 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
977 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
978 * - 7.5.3.1 Depth Buffer Clear
979 * - 7.5.3.2 Depth Buffer Resolve
980 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
982 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
983 ds
.DepthTestEnable
= true;
984 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
987 case BLORP_HIZ_OP_DEPTH_CLEAR
:
988 case BLORP_HIZ_OP_HIZ_RESOLVE
:
989 ds
.DepthTestEnable
= false;
994 if (params
->stencil
.enabled
) {
995 ds
.StencilBufferWriteEnable
= true;
996 ds
.StencilTestEnable
= true;
997 ds
.DoubleSidedStencilEnable
= false;
999 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1000 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1002 ds
.StencilWriteMask
= params
->stencil_mask
;
1004 ds
.StencilReferenceValue
= params
->stencil_ref
;
1009 uint32_t offset
= 0;
1010 uint32_t *dw
= blorp_emit_dwords(batch
,
1011 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1012 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1015 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_DEPTH_STENCIL_STATE
,
1016 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1018 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1022 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1023 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1031 blorp_emit_surface_state(struct blorp_batch
*batch
,
1032 const struct brw_blorp_surface_info
*surface
,
1033 void *state
, uint32_t state_offset
,
1034 bool is_render_target
)
1036 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1037 struct isl_surf surf
= surface
->surf
;
1039 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1040 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1041 assert(surf
.logical_level0_px
.height
== 1);
1042 surf
.dim
= ISL_SURF_DIM_2D
;
1045 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1046 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1047 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1048 aux_usage
= ISL_AUX_USAGE_NONE
;
1050 const uint32_t mocs
=
1051 is_render_target
? batch
->blorp
->mocs
.rb
: batch
->blorp
->mocs
.tex
;
1053 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1054 .surf
= &surf
, .view
= &surface
->view
,
1055 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1056 .mocs
= mocs
, .clear_color
= surface
->clear_color
);
1058 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1061 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1062 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1063 * used to store other information. This should be ok, however, because
1064 * surface buffer addresses are always 4K page alinged.
1066 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1067 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1068 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1069 surface
->aux_addr
, *aux_addr
);
1074 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1075 const struct brw_blorp_surface_info
*surface
,
1078 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1079 .SurfaceType
= SURFTYPE_NULL
,
1080 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1081 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1082 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1083 .MIPCountLOD
= surface
->view
.base_level
,
1084 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1085 .Depth
= surface
->view
.array_len
- 1,
1086 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1087 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1090 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1096 .TiledSurface
= true,
1100 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1104 blorp_emit_surface_states(struct blorp_batch
*batch
,
1105 const struct blorp_params
*params
)
1107 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1108 uint32_t bind_offset
, surface_offsets
[2];
1109 void *surface_maps
[2];
1111 if (params
->use_pre_baked_binding_table
) {
1112 bind_offset
= params
->pre_baked_binding_table_offset
;
1114 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1115 blorp_alloc_binding_table(batch
, num_surfaces
,
1116 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1117 &bind_offset
, surface_offsets
, surface_maps
);
1119 if (params
->dst
.enabled
) {
1120 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1121 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1122 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1125 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1126 const struct brw_blorp_surface_info
*surface
=
1127 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1128 blorp_emit_null_surface_state(batch
, surface
,
1129 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1132 if (params
->src
.enabled
) {
1133 blorp_emit_surface_state(batch
, ¶ms
->src
,
1134 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1135 surface_offsets
[BLORP_TEXTURE_BT_INDEX
], false);
1140 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1141 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1142 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1143 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1145 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1146 bt
.PointertoPSBindingTable
= bind_offset
;
1149 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1150 bt
.PSBindingTableChange
= true;
1151 bt
.PointertoPSBindingTable
= bind_offset
;
1157 blorp_emit_sampler_state(struct blorp_batch
*batch
,
1158 const struct blorp_params
*params
)
1160 struct GENX(SAMPLER_STATE
) sampler
= {
1161 .MipModeFilter
= MIPFILTER_NONE
,
1162 .MagModeFilter
= MAPFILTER_LINEAR
,
1163 .MinModeFilter
= MAPFILTER_LINEAR
,
1166 .TCXAddressControlMode
= TCM_CLAMP
,
1167 .TCYAddressControlMode
= TCM_CLAMP
,
1168 .TCZAddressControlMode
= TCM_CLAMP
,
1169 .MaximumAnisotropy
= RATIO21
,
1170 .RAddressMinFilterRoundingEnable
= true,
1171 .RAddressMagFilterRoundingEnable
= true,
1172 .VAddressMinFilterRoundingEnable
= true,
1173 .VAddressMagFilterRoundingEnable
= true,
1174 .UAddressMinFilterRoundingEnable
= true,
1175 .UAddressMagFilterRoundingEnable
= true,
1176 .NonnormalizedCoordinateEnable
= true,
1180 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_SAMPLER_STATE
,
1181 GENX(SAMPLER_STATE_length
) * 4,
1183 GENX(SAMPLER_STATE_pack
)(NULL
, state
, &sampler
);
1186 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
1187 ssp
.PointertoPSSamplerState
= offset
;
1190 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
1191 ssp
.VSSamplerStateChange
= true;
1192 ssp
.GSSamplerStateChange
= true;
1193 ssp
.PSSamplerStateChange
= true;
1194 ssp
.PointertoPSSamplerState
= offset
;
1200 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1201 const struct blorp_params
*params
)
1203 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1204 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1207 /* The PRM says that this bit is valid only for DX9:
1209 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1210 * should not have any effect by setting or not setting this bit.
1212 ms
.PixelPositionOffsetEnable
= false;
1213 ms
.PixelLocation
= CENTER
;
1215 ms
.PixelLocation
= PIXLOC_CENTER
;
1217 switch (params
->num_samples
) {
1219 GEN_SAMPLE_POS_1X(ms
.Sample
);
1222 GEN_SAMPLE_POS_2X(ms
.Sample
);
1225 GEN_SAMPLE_POS_4X(ms
.Sample
);
1228 GEN_SAMPLE_POS_8X(ms
.Sample
);
1234 ms
.PixelLocation
= PIXLOC_CENTER
;
1235 GEN_SAMPLE_POS_4X(ms
.Sample
);
1240 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
1242 blorp_emit_viewport_state(struct blorp_batch
*batch
,
1243 const struct blorp_params
*params
)
1245 uint32_t cc_vp_offset
;
1247 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_CC_VP_STATE
,
1248 GENX(CC_VIEWPORT_length
) * 4, 32,
1251 GENX(CC_VIEWPORT_pack
)(batch
, state
,
1252 &(struct GENX(CC_VIEWPORT
)) {
1253 .MinimumDepth
= 0.0,
1254 .MaximumDepth
= 1.0,
1258 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
1259 vsp
.CCViewportPointer
= cc_vp_offset
;
1262 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
1263 vsp
.CCViewportStateChange
= true;
1264 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
1271 * \brief Execute a blit or render pass operation.
1273 * To execute the operation, this function manually constructs and emits a
1274 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1275 * constructing and after emitting the batch.
1277 * This function alters no GL state.
1280 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1282 uint32_t blend_state_offset
= 0;
1283 uint32_t color_calc_state_offset
= 0;
1284 uint32_t depth_stencil_state_offset
;
1286 blorp_emit_vertex_buffers(batch
, params
);
1287 blorp_emit_vertex_elements(batch
, params
);
1289 emit_urb_config(batch
, params
);
1291 if (params
->wm_prog_data
) {
1292 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1294 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1295 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1298 /* 3DSTATE_CC_STATE_POINTERS
1300 * The pointer offsets are relative to
1301 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1303 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1305 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1306 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1307 * one CC_STATE_POINTERS packet so we have to emit that here.
1309 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1310 cc
.BLEND_STATEChange
= true;
1311 cc
.COLOR_CALC_STATEChange
= true;
1312 cc
.DEPTH_STENCIL_STATEChange
= true;
1313 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1314 cc
.PointertoCOLOR_CALC_STATE
= color_calc_state_offset
;
1315 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1318 (void)blend_state_offset
;
1319 (void)color_calc_state_offset
;
1320 (void)depth_stencil_state_offset
;
1323 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1325 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1326 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1328 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1329 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1331 blorp_emit_surface_states(batch
, params
);
1333 if (params
->src
.enabled
)
1334 blorp_emit_sampler_state(batch
, params
);
1336 blorp_emit_3dstate_multisample(batch
, params
);
1338 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1339 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1342 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1343 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1345 * [DevSNB] A pipeline flush must be programmed prior to a
1346 * 3DSTATE_VS command that causes the VS Function Enable to
1347 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1348 * command with CS stall bit set and a post sync operation.
1350 * We've already done one at the start of the BLORP operation.
1352 blorp_emit_vs_config(batch
, params
);
1354 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1355 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1356 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1357 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1359 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1361 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1362 clip
.PerspectiveDivideDisable
= true;
1365 blorp_emit_sf_config(batch
, params
);
1366 blorp_emit_ps_config(batch
, params
);
1368 blorp_emit_viewport_state(batch
, params
);
1370 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1371 blorp_emit_depth_stencil_config(batch
, params
);
1373 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1374 prim
.VertexAccessType
= SEQUENTIAL
;
1375 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1376 prim
.VertexCountPerInstance
= 3;
1377 prim
.InstanceCount
= params
->num_layers
;
1381 #endif /* BLORP_GENX_EXEC_H */