2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "dev/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "genxml/gen_macros.h"
33 * This file provides the blorp pipeline setup and execution functionality.
34 * It defines the following function:
37 * blorp_exec(struct blorp_context *blorp, void *batch_data,
38 * const struct blorp_params *params);
40 * It is the job of whoever includes this header to wrap this in something
41 * to get an externally visible symbol.
43 * In order for the blorp_exec function to work, the driver must provide
44 * implementations of the following static helper functions.
48 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
51 blorp_emit_reloc(struct blorp_batch
*batch
,
52 void *location
, struct blorp_address address
, uint32_t delta
);
55 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
60 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
61 struct blorp_address
*addr
);
63 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch
*batch
,
64 const struct blorp_address
*addrs
,
68 static struct blorp_address
69 blorp_get_workaround_page(struct blorp_batch
*batch
);
73 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
74 unsigned state_size
, unsigned state_alignment
,
75 uint32_t *bt_offset
, uint32_t *surface_offsets
,
79 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
82 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
83 struct blorp_address address
, uint32_t delta
);
86 blorp_get_surface_address(struct blorp_batch
*batch
,
87 struct blorp_address address
);
89 #if GEN_GEN >= 7 && GEN_GEN < 10
90 static struct blorp_address
91 blorp_get_surface_base_address(struct blorp_batch
*batch
);
95 blorp_emit_urb_config(struct blorp_batch
*batch
,
96 unsigned vs_entry_size
, unsigned sf_entry_size
);
99 blorp_emit_pipeline(struct blorp_batch
*batch
,
100 const struct blorp_params
*params
);
102 /***** BEGIN blorp_exec implementation ******/
105 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
106 struct blorp_address address
, uint32_t delta
)
108 if (address
.buffer
== NULL
) {
109 return address
.offset
+ delta
;
111 return blorp_emit_reloc(batch
, location
, address
, delta
);
115 #define __gen_address_type struct blorp_address
116 #define __gen_user_data struct blorp_batch
117 #define __gen_combine_address _blorp_combine_address
119 #include "genxml/genX_pack.h"
121 #define _blorp_cmd_length(cmd) cmd ## _length
122 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
123 #define _blorp_cmd_header(cmd) cmd ## _header
124 #define _blorp_cmd_pack(cmd) cmd ## _pack
126 #define blorp_emit(batch, cmd, name) \
127 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
128 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
129 __builtin_expect(_dst != NULL, 1); \
130 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
133 #define blorp_emitn(batch, cmd, n, ...) ({ \
134 uint32_t *_dw = blorp_emit_dwords(batch, n); \
136 struct cmd template = { \
137 _blorp_cmd_header(cmd), \
138 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
141 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
143 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
146 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
148 #define blorp_emit_dynamic(batch, state, name, align, offset) \
149 for (struct state name = STRUCT_ZERO(state), \
150 *_dst = blorp_alloc_dynamic_state(batch, \
151 _blorp_cmd_length(state) * 4, \
153 __builtin_expect(_dst != NULL, 1); \
154 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
155 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
164 * Assign the entire URB to the VS. Even though the VS disabled, URB space
165 * is still needed because the clipper loads the VUE's from the URB. From
166 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
167 * Dword 1.15:0 "VS Number of URB Entries":
168 * This field is always used (even if VS Function Enable is DISABLED).
170 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
171 * safely ignore it because this batch contains only one draw call.
172 * Because of URB corruption caused by allocating a previous GS unit
173 * URB entry to the VS unit, software is required to send a “GS NULL
174 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
175 * plus a dummy DRAW call before any case where VS will be taking over
178 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
179 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
181 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
182 * programmed in order for the programming of this state to be
186 emit_urb_config(struct blorp_batch
*batch
,
187 const struct blorp_params
*params
)
189 /* Once vertex fetcher has written full VUE entries with complete
190 * header the space requirement is as follows per vertex (in bytes):
192 * Header Position Program constants
193 * +--------+------------+-------------------+
194 * | 16 | 16 | n x 16 |
195 * +--------+------------+-------------------+
197 * where 'n' stands for number of varying inputs expressed as vec4s.
199 const unsigned num_varyings
=
200 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
201 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
203 /* The URB size is expressed in units of 64 bytes (512 bits) */
204 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
206 const unsigned sf_entry_size
=
207 params
->sf_prog_data
? params
->sf_prog_data
->urb_entry_size
: 0;
209 blorp_emit_urb_config(batch
, vs_entry_size
, sf_entry_size
);
214 blorp_emit_memcpy(struct blorp_batch
*batch
,
215 struct blorp_address dst
,
216 struct blorp_address src
,
221 blorp_emit_vertex_data(struct blorp_batch
*batch
,
222 const struct blorp_params
*params
,
223 struct blorp_address
*addr
,
226 const float vertices
[] = {
227 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
228 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
229 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
232 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
233 memcpy(data
, vertices
, sizeof(vertices
));
234 *size
= sizeof(vertices
);
235 blorp_flush_range(batch
, data
, *size
);
239 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
240 const struct blorp_params
*params
,
241 struct blorp_address
*addr
,
244 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
245 const unsigned max_num_varyings
=
246 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
247 const unsigned num_varyings
=
248 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
250 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
252 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
253 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
254 uint32_t *inputs
= data
;
256 /* Copy in the VS inputs */
257 assert(sizeof(params
->vs_inputs
) == 16);
258 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
261 if (params
->wm_prog_data
) {
262 /* Walk over the attribute slots, determine if the attribute is used by
263 * the program and when necessary copy the values from the input storage
264 * to the vertex data buffer.
266 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
267 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
269 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
273 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
279 blorp_flush_range(batch
, data
, *size
);
281 if (params
->dst_clear_color_as_input
) {
283 /* In this case, the clear color isn't known statically and instead
284 * comes in through an indirect which we have to copy into the vertex
285 * buffer before we execute the 3DPRIMITIVE. We already copied the
286 * value of params->wm_inputs.clear_color into the vertex buffer in the
287 * loop above. Now we emit code to stomp it from the GPU with the
288 * actual clear color value.
290 assert(num_varyings
== 1);
292 /* The clear color is the first thing after the header */
293 struct blorp_address clear_color_input_addr
= *addr
;
294 clear_color_input_addr
.offset
+= 16;
296 const unsigned clear_color_size
=
297 GEN_GEN
< 10 ? batch
->blorp
->isl_dev
->ss
.clear_value_size
: 4 * 4;
298 blorp_emit_memcpy(batch
, clear_color_input_addr
,
299 params
->dst
.clear_color_addr
,
302 unreachable("MCS partial resolve is not a thing on SNB and earlier");
308 blorp_fill_vertex_buffer_state(struct blorp_batch
*batch
,
309 struct GENX(VERTEX_BUFFER_STATE
) *vb
,
311 struct blorp_address addr
, uint32_t size
,
314 vb
[idx
].VertexBufferIndex
= idx
;
315 vb
[idx
].BufferStartingAddress
= addr
;
316 vb
[idx
].BufferPitch
= stride
;
319 vb
[idx
].MOCS
= addr
.mocs
;
323 vb
[idx
].AddressModifyEnable
= true;
327 vb
[idx
].BufferSize
= size
;
329 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
330 vb
[idx
].EndAddress
= vb
[idx
].BufferStartingAddress
;
331 vb
[idx
].EndAddress
.offset
+= size
- 1;
333 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
334 vb
[idx
].MaxIndex
= stride
> 0 ? size
/ stride
: 0;
339 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
340 const struct blorp_params
*params
)
342 struct GENX(VERTEX_BUFFER_STATE
) vb
[3];
343 uint32_t num_vbs
= 2;
344 memset(vb
, 0, sizeof(vb
));
346 struct blorp_address addrs
[2] = {};
348 blorp_emit_vertex_data(batch
, params
, &addrs
[0], &size
);
349 blorp_fill_vertex_buffer_state(batch
, vb
, 0, addrs
[0], size
,
352 blorp_emit_input_varying_data(batch
, params
, &addrs
[1], &size
);
353 blorp_fill_vertex_buffer_state(batch
, vb
, 1, addrs
[1], size
, 0);
355 blorp_vf_invalidate_for_vb_48b_transitions(batch
, addrs
, num_vbs
);
357 const unsigned num_dwords
= 1 + num_vbs
* GENX(VERTEX_BUFFER_STATE_length
);
358 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
362 for (unsigned i
= 0; i
< num_vbs
; i
++) {
363 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
364 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
369 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
370 const struct blorp_params
*params
)
372 const unsigned num_varyings
=
373 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
374 bool need_ndc
= batch
->blorp
->compiler
->devinfo
->gen
<= 5;
375 const unsigned num_elements
= 2 + need_ndc
+ num_varyings
;
377 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
378 memset(ve
, 0, num_elements
* sizeof(*ve
));
380 /* Setup VBO for the rectangle primitive..
382 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
383 * vertices. The vertices reside in screen space with DirectX
384 * coordinates (that is, (0, 0) is the upper left corner).
391 * Since the VS is disabled, the clipper loads each VUE directly from
392 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
393 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
394 * dw0: Reserved, MBZ.
395 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
396 * to assign this with primitive instance identifier which will be
397 * used for layered clears. All other renders have only one instance
398 * and therefore the value will be effectively zero.
399 * dw2: Viewport Index. The HiZ op disables viewport mapping and
400 * scissoring, so set the dword to 0.
401 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
402 * so set the dword to 0.
403 * dw4: Vertex Position X.
404 * dw5: Vertex Position Y.
405 * dw6: Vertex Position Z.
406 * dw7: Vertex Position W.
408 * dw8: Flat vertex input 0
409 * dw9: Flat vertex input 1
411 * dwn: Flat vertex input n - 8
413 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
414 * "Vertex URB Entry (VUE) Formats".
416 * Only vertex position X and Y are going to be variable, Z is fixed to
417 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
418 * include the fixed values in the vertex buffer. Vertex fetcher can be
419 * instructed to fill vertex elements with constant values of one and zero
420 * instead of reading them from the buffer.
421 * Flat inputs are program constants that are not interpolated. Moreover
422 * their values will be the same between vertices.
424 * See the vertex element setup below.
428 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
429 .VertexBufferIndex
= 1,
431 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
432 .SourceElementOffset
= 0,
433 .Component0Control
= VFCOMP_STORE_SRC
,
435 /* From Gen8 onwards hardware is no more instructed to overwrite
436 * components using an element specifier. Instead one has separate
437 * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it.
440 .Component1Control
= VFCOMP_STORE_0
,
442 .Component1Control
= VFCOMP_STORE_IID
,
444 .Component1Control
= VFCOMP_STORE_0
,
446 .Component2Control
= VFCOMP_STORE_0
,
447 .Component3Control
= VFCOMP_STORE_0
,
449 .DestinationElementOffset
= slot
* 4,
455 /* On Iron Lake and earlier, a native device coordinates version of the
456 * position goes right after the normal VUE header and before position.
457 * Since w == 1 for all of our coordinates, this is just a copy of the
460 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
461 .VertexBufferIndex
= 0,
463 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
464 .SourceElementOffset
= 0,
465 .Component0Control
= VFCOMP_STORE_SRC
,
466 .Component1Control
= VFCOMP_STORE_SRC
,
467 .Component2Control
= VFCOMP_STORE_SRC
,
468 .Component3Control
= VFCOMP_STORE_1_FP
,
469 .DestinationElementOffset
= slot
* 4,
474 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
475 .VertexBufferIndex
= 0,
477 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
478 .SourceElementOffset
= 0,
479 .Component0Control
= VFCOMP_STORE_SRC
,
480 .Component1Control
= VFCOMP_STORE_SRC
,
481 .Component2Control
= VFCOMP_STORE_SRC
,
482 .Component3Control
= VFCOMP_STORE_1_FP
,
484 .DestinationElementOffset
= slot
* 4,
489 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
490 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
491 .VertexBufferIndex
= 1,
493 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
494 .SourceElementOffset
= 16 + i
* 4 * sizeof(float),
495 .Component0Control
= VFCOMP_STORE_SRC
,
496 .Component1Control
= VFCOMP_STORE_SRC
,
497 .Component2Control
= VFCOMP_STORE_SRC
,
498 .Component3Control
= VFCOMP_STORE_SRC
,
500 .DestinationElementOffset
= slot
* 4,
506 const unsigned num_dwords
=
507 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
508 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
512 for (unsigned i
= 0; i
< num_elements
; i
++) {
513 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
514 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
517 blorp_emit(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
518 vf
.StatisticsEnable
= false;
522 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
523 * primitive instance identifier. This is used for layered clears.
525 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
526 sgvs
.InstanceIDEnable
= true;
527 sgvs
.InstanceIDComponentNumber
= COMP_1
;
528 sgvs
.InstanceIDElementOffset
= 0;
531 for (unsigned i
= 0; i
< num_elements
; i
++) {
532 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
533 vf
.VertexElementIndex
= i
;
534 vf
.InstancingEnable
= false;
538 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
539 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
544 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
546 blorp_emit_cc_viewport(struct blorp_batch
*batch
)
548 uint32_t cc_vp_offset
;
549 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
550 vp
.MinimumDepth
= 0.0;
551 vp
.MaximumDepth
= 1.0;
555 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
556 vsp
.CCViewportPointer
= cc_vp_offset
;
559 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
560 vsp
.CCViewportStateChange
= true;
561 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
569 blorp_emit_sampler_state(struct blorp_batch
*batch
)
572 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
573 sampler
.MipModeFilter
= MIPFILTER_NONE
;
574 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
575 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
578 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
579 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
580 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
581 sampler
.MaximumAnisotropy
= RATIO21
;
582 sampler
.RAddressMinFilterRoundingEnable
= true;
583 sampler
.RAddressMagFilterRoundingEnable
= true;
584 sampler
.VAddressMinFilterRoundingEnable
= true;
585 sampler
.VAddressMagFilterRoundingEnable
= true;
586 sampler
.UAddressMinFilterRoundingEnable
= true;
587 sampler
.UAddressMagFilterRoundingEnable
= true;
589 sampler
.NonnormalizedCoordinateEnable
= true;
594 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
595 ssp
.PointertoPSSamplerState
= offset
;
598 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
599 ssp
.VSSamplerStateChange
= true;
600 ssp
.GSSamplerStateChange
= true;
601 ssp
.PSSamplerStateChange
= true;
602 ssp
.PointertoPSSamplerState
= offset
;
609 /* What follows is the code for setting up a "pipeline" on Sandy Bridge and
610 * later hardware. This file will be included by i965 for gen4-5 as well, so
611 * this code is guarded by GEN_GEN >= 6.
616 blorp_emit_vs_config(struct blorp_batch
*batch
,
617 const struct blorp_params
*params
)
619 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
620 assert(!vs_prog_data
|| GEN_GEN
< 11 ||
621 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
623 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
627 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
629 vs
.DispatchGRFStartRegisterForURBData
=
630 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
631 vs
.VertexURBEntryReadLength
=
632 vs_prog_data
->base
.urb_read_length
;
633 vs
.VertexURBEntryReadOffset
= 0;
635 vs
.MaximumNumberofThreads
=
636 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
639 vs
.SIMD8DispatchEnable
=
640 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
647 blorp_emit_sf_config(struct blorp_batch
*batch
,
648 const struct blorp_params
*params
)
650 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
654 * Disable ViewportTransformEnable (dw2.1)
656 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
657 * Primitives Overview":
658 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
659 * use of screen- space coordinates).
661 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
662 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
664 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
665 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
666 * SOLID: Any triangle or rectangle object found to be front-facing
667 * is rendered as a solid object. This setting is required when
668 * (rendering rectangle (RECTLIST) objects.
673 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
675 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
676 raster
.CullMode
= CULLMODE_NONE
;
679 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
680 sbe
.VertexURBEntryReadOffset
= 1;
682 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
683 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
684 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
686 sbe
.NumberofSFOutputAttributes
= 0;
687 sbe
.VertexURBEntryReadLength
= 1;
689 sbe
.ForceVertexURBEntryReadLength
= true;
690 sbe
.ForceVertexURBEntryReadOffset
= true;
693 for (unsigned i
= 0; i
< 32; i
++)
694 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
700 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
701 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
702 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
704 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
705 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
708 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
712 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
713 sbe
.VertexURBEntryReadOffset
= 1;
715 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
716 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
717 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
719 sbe
.NumberofSFOutputAttributes
= 0;
720 sbe
.VertexURBEntryReadLength
= 1;
724 #else /* GEN_GEN <= 6 */
726 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
727 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
728 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
730 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
731 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
733 sf
.VertexURBEntryReadOffset
= 1;
735 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
736 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
737 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
739 sf
.NumberofSFOutputAttributes
= 0;
740 sf
.VertexURBEntryReadLength
= 1;
748 blorp_emit_ps_config(struct blorp_batch
*batch
,
749 const struct blorp_params
*params
)
751 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
753 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
754 * nonzero to prevent the GPU from hanging. While the documentation doesn't
755 * mention this explicitly, it notes that the valid range for the field is
756 * [1,39] = [2,40] threads, which excludes zero.
758 * To be safe (and to minimize extraneous code) we go ahead and fully
759 * configure the WM state whether or not there is a WM program.
764 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
766 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
767 if (params
->src
.enabled
) {
768 ps
.SamplerCount
= 1; /* Up to 4 samplers */
769 ps
.BindingTableEntryCount
= 2;
771 ps
.BindingTableEntryCount
= 1;
774 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
775 * disable prefetching of binding tables on A0 and B0 steppings.
776 * TODO: Revisit this WA on C0 stepping.
779 ps
.BindingTableEntryCount
= 0;
781 /* SAMPLER_STATE prefetching is broken on Gen11 - WA_1606682166 */
786 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
787 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
788 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
790 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
792 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
793 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
795 * Since 16x MSAA is first introduced on SKL, we don't need to apply
796 * the workaround on any older hardware.
798 if (GEN_GEN
>= 9 && !prog_data
->persample_dispatch
&&
799 params
->num_samples
== 16) {
800 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
801 ps
._32PixelDispatchEnable
= false;
804 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
805 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
806 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
807 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
808 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
809 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
811 ps
.KernelStartPointer0
= params
->wm_prog_kernel
+
812 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
813 ps
.KernelStartPointer1
= params
->wm_prog_kernel
+
814 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
815 ps
.KernelStartPointer2
= params
->wm_prog_kernel
+
816 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
819 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
820 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
821 * k, it implies 2(k+1) threads. It implicitly scales for different GT
822 * levels (which have some # of PSDs).
824 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
827 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
829 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
831 switch (params
->fast_clear_op
) {
832 case ISL_AUX_OP_NONE
:
835 case ISL_AUX_OP_AMBIGUATE
:
836 ps
.RenderTargetFastClearEnable
= true;
837 ps
.RenderTargetResolveType
= FAST_CLEAR_0
;
841 case ISL_AUX_OP_PARTIAL_RESOLVE
:
842 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
844 case ISL_AUX_OP_FULL_RESOLVE
:
845 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
848 case ISL_AUX_OP_FULL_RESOLVE
:
849 ps
.RenderTargetResolveEnable
= true;
852 case ISL_AUX_OP_FAST_CLEAR
:
853 ps
.RenderTargetFastClearEnable
= true;
856 unreachable("Invalid fast clear op");
860 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
862 psx
.PixelShaderValid
= true;
863 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
864 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
867 if (params
->src
.enabled
)
868 psx
.PixelShaderKillsPixel
= true;
873 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
874 switch (params
->hiz_op
) {
875 case ISL_AUX_OP_FAST_CLEAR
:
876 wm
.DepthBufferClear
= true;
878 case ISL_AUX_OP_FULL_RESOLVE
:
879 wm
.DepthBufferResolveEnable
= true;
881 case ISL_AUX_OP_AMBIGUATE
:
882 wm
.HierarchicalDepthBufferResolveEnable
= true;
884 case ISL_AUX_OP_NONE
:
887 unreachable("not reached");
891 wm
.ThreadDispatchEnable
= true;
893 if (params
->src
.enabled
)
894 wm
.PixelShaderKillsPixel
= true;
896 if (params
->num_samples
> 1) {
897 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
898 wm
.MultisampleDispatchMode
=
899 (prog_data
&& prog_data
->persample_dispatch
) ?
900 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
902 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
903 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
907 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
908 ps
.MaximumNumberofThreads
=
909 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
916 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
917 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
918 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
920 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
921 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
922 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
923 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
924 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
925 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
927 ps
.KernelStartPointer0
= params
->wm_prog_kernel
+
928 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
929 ps
.KernelStartPointer1
= params
->wm_prog_kernel
+
930 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
931 ps
.KernelStartPointer2
= params
->wm_prog_kernel
+
932 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
934 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
936 /* Gen7 hardware gets angry if we don't enable at least one dispatch
937 * mode, so just enable 16-pixel dispatch if we don't have a program.
939 ps
._16PixelDispatchEnable
= true;
942 if (params
->src
.enabled
)
943 ps
.SamplerCount
= 1; /* Up to 4 samplers */
945 switch (params
->fast_clear_op
) {
946 case ISL_AUX_OP_NONE
:
948 case ISL_AUX_OP_FULL_RESOLVE
:
949 ps
.RenderTargetResolveEnable
= true;
951 case ISL_AUX_OP_FAST_CLEAR
:
952 ps
.RenderTargetFastClearEnable
= true;
955 unreachable("Invalid fast clear op");
959 #else /* GEN_GEN <= 6 */
961 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
962 wm
.MaximumNumberofThreads
=
963 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
965 switch (params
->hiz_op
) {
966 case ISL_AUX_OP_FAST_CLEAR
:
967 wm
.DepthBufferClear
= true;
969 case ISL_AUX_OP_FULL_RESOLVE
:
970 wm
.DepthBufferResolveEnable
= true;
972 case ISL_AUX_OP_AMBIGUATE
:
973 wm
.HierarchicalDepthBufferResolveEnable
= true;
975 case ISL_AUX_OP_NONE
:
978 unreachable("not reached");
982 wm
.ThreadDispatchEnable
= true;
984 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
985 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
986 wm
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
988 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
989 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 0);
990 wm
.DispatchGRFStartRegisterForConstantSetupData1
=
991 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 1);
992 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
993 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 2);
995 wm
.KernelStartPointer0
= params
->wm_prog_kernel
+
996 brw_wm_prog_data_prog_offset(prog_data
, wm
, 0);
997 wm
.KernelStartPointer1
= params
->wm_prog_kernel
+
998 brw_wm_prog_data_prog_offset(prog_data
, wm
, 1);
999 wm
.KernelStartPointer2
= params
->wm_prog_kernel
+
1000 brw_wm_prog_data_prog_offset(prog_data
, wm
, 2);
1002 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
1005 if (params
->src
.enabled
) {
1006 wm
.SamplerCount
= 1; /* Up to 4 samplers */
1007 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
1010 if (params
->num_samples
> 1) {
1011 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1012 wm
.MultisampleDispatchMode
=
1013 (prog_data
&& prog_data
->persample_dispatch
) ?
1014 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
1016 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1017 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1021 #endif /* GEN_GEN */
1025 blorp_emit_blend_state(struct blorp_batch
*batch
,
1026 const struct blorp_params
*params
)
1028 struct GENX(BLEND_STATE
) blend
;
1029 memset(&blend
, 0, sizeof(blend
));
1032 int size
= GENX(BLEND_STATE_length
) * 4;
1033 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
1034 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
1035 uint32_t *pos
= state
;
1037 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
1038 pos
+= GENX(BLEND_STATE_length
);
1040 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
1041 struct GENX(BLEND_STATE_ENTRY
) entry
= {
1042 .PreBlendColorClampEnable
= true,
1043 .PostBlendColorClampEnable
= true,
1044 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
1046 .WriteDisableRed
= params
->color_write_disable
[0],
1047 .WriteDisableGreen
= params
->color_write_disable
[1],
1048 .WriteDisableBlue
= params
->color_write_disable
[2],
1049 .WriteDisableAlpha
= params
->color_write_disable
[3],
1051 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
1052 pos
+= GENX(BLEND_STATE_ENTRY_length
);
1055 blorp_flush_range(batch
, state
, size
);
1058 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
1059 sp
.BlendStatePointer
= offset
;
1061 sp
.BlendStatePointerValid
= true;
1067 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
1068 ps_blend
.HasWriteableRT
= true;
1076 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
1077 MAYBE_UNUSED
const struct blorp_params
*params
)
1080 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
1082 cc
.StencilReferenceValue
= params
->stencil_ref
;
1087 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
1088 sp
.ColorCalcStatePointer
= offset
;
1090 sp
.ColorCalcStatePointerValid
= true;
1099 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
1100 const struct blorp_params
*params
)
1103 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
1104 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
1107 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
1110 if (params
->depth
.enabled
) {
1111 ds
.DepthBufferWriteEnable
= true;
1113 switch (params
->hiz_op
) {
1114 case ISL_AUX_OP_NONE
:
1115 ds
.DepthTestEnable
= true;
1116 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
1119 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
1120 * - 7.5.3.1 Depth Buffer Clear
1121 * - 7.5.3.2 Depth Buffer Resolve
1122 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1124 case ISL_AUX_OP_FULL_RESOLVE
:
1125 ds
.DepthTestEnable
= true;
1126 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
1129 case ISL_AUX_OP_FAST_CLEAR
:
1130 case ISL_AUX_OP_AMBIGUATE
:
1131 ds
.DepthTestEnable
= false;
1133 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1134 unreachable("Invalid HIZ op");
1138 if (params
->stencil
.enabled
) {
1139 ds
.StencilBufferWriteEnable
= true;
1140 ds
.StencilTestEnable
= true;
1141 ds
.DoubleSidedStencilEnable
= false;
1143 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1144 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1146 ds
.StencilWriteMask
= params
->stencil_mask
;
1148 ds
.StencilReferenceValue
= params
->stencil_ref
;
1153 uint32_t offset
= 0;
1154 uint32_t *dw
= blorp_emit_dwords(batch
,
1155 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1159 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1162 void *state
= blorp_alloc_dynamic_state(batch
,
1163 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1165 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1166 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1170 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1171 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1179 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1180 const struct blorp_params
*params
)
1182 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1183 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1186 /* The PRM says that this bit is valid only for DX9:
1188 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1189 * should not have any effect by setting or not setting this bit.
1191 ms
.PixelPositionOffsetEnable
= false;
1194 switch (params
->num_samples
) {
1196 GEN_SAMPLE_POS_1X(ms
.Sample
);
1199 GEN_SAMPLE_POS_2X(ms
.Sample
);
1202 GEN_SAMPLE_POS_4X(ms
.Sample
);
1205 GEN_SAMPLE_POS_8X(ms
.Sample
);
1211 GEN_SAMPLE_POS_4X(ms
.Sample
);
1213 ms
.PixelLocation
= CENTER
;
1218 blorp_emit_pipeline(struct blorp_batch
*batch
,
1219 const struct blorp_params
*params
)
1221 uint32_t blend_state_offset
= 0;
1222 uint32_t color_calc_state_offset
;
1223 uint32_t depth_stencil_state_offset
;
1225 emit_urb_config(batch
, params
);
1227 if (params
->wm_prog_data
) {
1228 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1230 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1231 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1234 /* 3DSTATE_CC_STATE_POINTERS
1236 * The pointer offsets are relative to
1237 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1239 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1241 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1242 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1243 * one CC_STATE_POINTERS packet so we have to emit that here.
1245 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1246 cc
.BLEND_STATEChange
= true;
1247 cc
.ColorCalcStatePointerValid
= true;
1248 cc
.DEPTH_STENCIL_STATEChange
= true;
1249 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1250 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1251 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1254 (void)blend_state_offset
;
1255 (void)color_calc_state_offset
;
1256 (void)depth_stencil_state_offset
;
1259 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1261 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1262 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1264 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1265 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1267 if (params
->src
.enabled
)
1268 blorp_emit_sampler_state(batch
);
1270 blorp_emit_3dstate_multisample(batch
, params
);
1272 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1273 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1276 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1277 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1279 * [DevSNB] A pipeline flush must be programmed prior to a
1280 * 3DSTATE_VS command that causes the VS Function Enable to
1281 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1282 * command with CS stall bit set and a post sync operation.
1284 * We've already done one at the start of the BLORP operation.
1286 blorp_emit_vs_config(batch
, params
);
1288 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1289 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1290 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1291 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1293 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1295 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1296 clip
.PerspectiveDivideDisable
= true;
1299 blorp_emit_sf_config(batch
, params
);
1300 blorp_emit_ps_config(batch
, params
);
1302 blorp_emit_cc_viewport(batch
);
1305 /******** This is the end of the pipeline setup code ********/
1307 #endif /* GEN_GEN >= 6 */
1311 blorp_emit_memcpy(struct blorp_batch
*batch
,
1312 struct blorp_address dst
,
1313 struct blorp_address src
,
1316 assert(size
% 4 == 0);
1318 for (unsigned dw
= 0; dw
< size
; dw
+= 4) {
1320 blorp_emit(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
1321 cp
.DestinationMemoryAddress
= dst
;
1322 cp
.SourceMemoryAddress
= src
;
1325 /* IVB does not have a general purpose register for command streamer
1326 * commands. Therefore, we use an alternate temporary register.
1328 #define BLORP_TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
1329 blorp_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), load
) {
1330 load
.RegisterAddress
= BLORP_TEMP_REG
;
1331 load
.MemoryAddress
= src
;
1333 blorp_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), store
) {
1334 store
.RegisterAddress
= BLORP_TEMP_REG
;
1335 store
.MemoryAddress
= dst
;
1337 #undef BLORP_TEMP_REG
1346 blorp_emit_surface_state(struct blorp_batch
*batch
,
1347 const struct brw_blorp_surface_info
*surface
,
1348 enum isl_aux_op aux_op
,
1349 void *state
, uint32_t state_offset
,
1350 const bool color_write_disables
[4],
1351 bool is_render_target
)
1353 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1354 struct isl_surf surf
= surface
->surf
;
1356 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1357 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1358 assert(surf
.logical_level0_px
.height
== 1);
1359 surf
.dim
= ISL_SURF_DIM_2D
;
1362 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1363 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1364 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1365 aux_usage
= ISL_AUX_USAGE_NONE
;
1367 isl_channel_mask_t write_disable_mask
= 0;
1368 if (is_render_target
&& GEN_GEN
<= 5) {
1369 if (color_write_disables
[0])
1370 write_disable_mask
|= ISL_CHANNEL_RED_BIT
;
1371 if (color_write_disables
[1])
1372 write_disable_mask
|= ISL_CHANNEL_GREEN_BIT
;
1373 if (color_write_disables
[2])
1374 write_disable_mask
|= ISL_CHANNEL_BLUE_BIT
;
1375 if (color_write_disables
[3])
1376 write_disable_mask
|= ISL_CHANNEL_ALPHA_BIT
;
1379 const bool use_clear_address
=
1380 GEN_GEN
>= 10 && (surface
->clear_color_addr
.buffer
!= NULL
);
1382 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1383 .surf
= &surf
, .view
= &surface
->view
,
1384 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1386 blorp_get_surface_address(batch
, surface
->addr
),
1387 .aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
? 0 :
1388 blorp_get_surface_address(batch
, surface
->aux_addr
),
1389 .clear_address
= !use_clear_address
? 0 :
1390 blorp_get_surface_address(batch
,
1391 surface
->clear_color_addr
),
1392 .mocs
= surface
->addr
.mocs
,
1393 .clear_color
= surface
->clear_color
,
1394 .use_clear_address
= use_clear_address
,
1395 .write_disables
= write_disable_mask
);
1397 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1400 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1401 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1402 * used to store other information. This should be ok, however, because
1403 * surface buffer addresses are always 4K page alinged.
1405 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1406 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1407 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1408 surface
->aux_addr
, *aux_addr
);
1411 if (aux_usage
!= ISL_AUX_USAGE_NONE
&& surface
->clear_color_addr
.buffer
) {
1413 assert((surface
->clear_color_addr
.offset
& 0x3f) == 0);
1414 uint32_t *clear_addr
= state
+ isl_dev
->ss
.clear_color_state_offset
;
1415 blorp_surface_reloc(batch
, state_offset
+
1416 isl_dev
->ss
.clear_color_state_offset
,
1417 surface
->clear_color_addr
, *clear_addr
);
1419 /* Fast clears just whack the AUX surface and don't actually use the
1420 * clear color for anything. We can avoid the MI memcpy on that case.
1422 if (aux_op
!= ISL_AUX_OP_FAST_CLEAR
) {
1423 struct blorp_address dst_addr
= blorp_get_surface_base_address(batch
);
1424 dst_addr
.offset
+= state_offset
+ isl_dev
->ss
.clear_value_offset
;
1425 blorp_emit_memcpy(batch
, dst_addr
, surface
->clear_color_addr
,
1426 isl_dev
->ss
.clear_value_size
);
1429 unreachable("Fast clears are only supported on gen7+");
1433 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1437 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1438 const struct brw_blorp_surface_info
*surface
,
1441 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1442 .SurfaceType
= SURFTYPE_NULL
,
1443 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1444 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1445 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1446 .MIPCountLOD
= surface
->view
.base_level
,
1447 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1448 .Depth
= surface
->view
.array_len
- 1,
1449 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1451 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1455 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1461 .TiledSurface
= true,
1465 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1467 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1471 blorp_emit_surface_states(struct blorp_batch
*batch
,
1472 const struct blorp_params
*params
)
1474 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1475 uint32_t bind_offset
= 0, surface_offsets
[2];
1476 void *surface_maps
[2];
1478 MAYBE_UNUSED
bool has_indirect_clear_color
= false;
1479 if (params
->use_pre_baked_binding_table
) {
1480 bind_offset
= params
->pre_baked_binding_table_offset
;
1482 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1483 blorp_alloc_binding_table(batch
, num_surfaces
,
1484 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1485 &bind_offset
, surface_offsets
, surface_maps
);
1487 if (params
->dst
.enabled
) {
1488 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1489 params
->fast_clear_op
,
1490 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1491 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1492 params
->color_write_disable
, true);
1493 if (params
->dst
.clear_color_addr
.buffer
!= NULL
)
1494 has_indirect_clear_color
= true;
1496 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1497 const struct brw_blorp_surface_info
*surface
=
1498 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1499 blorp_emit_null_surface_state(batch
, surface
,
1500 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1503 if (params
->src
.enabled
) {
1504 blorp_emit_surface_state(batch
, ¶ms
->src
,
1505 params
->fast_clear_op
,
1506 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1507 surface_offsets
[BLORP_TEXTURE_BT_INDEX
],
1509 if (params
->src
.clear_color_addr
.buffer
!= NULL
)
1510 has_indirect_clear_color
= true;
1515 if (has_indirect_clear_color
) {
1516 /* Updating a surface state object may require that the state cache be
1517 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1520 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1521 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1522 * modified [...], the L1 state cache must be invalidated to ensure
1523 * the new surface or sampler state is fetched from system memory.
1525 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1526 pipe
.StateCacheInvalidationEnable
= true;
1532 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1533 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1534 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1535 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1537 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1538 bt
.PointertoPSBindingTable
= bind_offset
;
1541 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1542 bt
.PSBindingTableChange
= true;
1543 bt
.PointertoPSBindingTable
= bind_offset
;
1546 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1547 bt
.PointertoPSBindingTable
= bind_offset
;
1553 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
1554 const struct blorp_params
*params
)
1556 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1558 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
1562 struct isl_depth_stencil_hiz_emit_info info
= { };
1564 if (params
->depth
.enabled
) {
1565 info
.view
= ¶ms
->depth
.view
;
1566 info
.mocs
= params
->depth
.addr
.mocs
;
1567 } else if (params
->stencil
.enabled
) {
1568 info
.view
= ¶ms
->stencil
.view
;
1569 info
.mocs
= params
->stencil
.addr
.mocs
;
1572 if (params
->depth
.enabled
) {
1573 info
.depth_surf
= ¶ms
->depth
.surf
;
1575 info
.depth_address
=
1576 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
1577 params
->depth
.addr
, 0);
1579 info
.hiz_usage
= params
->depth
.aux_usage
;
1580 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
1581 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
1583 struct blorp_address hiz_address
= params
->depth
.aux_addr
;
1585 /* Sandy bridge hardware does not technically support mipmapped HiZ.
1586 * However, we have a special layout that allows us to make it work
1587 * anyway by manually offsetting to the specified miplevel.
1589 assert(info
.hiz_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1591 isl_surf_get_image_offset_B_tile_sa(info
.hiz_surf
,
1592 info
.view
->base_level
, 0, 0,
1593 &offset_B
, NULL
, NULL
);
1594 hiz_address
.offset
+= offset_B
;
1598 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
1601 info
.depth_clear_value
= params
->depth
.clear_color
.f32
[0];
1605 if (params
->stencil
.enabled
) {
1606 info
.stencil_surf
= ¶ms
->stencil
.surf
;
1608 struct blorp_address stencil_address
= params
->stencil
.addr
;
1610 /* Sandy bridge hardware does not technically support mipmapped stencil.
1611 * However, we have a special layout that allows us to make it work
1612 * anyway by manually offsetting to the specified miplevel.
1614 assert(info
.stencil_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1616 isl_surf_get_image_offset_B_tile_sa(info
.stencil_surf
,
1617 info
.view
->base_level
, 0, 0,
1618 &offset_B
, NULL
, NULL
);
1619 stencil_address
.offset
+= offset_B
;
1622 info
.stencil_address
=
1623 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
1624 stencil_address
, 0);
1627 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
1631 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1632 * depth/stencil buffer extents are ignored to handle APIs which perform
1633 * clearing operations without such information.
1636 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1637 const struct blorp_params
*params
)
1639 /* We should be performing an operation on a depth or stencil buffer.
1641 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1643 /* The stencil buffer should only be enabled if a fast clear operation is
1646 if (params
->stencil
.enabled
)
1647 assert(params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
);
1649 /* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
1651 * 3DSTATE_MULTISAMPLE packet must be used prior to this packet to change
1652 * the Number of Multisamples. This packet must not be used to change
1653 * Number of Multisamples in a rendering sequence.
1655 * Since HIZ may be the first thing in a batch buffer, play safe and always
1656 * emit 3DSTATE_MULTISAMPLE.
1658 blorp_emit_3dstate_multisample(batch
, params
);
1660 /* From the BDW PRM Volume 7, Depth Buffer Clear:
1662 * The clear value must be between the min and max depth values
1663 * (inclusive) defined in the CC_VIEWPORT. If the depth buffer format is
1664 * D32_FLOAT, then +/-DENORM values are also allowed.
1666 * Set the bounds to match our hardware limits, [0.0, 1.0].
1668 if (params
->depth
.enabled
&& params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
) {
1669 assert(params
->depth
.clear_color
.f32
[0] >= 0.0f
);
1670 assert(params
->depth
.clear_color
.f32
[0] <= 1.0f
);
1671 blorp_emit_cc_viewport(batch
);
1674 /* According to the SKL PRM formula for WM_INT::ThreadDispatchEnable, the
1675 * 3DSTATE_WM::ForceThreadDispatchEnable field can force WM thread dispatch
1676 * even when WM_HZ_OP is active. However, WM thread dispatch is normally
1677 * disabled for HiZ ops and it appears that force-enabling it can lead to
1678 * GPU hangs on at least Skylake. Since we don't know the current state of
1679 * the 3DSTATE_WM packet, just emit a dummy one prior to 3DSTATE_WM_HZ_OP.
1681 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
1683 /* If we can't alter the depth stencil config and multiple layers are
1684 * involved, the HiZ op will fail. This is because the op requires that a
1685 * new config is emitted for each additional layer.
1687 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1688 assert(params
->num_layers
<= 1);
1690 blorp_emit_depth_stencil_config(batch
, params
);
1693 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1694 switch (params
->hiz_op
) {
1695 case ISL_AUX_OP_FAST_CLEAR
:
1696 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1697 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1698 hzp
.StencilClearValue
= params
->stencil_ref
;
1699 hzp
.FullSurfaceDepthandStencilClear
= params
->full_surface_hiz_op
;
1701 case ISL_AUX_OP_FULL_RESOLVE
:
1702 assert(params
->full_surface_hiz_op
);
1703 hzp
.DepthBufferResolveEnable
= true;
1705 case ISL_AUX_OP_AMBIGUATE
:
1706 assert(params
->full_surface_hiz_op
);
1707 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1709 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1710 case ISL_AUX_OP_NONE
:
1711 unreachable("Invalid HIZ op");
1714 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1715 hzp
.SampleMask
= 0xFFFF;
1717 /* Due to a hardware issue, this bit MBZ */
1718 assert(hzp
.ScissorRectangleEnable
== false);
1720 /* Contrary to the HW docs both fields are inclusive */
1721 hzp
.ClearRectangleXMin
= params
->x0
;
1722 hzp
.ClearRectangleYMin
= params
->y0
;
1724 /* Contrary to the HW docs both fields are exclusive */
1725 hzp
.ClearRectangleXMax
= params
->x1
;
1726 hzp
.ClearRectangleYMax
= params
->y1
;
1729 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1730 * to “Write Immediate Data” enabled.
1732 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1733 pc
.PostSyncOperation
= WriteImmediateData
;
1734 pc
.Address
= blorp_get_workaround_page(batch
);
1737 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1742 blorp_update_clear_color(struct blorp_batch
*batch
,
1743 const struct brw_blorp_surface_info
*info
,
1746 if (info
->clear_color_addr
.buffer
&& op
== ISL_AUX_OP_FAST_CLEAR
) {
1748 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1749 pipe
.CommandStreamerStallEnable
= true;
1753 const unsigned inlinedata_dw
= 2 * 2;
1754 const unsigned num_dwords
= GENX(MI_ATOMIC_length
) + inlinedata_dw
;
1756 struct blorp_address clear_addr
= info
->clear_color_addr
;
1757 uint32_t *dw
= blorp_emitn(batch
, GENX(MI_ATOMIC
), num_dwords
,
1758 .DataSize
= MI_ATOMIC_QWORD
,
1759 .ATOMICOPCODE
= MI_ATOMIC_OP_MOVE8B
,
1761 .MemoryAddress
= clear_addr
);
1762 /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
1763 dw
[2] = info
->clear_color
.u32
[0];
1764 dw
[4] = info
->clear_color
.u32
[1];
1766 clear_addr
.offset
+= 8;
1767 dw
= blorp_emitn(batch
, GENX(MI_ATOMIC
), num_dwords
,
1768 .DataSize
= MI_ATOMIC_QWORD
,
1769 .ATOMICOPCODE
= MI_ATOMIC_OP_MOVE8B
,
1771 .ReturnDataControl
= true,
1773 .MemoryAddress
= clear_addr
);
1774 /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
1775 dw
[2] = info
->clear_color
.u32
[2];
1776 dw
[4] = info
->clear_color
.u32
[3];
1778 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1779 pipe
.StateCacheInvalidationEnable
= true;
1780 pipe
.TextureCacheInvalidationEnable
= true;
1783 for (int i
= 0; i
< 4; i
++) {
1784 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1785 sdi
.Address
= info
->clear_color_addr
;
1786 sdi
.Address
.offset
+= i
* 4;
1787 sdi
.ImmediateData
= info
->clear_color
.u32
[i
];
1791 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1792 sdi
.Address
= info
->clear_color_addr
;
1793 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
1794 ISL_CHANNEL_SELECT_GREEN
<< 22 |
1795 ISL_CHANNEL_SELECT_BLUE
<< 19 |
1796 ISL_CHANNEL_SELECT_ALPHA
<< 16;
1797 if (isl_format_has_int_channel(info
->view
.format
)) {
1798 for (unsigned i
= 0; i
< 4; i
++) {
1799 assert(info
->clear_color
.u32
[i
] == 0 ||
1800 info
->clear_color
.u32
[i
] == 1);
1802 sdi
.ImmediateData
|= (info
->clear_color
.u32
[0] != 0) << 31;
1803 sdi
.ImmediateData
|= (info
->clear_color
.u32
[1] != 0) << 30;
1804 sdi
.ImmediateData
|= (info
->clear_color
.u32
[2] != 0) << 29;
1805 sdi
.ImmediateData
|= (info
->clear_color
.u32
[3] != 0) << 28;
1807 for (unsigned i
= 0; i
< 4; i
++) {
1808 assert(info
->clear_color
.f32
[i
] == 0.0f
||
1809 info
->clear_color
.f32
[i
] == 1.0f
);
1811 sdi
.ImmediateData
|= (info
->clear_color
.f32
[0] != 0.0f
) << 31;
1812 sdi
.ImmediateData
|= (info
->clear_color
.f32
[1] != 0.0f
) << 30;
1813 sdi
.ImmediateData
|= (info
->clear_color
.f32
[2] != 0.0f
) << 29;
1814 sdi
.ImmediateData
|= (info
->clear_color
.f32
[3] != 0.0f
) << 28;
1822 * \brief Execute a blit or render pass operation.
1824 * To execute the operation, this function manually constructs and emits a
1825 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1826 * constructing and after emitting the batch.
1828 * This function alters no GL state.
1831 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1833 if (!(batch
->flags
& BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
)) {
1834 blorp_update_clear_color(batch
, ¶ms
->dst
, params
->fast_clear_op
);
1835 blorp_update_clear_color(batch
, ¶ms
->depth
, params
->hiz_op
);
1839 if (params
->hiz_op
!= ISL_AUX_OP_NONE
) {
1840 blorp_emit_gen8_hiz_op(batch
, params
);
1845 blorp_emit_vertex_buffers(batch
, params
);
1846 blorp_emit_vertex_elements(batch
, params
);
1848 blorp_emit_pipeline(batch
, params
);
1850 blorp_emit_surface_states(batch
, params
);
1852 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1853 blorp_emit_depth_stencil_config(batch
, params
);
1855 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1856 prim
.VertexAccessType
= SEQUENTIAL
;
1857 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1859 prim
.PredicateEnable
= batch
->flags
& BLORP_BATCH_PREDICATE_ENABLE
;
1861 prim
.VertexCountPerInstance
= 3;
1862 prim
.InstanceCount
= params
->num_layers
;
1866 #endif /* BLORP_GENX_EXEC_H */