2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "common/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
32 * This file provides the blorp pipeline setup and execution functionality.
33 * It defines the following function:
36 * blorp_exec(struct blorp_context *blorp, void *batch_data,
37 * const struct blorp_params *params);
39 * It is the job of whoever includes this header to wrap this in something
40 * to get an externally visible symbol.
42 * In order for the blorp_exec function to work, the driver must provide
43 * implementations of the following static helper functions.
47 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
50 blorp_emit_reloc(struct blorp_batch
*batch
,
51 void *location
, struct blorp_address address
, uint32_t delta
);
54 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
59 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
60 struct blorp_address
*addr
);
63 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
64 unsigned state_size
, unsigned state_alignment
,
65 uint32_t *bt_offset
, uint32_t *surface_offsets
,
69 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
72 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
73 struct blorp_address address
, uint32_t delta
);
76 blorp_emit_urb_config(struct blorp_batch
*batch
, unsigned vs_entry_size
);
78 /***** BEGIN blorp_exec implementation ******/
80 #include "genxml/gen_macros.h"
83 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
84 struct blorp_address address
, uint32_t delta
)
86 if (address
.buffer
== NULL
) {
87 return address
.offset
+ delta
;
89 return blorp_emit_reloc(batch
, location
, address
, delta
);
93 #define __gen_address_type struct blorp_address
94 #define __gen_user_data struct blorp_batch
95 #define __gen_combine_address _blorp_combine_address
97 #include "genxml/genX_pack.h"
99 #define _blorp_cmd_length(cmd) cmd ## _length
100 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
101 #define _blorp_cmd_header(cmd) cmd ## _header
102 #define _blorp_cmd_pack(cmd) cmd ## _pack
104 #define blorp_emit(batch, cmd, name) \
105 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
106 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
107 __builtin_expect(_dst != NULL, 1); \
108 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
111 #define blorp_emitn(batch, cmd, n) ({ \
112 uint32_t *_dw = blorp_emit_dwords(batch, n); \
114 struct cmd template = { \
115 _blorp_cmd_header(cmd), \
116 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
118 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
120 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
123 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
125 #define blorp_emit_dynamic(batch, state, name, align, offset) \
126 for (struct state name = STRUCT_ZERO(state), \
127 *_dst = blorp_alloc_dynamic_state(batch, \
128 _blorp_cmd_length(state) * 4, \
130 __builtin_expect(_dst != NULL, 1); \
131 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
132 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
141 * Assign the entire URB to the VS. Even though the VS disabled, URB space
142 * is still needed because the clipper loads the VUE's from the URB. From
143 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
144 * Dword 1.15:0 "VS Number of URB Entries":
145 * This field is always used (even if VS Function Enable is DISABLED).
147 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
148 * safely ignore it because this batch contains only one draw call.
149 * Because of URB corruption caused by allocating a previous GS unit
150 * URB entry to the VS unit, software is required to send a “GS NULL
151 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
152 * plus a dummy DRAW call before any case where VS will be taking over
155 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
156 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
158 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
159 * programmed in order for the programming of this state to be
163 emit_urb_config(struct blorp_batch
*batch
,
164 const struct blorp_params
*params
)
166 /* Once vertex fetcher has written full VUE entries with complete
167 * header the space requirement is as follows per vertex (in bytes):
169 * Header Position Program constants
170 * +--------+------------+-------------------+
171 * | 16 | 16 | n x 16 |
172 * +--------+------------+-------------------+
174 * where 'n' stands for number of varying inputs expressed as vec4s.
176 const unsigned num_varyings
=
177 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
178 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
180 /* The URB size is expressed in units of 64 bytes (512 bits) */
181 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
183 blorp_emit_urb_config(batch
, vs_entry_size
);
187 blorp_emit_vertex_data(struct blorp_batch
*batch
,
188 const struct blorp_params
*params
,
189 struct blorp_address
*addr
,
192 const float vertices
[] = {
193 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
194 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
195 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
198 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
199 memcpy(data
, vertices
, sizeof(vertices
));
200 *size
= sizeof(vertices
);
201 blorp_flush_range(batch
, data
, *size
);
205 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
206 const struct blorp_params
*params
,
207 struct blorp_address
*addr
,
210 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
211 const unsigned max_num_varyings
=
212 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
213 const unsigned num_varyings
=
214 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
216 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
218 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
219 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
220 uint32_t *inputs
= data
;
222 /* Copy in the VS inputs */
223 assert(sizeof(params
->vs_inputs
) == 16);
224 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
227 if (params
->wm_prog_data
) {
228 /* Walk over the attribute slots, determine if the attribute is used by
229 * the program and when necessary copy the values from the input storage
230 * to the vertex data buffer.
232 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
233 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
235 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
239 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
245 blorp_flush_range(batch
, data
, *size
);
249 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
250 const struct blorp_params
*params
)
252 struct GENX(VERTEX_BUFFER_STATE
) vb
[2];
253 memset(vb
, 0, sizeof(vb
));
256 blorp_emit_vertex_data(batch
, params
, &vb
[0].BufferStartingAddress
, &size
);
257 vb
[0].VertexBufferIndex
= 0;
258 vb
[0].BufferPitch
= 3 * sizeof(float);
259 vb
[0].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
261 vb
[0].AddressModifyEnable
= true;
264 vb
[0].BufferSize
= size
;
266 vb
[0].BufferAccessType
= VERTEXDATA
;
267 vb
[0].EndAddress
= vb
[0].BufferStartingAddress
;
268 vb
[0].EndAddress
.offset
+= size
- 1;
271 blorp_emit_input_varying_data(batch
, params
,
272 &vb
[1].BufferStartingAddress
, &size
);
273 vb
[1].VertexBufferIndex
= 1;
274 vb
[1].BufferPitch
= 0;
275 vb
[1].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
277 vb
[1].AddressModifyEnable
= true;
280 vb
[1].BufferSize
= size
;
282 vb
[1].BufferAccessType
= INSTANCEDATA
;
283 vb
[1].EndAddress
= vb
[1].BufferStartingAddress
;
284 vb
[1].EndAddress
.offset
+= size
- 1;
287 const unsigned num_dwords
= 1 + GENX(VERTEX_BUFFER_STATE_length
) * 2;
288 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
292 for (unsigned i
= 0; i
< 2; i
++) {
293 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
294 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
299 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
300 const struct blorp_params
*params
)
302 const unsigned num_varyings
=
303 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
304 const unsigned num_elements
= 2 + num_varyings
;
306 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
307 memset(ve
, 0, num_elements
* sizeof(*ve
));
309 /* Setup VBO for the rectangle primitive..
311 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
312 * vertices. The vertices reside in screen space with DirectX
313 * coordinates (that is, (0, 0) is the upper left corner).
320 * Since the VS is disabled, the clipper loads each VUE directly from
321 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
322 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
323 * dw0: Reserved, MBZ.
324 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
325 * to assign this with primitive instance identifier which will be
326 * used for layered clears. All other renders have only one instance
327 * and therefore the value will be effectively zero.
328 * dw2: Viewport Index. The HiZ op disables viewport mapping and
329 * scissoring, so set the dword to 0.
330 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
331 * so set the dword to 0.
332 * dw4: Vertex Position X.
333 * dw5: Vertex Position Y.
334 * dw6: Vertex Position Z.
335 * dw7: Vertex Position W.
337 * dw8: Flat vertex input 0
338 * dw9: Flat vertex input 1
340 * dwn: Flat vertex input n - 8
342 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
343 * "Vertex URB Entry (VUE) Formats".
345 * Only vertex position X and Y are going to be variable, Z is fixed to
346 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
347 * include the fixed values in the vertex buffer. Vertex fetcher can be
348 * instructed to fill vertex elements with constant values of one and zero
349 * instead of reading them from the buffer.
350 * Flat inputs are program constants that are not interpolated. Moreover
351 * their values will be the same between vertices.
353 * See the vertex element setup below.
355 ve
[0].VertexBufferIndex
= 1;
357 ve
[0].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
358 ve
[0].SourceElementOffset
= 0;
359 ve
[0].Component0Control
= VFCOMP_STORE_SRC
;
361 /* From Gen8 onwards hardware is no more instructed to overwrite components
362 * using an element specifier. Instead one has separate 3DSTATE_VF_SGVS
363 * (System Generated Value Setup) state packet for it.
366 ve
[0].Component1Control
= VFCOMP_STORE_0
;
368 ve
[0].Component1Control
= VFCOMP_STORE_IID
;
370 ve
[0].Component2Control
= VFCOMP_STORE_SRC
;
371 ve
[0].Component3Control
= VFCOMP_STORE_SRC
;
373 ve
[1].VertexBufferIndex
= 0;
375 ve
[1].SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
;
376 ve
[1].SourceElementOffset
= 0;
377 ve
[1].Component0Control
= VFCOMP_STORE_SRC
;
378 ve
[1].Component1Control
= VFCOMP_STORE_SRC
;
379 ve
[1].Component2Control
= VFCOMP_STORE_SRC
;
380 ve
[1].Component3Control
= VFCOMP_STORE_1_FP
;
382 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
383 ve
[i
+ 2].VertexBufferIndex
= 1;
384 ve
[i
+ 2].Valid
= true;
385 ve
[i
+ 2].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
386 ve
[i
+ 2].SourceElementOffset
= 16 + i
* 4 * sizeof(float);
387 ve
[i
+ 2].Component0Control
= VFCOMP_STORE_SRC
;
388 ve
[i
+ 2].Component1Control
= VFCOMP_STORE_SRC
;
389 ve
[i
+ 2].Component2Control
= VFCOMP_STORE_SRC
;
390 ve
[i
+ 2].Component3Control
= VFCOMP_STORE_SRC
;
393 const unsigned num_dwords
=
394 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
395 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
399 for (unsigned i
= 0; i
< num_elements
; i
++) {
400 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
401 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
405 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
406 * primitive instance identifier. This is used for layered clears.
408 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
409 sgvs
.InstanceIDEnable
= true;
410 sgvs
.InstanceIDComponentNumber
= COMP_1
;
411 sgvs
.InstanceIDElementOffset
= 0;
414 for (unsigned i
= 0; i
< num_elements
; i
++) {
415 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
416 vf
.VertexElementIndex
= i
;
417 vf
.InstancingEnable
= false;
421 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
422 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
428 blorp_emit_vs_config(struct blorp_batch
*batch
,
429 const struct blorp_params
*params
)
431 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
433 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
437 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
439 vs
.DispatchGRFStartRegisterForURBData
=
440 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
441 vs
.VertexURBEntryReadLength
=
442 vs_prog_data
->base
.urb_read_length
;
443 vs
.VertexURBEntryReadOffset
= 0;
445 vs
.MaximumNumberofThreads
=
446 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
449 vs
.SIMD8DispatchEnable
=
450 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
457 blorp_emit_sf_config(struct blorp_batch
*batch
,
458 const struct blorp_params
*params
)
460 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
464 * Disable ViewportTransformEnable (dw2.1)
466 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
467 * Primitives Overview":
468 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
469 * use of screen- space coordinates).
471 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
472 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
474 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
475 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
476 * SOLID: Any triangle or rectangle object found to be front-facing
477 * is rendered as a solid object. This setting is required when
478 * (rendering rectangle (RECTLIST) objects.
483 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
485 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
486 raster
.CullMode
= CULLMODE_NONE
;
489 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
490 sbe
.VertexURBEntryReadOffset
= 1;
492 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
493 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
494 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
496 sbe
.NumberofSFOutputAttributes
= 0;
497 sbe
.VertexURBEntryReadLength
= 1;
499 sbe
.ForceVertexURBEntryReadLength
= true;
500 sbe
.ForceVertexURBEntryReadOffset
= true;
503 for (unsigned i
= 0; i
< 32; i
++)
504 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
510 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
511 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
512 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
514 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
515 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
518 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
522 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
523 sbe
.VertexURBEntryReadOffset
= 1;
525 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
526 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
527 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
529 sbe
.NumberofSFOutputAttributes
= 0;
530 sbe
.VertexURBEntryReadLength
= 1;
534 #else /* GEN_GEN <= 6 */
536 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
537 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
538 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
540 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
541 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
543 sf
.VertexURBEntryReadOffset
= 1;
545 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
546 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
547 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
549 sf
.NumberofSFOutputAttributes
= 0;
550 sf
.VertexURBEntryReadLength
= 1;
558 blorp_emit_ps_config(struct blorp_batch
*batch
,
559 const struct blorp_params
*params
)
561 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
563 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
564 * nonzero to prevent the GPU from hanging. While the documentation doesn't
565 * mention this explicitly, it notes that the valid range for the field is
566 * [1,39] = [2,40] threads, which excludes zero.
568 * To be safe (and to minimize extraneous code) we go ahead and fully
569 * configure the WM state whether or not there is a WM program.
574 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
576 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
577 if (params
->src
.enabled
) {
578 ps
.SamplerCount
= 1; /* Up to 4 samplers */
579 ps
.BindingTableEntryCount
= 2;
581 ps
.BindingTableEntryCount
= 1;
585 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
586 prog_data
->base
.dispatch_grf_start_reg
;
587 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
588 prog_data
->dispatch_grf_start_reg_2
;
590 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
591 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
593 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
594 ps
.KernelStartPointer2
=
595 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
598 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
599 * it implicitly scales for different GT levels (which have some # of
602 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
605 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
607 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
609 switch (params
->fast_clear_op
) {
610 case BLORP_FAST_CLEAR_OP_NONE
:
613 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
614 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
616 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
617 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
620 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
621 ps
.RenderTargetResolveEnable
= true;
624 case BLORP_FAST_CLEAR_OP_CLEAR
:
625 ps
.RenderTargetFastClearEnable
= true;
628 unreachable("Invalid fast clear op");
632 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
634 psx
.PixelShaderValid
= true;
635 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
636 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
639 if (params
->src
.enabled
)
640 psx
.PixelShaderKillsPixel
= true;
645 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
646 switch (params
->hiz_op
) {
647 case BLORP_HIZ_OP_DEPTH_CLEAR
:
648 wm
.DepthBufferClear
= true;
650 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
651 wm
.DepthBufferResolveEnable
= true;
653 case BLORP_HIZ_OP_HIZ_RESOLVE
:
654 wm
.HierarchicalDepthBufferResolveEnable
= true;
656 case BLORP_HIZ_OP_NONE
:
659 unreachable("not reached");
663 wm
.ThreadDispatchEnable
= true;
665 if (params
->src
.enabled
)
666 wm
.PixelShaderKillsPixel
= true;
668 if (params
->num_samples
> 1) {
669 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
670 wm
.MultisampleDispatchMode
=
671 (prog_data
&& prog_data
->persample_dispatch
) ?
672 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
674 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
675 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
679 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
680 ps
.MaximumNumberofThreads
=
681 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
688 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
689 prog_data
->base
.dispatch_grf_start_reg
;
690 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
691 prog_data
->dispatch_grf_start_reg_2
;
693 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
694 ps
.KernelStartPointer2
=
695 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
697 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
698 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
700 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
702 /* Gen7 hardware gets angry if we don't enable at least one dispatch
703 * mode, so just enable 16-pixel dispatch if we don't have a program.
705 ps
._16PixelDispatchEnable
= true;
708 if (params
->src
.enabled
)
709 ps
.SamplerCount
= 1; /* Up to 4 samplers */
711 switch (params
->fast_clear_op
) {
712 case BLORP_FAST_CLEAR_OP_NONE
:
714 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
715 ps
.RenderTargetResolveEnable
= true;
717 case BLORP_FAST_CLEAR_OP_CLEAR
:
718 ps
.RenderTargetFastClearEnable
= true;
721 unreachable("Invalid fast clear op");
725 #else /* GEN_GEN <= 6 */
727 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
728 wm
.MaximumNumberofThreads
=
729 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
731 switch (params
->hiz_op
) {
732 case BLORP_HIZ_OP_DEPTH_CLEAR
:
733 wm
.DepthBufferClear
= true;
735 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
736 wm
.DepthBufferResolveEnable
= true;
738 case BLORP_HIZ_OP_HIZ_RESOLVE
:
739 wm
.HierarchicalDepthBufferResolveEnable
= true;
741 case BLORP_HIZ_OP_NONE
:
744 unreachable("not reached");
748 wm
.ThreadDispatchEnable
= true;
750 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
751 prog_data
->base
.dispatch_grf_start_reg
;
752 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
753 prog_data
->dispatch_grf_start_reg_2
;
755 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
756 wm
.KernelStartPointer2
=
757 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
759 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
760 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
762 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
765 if (params
->src
.enabled
) {
766 wm
.SamplerCount
= 1; /* Up to 4 samplers */
767 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
770 if (params
->num_samples
> 1) {
771 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
772 wm
.MultisampleDispatchMode
=
773 (prog_data
&& prog_data
->persample_dispatch
) ?
774 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
776 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
777 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
784 static const uint32_t isl_to_gen_ds_surftype
[] = {
786 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
788 * "If depth/stencil is enabled with 1D render target, depth/stencil
789 * surface type needs to be set to 2D surface type and height set to 1.
790 * Depth will use (legacy) TileY and stencil will use TileW. For this
791 * case only, the Surface Type of the depth buffer can be 2D while the
792 * Surface Type of the render target(s) are 1D, representing an
793 * exception to a programming note above.
795 [ISL_SURF_DIM_1D
] = SURFTYPE_2D
,
797 [ISL_SURF_DIM_1D
] = SURFTYPE_1D
,
799 [ISL_SURF_DIM_2D
] = SURFTYPE_2D
,
800 [ISL_SURF_DIM_3D
] = SURFTYPE_3D
,
804 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
805 const struct blorp_params
*params
)
807 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
809 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
813 struct isl_depth_stencil_hiz_emit_info info
= {
815 .mocs
= 1, /* GEN7_MOCS_L3 */
821 if (params
->depth
.enabled
) {
822 info
.view
= ¶ms
->depth
.view
;
823 } else if (params
->stencil
.enabled
) {
824 info
.view
= ¶ms
->stencil
.view
;
827 if (params
->depth
.enabled
) {
828 info
.depth_surf
= ¶ms
->depth
.surf
;
831 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
832 params
->depth
.addr
, 0);
834 info
.hiz_usage
= params
->depth
.aux_usage
;
835 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
836 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
839 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
840 params
->depth
.aux_addr
, 0);
842 info
.depth_clear_value
= params
->depth
.clear_color
.u32
[0];
846 if (params
->stencil
.enabled
) {
847 info
.stencil_surf
= ¶ms
->stencil
.surf
;
849 info
.stencil_address
=
850 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
851 params
->stencil
.addr
, 0);
854 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
858 blorp_emit_blend_state(struct blorp_batch
*batch
,
859 const struct blorp_params
*params
)
861 struct GENX(BLEND_STATE
) blend
;
862 memset(&blend
, 0, sizeof(blend
));
865 int size
= GENX(BLEND_STATE_length
) * 4;
866 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
867 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
868 uint32_t *pos
= state
;
870 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
871 pos
+= GENX(BLEND_STATE_length
);
873 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
874 struct GENX(BLEND_STATE_ENTRY
) entry
= {
875 .PreBlendColorClampEnable
= true,
876 .PostBlendColorClampEnable
= true,
877 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
879 .WriteDisableRed
= params
->color_write_disable
[0],
880 .WriteDisableGreen
= params
->color_write_disable
[1],
881 .WriteDisableBlue
= params
->color_write_disable
[2],
882 .WriteDisableAlpha
= params
->color_write_disable
[3],
884 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
885 pos
+= GENX(BLEND_STATE_ENTRY_length
);
888 blorp_flush_range(batch
, state
, size
);
891 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
892 sp
.BlendStatePointer
= offset
;
894 sp
.BlendStatePointerValid
= true;
900 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
901 ps_blend
.HasWriteableRT
= true;
909 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
910 const struct blorp_params
*params
)
913 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
915 cc
.StencilReferenceValue
= params
->stencil_ref
;
920 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
921 sp
.ColorCalcStatePointer
= offset
;
923 sp
.ColorCalcStatePointerValid
= true;
932 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
933 const struct blorp_params
*params
)
936 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
937 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
940 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
943 if (params
->depth
.enabled
) {
944 ds
.DepthBufferWriteEnable
= true;
946 switch (params
->hiz_op
) {
947 case BLORP_HIZ_OP_NONE
:
948 ds
.DepthTestEnable
= true;
949 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
952 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
953 * - 7.5.3.1 Depth Buffer Clear
954 * - 7.5.3.2 Depth Buffer Resolve
955 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
957 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
958 ds
.DepthTestEnable
= true;
959 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
962 case BLORP_HIZ_OP_DEPTH_CLEAR
:
963 case BLORP_HIZ_OP_HIZ_RESOLVE
:
964 ds
.DepthTestEnable
= false;
969 if (params
->stencil
.enabled
) {
970 ds
.StencilBufferWriteEnable
= true;
971 ds
.StencilTestEnable
= true;
972 ds
.DoubleSidedStencilEnable
= false;
974 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
975 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
977 ds
.StencilWriteMask
= params
->stencil_mask
;
979 ds
.StencilReferenceValue
= params
->stencil_ref
;
985 uint32_t *dw
= blorp_emit_dwords(batch
,
986 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
990 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
993 void *state
= blorp_alloc_dynamic_state(batch
,
994 GENX(DEPTH_STENCIL_STATE_length
) * 4,
996 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
997 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1001 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1002 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1010 blorp_emit_surface_state(struct blorp_batch
*batch
,
1011 const struct brw_blorp_surface_info
*surface
,
1012 void *state
, uint32_t state_offset
,
1013 bool is_render_target
)
1015 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1016 struct isl_surf surf
= surface
->surf
;
1018 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1019 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1020 assert(surf
.logical_level0_px
.height
== 1);
1021 surf
.dim
= ISL_SURF_DIM_2D
;
1024 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1025 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1026 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1027 aux_usage
= ISL_AUX_USAGE_NONE
;
1029 const uint32_t mocs
=
1030 is_render_target
? batch
->blorp
->mocs
.rb
: batch
->blorp
->mocs
.tex
;
1032 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1033 .surf
= &surf
, .view
= &surface
->view
,
1034 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1035 .mocs
= mocs
, .clear_color
= surface
->clear_color
);
1037 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1040 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1041 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1042 * used to store other information. This should be ok, however, because
1043 * surface buffer addresses are always 4K page alinged.
1045 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1046 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1047 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1048 surface
->aux_addr
, *aux_addr
);
1051 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1055 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1056 const struct brw_blorp_surface_info
*surface
,
1059 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1060 .SurfaceType
= SURFTYPE_NULL
,
1061 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1062 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1063 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1064 .MIPCountLOD
= surface
->view
.base_level
,
1065 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1066 .Depth
= surface
->view
.array_len
- 1,
1067 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1068 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1071 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1077 .TiledSurface
= true,
1081 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1083 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1087 blorp_emit_surface_states(struct blorp_batch
*batch
,
1088 const struct blorp_params
*params
)
1090 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1091 uint32_t bind_offset
, surface_offsets
[2];
1092 void *surface_maps
[2];
1094 if (params
->use_pre_baked_binding_table
) {
1095 bind_offset
= params
->pre_baked_binding_table_offset
;
1097 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1098 blorp_alloc_binding_table(batch
, num_surfaces
,
1099 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1100 &bind_offset
, surface_offsets
, surface_maps
);
1102 if (params
->dst
.enabled
) {
1103 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1104 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1105 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1108 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1109 const struct brw_blorp_surface_info
*surface
=
1110 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1111 blorp_emit_null_surface_state(batch
, surface
,
1112 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1115 if (params
->src
.enabled
) {
1116 blorp_emit_surface_state(batch
, ¶ms
->src
,
1117 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1118 surface_offsets
[BLORP_TEXTURE_BT_INDEX
], false);
1123 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1124 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1125 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1126 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1128 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1129 bt
.PointertoPSBindingTable
= bind_offset
;
1132 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1133 bt
.PSBindingTableChange
= true;
1134 bt
.PointertoPSBindingTable
= bind_offset
;
1140 blorp_emit_sampler_state(struct blorp_batch
*batch
,
1141 const struct blorp_params
*params
)
1144 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
1145 sampler
.MipModeFilter
= MIPFILTER_NONE
;
1146 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
1147 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
1150 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
1151 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
1152 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
1153 sampler
.MaximumAnisotropy
= RATIO21
;
1154 sampler
.RAddressMinFilterRoundingEnable
= true;
1155 sampler
.RAddressMagFilterRoundingEnable
= true;
1156 sampler
.VAddressMinFilterRoundingEnable
= true;
1157 sampler
.VAddressMagFilterRoundingEnable
= true;
1158 sampler
.UAddressMinFilterRoundingEnable
= true;
1159 sampler
.UAddressMagFilterRoundingEnable
= true;
1160 sampler
.NonnormalizedCoordinateEnable
= true;
1164 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
1165 ssp
.PointertoPSSamplerState
= offset
;
1168 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
1169 ssp
.VSSamplerStateChange
= true;
1170 ssp
.GSSamplerStateChange
= true;
1171 ssp
.PSSamplerStateChange
= true;
1172 ssp
.PointertoPSSamplerState
= offset
;
1178 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1179 const struct blorp_params
*params
)
1181 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1182 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1185 /* The PRM says that this bit is valid only for DX9:
1187 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1188 * should not have any effect by setting or not setting this bit.
1190 ms
.PixelPositionOffsetEnable
= false;
1193 switch (params
->num_samples
) {
1195 GEN_SAMPLE_POS_1X(ms
.Sample
);
1198 GEN_SAMPLE_POS_2X(ms
.Sample
);
1201 GEN_SAMPLE_POS_4X(ms
.Sample
);
1204 GEN_SAMPLE_POS_8X(ms
.Sample
);
1210 GEN_SAMPLE_POS_4X(ms
.Sample
);
1212 ms
.PixelLocation
= CENTER
;
1217 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1218 * depth/stencil buffer extents are ignored to handle APIs which perform
1219 * clearing operations without such information.
1222 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1223 const struct blorp_params
*params
)
1225 /* We should be performing an operation on a depth or stencil buffer.
1227 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1229 /* The stencil buffer should only be enabled if a fast clear operation is
1232 if (params
->stencil
.enabled
)
1233 assert(params
->hiz_op
== BLORP_HIZ_OP_DEPTH_CLEAR
);
1235 /* If we can't alter the depth stencil config and multiple layers are
1236 * involved, the HiZ op will fail. This is because the op requires that a
1237 * new config is emitted for each additional layer.
1239 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1240 assert(params
->num_layers
<= 1);
1242 blorp_emit_depth_stencil_config(batch
, params
);
1245 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1246 switch (params
->hiz_op
) {
1247 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1248 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1249 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1250 hzp
.StencilClearValue
= params
->stencil_ref
;
1252 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1253 hzp
.DepthBufferResolveEnable
= true;
1255 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1256 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1258 case BLORP_HIZ_OP_NONE
:
1259 unreachable("Invalid HIZ op");
1262 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1263 hzp
.SampleMask
= 0xFFFF;
1265 /* Due to a hardware issue, this bit MBZ */
1266 assert(hzp
.ScissorRectangleEnable
== false);
1268 /* Contrary to the HW docs both fields are inclusive */
1269 hzp
.ClearRectangleXMin
= params
->x0
;
1270 hzp
.ClearRectangleYMin
= params
->y0
;
1272 /* Contrary to the HW docs both fields are exclusive */
1273 hzp
.ClearRectangleXMax
= params
->x1
;
1274 hzp
.ClearRectangleYMax
= params
->y1
;
1277 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1278 * to “Write Immediate Data” enabled.
1280 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1281 pc
.PostSyncOperation
= WriteImmediateData
;
1284 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1286 /* Perform depth clear specific flushing */
1287 if (params
->hiz_op
== BLORP_HIZ_OP_DEPTH_CLEAR
&& params
->depth
.enabled
) {
1288 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1289 pc
.DepthStallEnable
= true;
1290 pc
.DepthCacheFlushEnable
= true;
1296 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
1298 blorp_emit_viewport_state(struct blorp_batch
*batch
,
1299 const struct blorp_params
*params
)
1301 uint32_t cc_vp_offset
;
1302 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
1303 vp
.MinimumDepth
= 0.0;
1304 vp
.MaximumDepth
= 1.0;
1308 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
1309 vsp
.CCViewportPointer
= cc_vp_offset
;
1312 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
1313 vsp
.CCViewportStateChange
= true;
1314 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
1321 * \brief Execute a blit or render pass operation.
1323 * To execute the operation, this function manually constructs and emits a
1324 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1325 * constructing and after emitting the batch.
1327 * This function alters no GL state.
1330 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1332 uint32_t blend_state_offset
= 0;
1333 uint32_t color_calc_state_offset
= 0;
1334 uint32_t depth_stencil_state_offset
;
1337 if (params
->hiz_op
!= BLORP_HIZ_OP_NONE
) {
1338 blorp_emit_gen8_hiz_op(batch
, params
);
1343 blorp_emit_vertex_buffers(batch
, params
);
1344 blorp_emit_vertex_elements(batch
, params
);
1346 emit_urb_config(batch
, params
);
1348 if (params
->wm_prog_data
) {
1349 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1351 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1352 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1355 /* 3DSTATE_CC_STATE_POINTERS
1357 * The pointer offsets are relative to
1358 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1360 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1362 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1363 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1364 * one CC_STATE_POINTERS packet so we have to emit that here.
1366 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1367 cc
.BLEND_STATEChange
= true;
1368 cc
.ColorCalcStatePointerValid
= true;
1369 cc
.DEPTH_STENCIL_STATEChange
= true;
1370 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1371 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1372 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1375 (void)blend_state_offset
;
1376 (void)color_calc_state_offset
;
1377 (void)depth_stencil_state_offset
;
1380 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1382 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1383 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1385 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1386 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1388 blorp_emit_surface_states(batch
, params
);
1390 if (params
->src
.enabled
)
1391 blorp_emit_sampler_state(batch
, params
);
1393 blorp_emit_3dstate_multisample(batch
, params
);
1395 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1396 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1399 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1400 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1402 * [DevSNB] A pipeline flush must be programmed prior to a
1403 * 3DSTATE_VS command that causes the VS Function Enable to
1404 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1405 * command with CS stall bit set and a post sync operation.
1407 * We've already done one at the start of the BLORP operation.
1409 blorp_emit_vs_config(batch
, params
);
1411 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1412 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1413 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1414 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1416 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1418 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1419 clip
.PerspectiveDivideDisable
= true;
1422 blorp_emit_sf_config(batch
, params
);
1423 blorp_emit_ps_config(batch
, params
);
1425 blorp_emit_viewport_state(batch
, params
);
1427 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1428 blorp_emit_depth_stencil_config(batch
, params
);
1430 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1431 prim
.VertexAccessType
= SEQUENTIAL
;
1432 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1433 prim
.VertexCountPerInstance
= 3;
1434 prim
.InstanceCount
= params
->num_layers
;
1438 #endif /* BLORP_GENX_EXEC_H */