2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "dev/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "genxml/gen_macros.h"
33 * This file provides the blorp pipeline setup and execution functionality.
34 * It defines the following function:
37 * blorp_exec(struct blorp_context *blorp, void *batch_data,
38 * const struct blorp_params *params);
40 * It is the job of whoever includes this header to wrap this in something
41 * to get an externally visible symbol.
43 * In order for the blorp_exec function to work, the driver must provide
44 * implementations of the following static helper functions.
48 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
51 blorp_emit_reloc(struct blorp_batch
*batch
,
52 void *location
, struct blorp_address address
, uint32_t delta
);
55 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
60 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
61 struct blorp_address
*addr
);
63 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch
*batch
,
64 const struct blorp_address
*addrs
,
68 static struct blorp_address
69 blorp_get_workaround_page(struct blorp_batch
*batch
);
73 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
74 unsigned state_size
, unsigned state_alignment
,
75 uint32_t *bt_offset
, uint32_t *surface_offsets
,
79 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
82 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
83 struct blorp_address address
, uint32_t delta
);
86 blorp_get_surface_address(struct blorp_batch
*batch
,
87 struct blorp_address address
);
89 #if GEN_GEN >= 7 && GEN_GEN < 10
90 static struct blorp_address
91 blorp_get_surface_base_address(struct blorp_batch
*batch
);
95 blorp_emit_urb_config(struct blorp_batch
*batch
,
96 unsigned vs_entry_size
, unsigned sf_entry_size
);
99 blorp_emit_pipeline(struct blorp_batch
*batch
,
100 const struct blorp_params
*params
);
102 /***** BEGIN blorp_exec implementation ******/
105 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
106 struct blorp_address address
, uint32_t delta
)
108 if (address
.buffer
== NULL
) {
109 return address
.offset
+ delta
;
111 return blorp_emit_reloc(batch
, location
, address
, delta
);
115 #define __gen_address_type struct blorp_address
116 #define __gen_user_data struct blorp_batch
117 #define __gen_combine_address _blorp_combine_address
119 #include "genxml/genX_pack.h"
121 #define _blorp_cmd_length(cmd) cmd ## _length
122 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
123 #define _blorp_cmd_header(cmd) cmd ## _header
124 #define _blorp_cmd_pack(cmd) cmd ## _pack
126 #define blorp_emit(batch, cmd, name) \
127 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
128 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
129 __builtin_expect(_dst != NULL, 1); \
130 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
133 #define blorp_emitn(batch, cmd, n) ({ \
134 uint32_t *_dw = blorp_emit_dwords(batch, n); \
136 struct cmd template = { \
137 _blorp_cmd_header(cmd), \
138 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
140 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
142 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
145 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
147 #define blorp_emit_dynamic(batch, state, name, align, offset) \
148 for (struct state name = STRUCT_ZERO(state), \
149 *_dst = blorp_alloc_dynamic_state(batch, \
150 _blorp_cmd_length(state) * 4, \
152 __builtin_expect(_dst != NULL, 1); \
153 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
154 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
163 * Assign the entire URB to the VS. Even though the VS disabled, URB space
164 * is still needed because the clipper loads the VUE's from the URB. From
165 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
166 * Dword 1.15:0 "VS Number of URB Entries":
167 * This field is always used (even if VS Function Enable is DISABLED).
169 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
170 * safely ignore it because this batch contains only one draw call.
171 * Because of URB corruption caused by allocating a previous GS unit
172 * URB entry to the VS unit, software is required to send a “GS NULL
173 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
174 * plus a dummy DRAW call before any case where VS will be taking over
177 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
178 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
180 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
181 * programmed in order for the programming of this state to be
185 emit_urb_config(struct blorp_batch
*batch
,
186 const struct blorp_params
*params
)
188 /* Once vertex fetcher has written full VUE entries with complete
189 * header the space requirement is as follows per vertex (in bytes):
191 * Header Position Program constants
192 * +--------+------------+-------------------+
193 * | 16 | 16 | n x 16 |
194 * +--------+------------+-------------------+
196 * where 'n' stands for number of varying inputs expressed as vec4s.
198 const unsigned num_varyings
=
199 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
200 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
202 /* The URB size is expressed in units of 64 bytes (512 bits) */
203 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
205 const unsigned sf_entry_size
=
206 params
->sf_prog_data
? params
->sf_prog_data
->urb_entry_size
: 0;
208 blorp_emit_urb_config(batch
, vs_entry_size
, sf_entry_size
);
213 blorp_emit_memcpy(struct blorp_batch
*batch
,
214 struct blorp_address dst
,
215 struct blorp_address src
,
220 blorp_emit_vertex_data(struct blorp_batch
*batch
,
221 const struct blorp_params
*params
,
222 struct blorp_address
*addr
,
225 const float vertices
[] = {
226 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
227 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
228 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
231 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
232 memcpy(data
, vertices
, sizeof(vertices
));
233 *size
= sizeof(vertices
);
234 blorp_flush_range(batch
, data
, *size
);
238 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
239 const struct blorp_params
*params
,
240 struct blorp_address
*addr
,
243 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
244 const unsigned max_num_varyings
=
245 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
246 const unsigned num_varyings
=
247 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
249 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
251 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
252 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
253 uint32_t *inputs
= data
;
255 /* Copy in the VS inputs */
256 assert(sizeof(params
->vs_inputs
) == 16);
257 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
260 if (params
->wm_prog_data
) {
261 /* Walk over the attribute slots, determine if the attribute is used by
262 * the program and when necessary copy the values from the input storage
263 * to the vertex data buffer.
265 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
266 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
268 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
272 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
278 blorp_flush_range(batch
, data
, *size
);
280 if (params
->dst_clear_color_as_input
) {
282 /* In this case, the clear color isn't known statically and instead
283 * comes in through an indirect which we have to copy into the vertex
284 * buffer before we execute the 3DPRIMITIVE. We already copied the
285 * value of params->wm_inputs.clear_color into the vertex buffer in the
286 * loop above. Now we emit code to stomp it from the GPU with the
287 * actual clear color value.
289 assert(num_varyings
== 1);
291 /* The clear color is the first thing after the header */
292 struct blorp_address clear_color_input_addr
= *addr
;
293 clear_color_input_addr
.offset
+= 16;
295 const unsigned clear_color_size
=
296 GEN_GEN
< 10 ? batch
->blorp
->isl_dev
->ss
.clear_value_size
: 4 * 4;
297 blorp_emit_memcpy(batch
, clear_color_input_addr
,
298 params
->dst
.clear_color_addr
,
301 unreachable("MCS partial resolve is not a thing on SNB and earlier");
307 blorp_fill_vertex_buffer_state(struct blorp_batch
*batch
,
308 struct GENX(VERTEX_BUFFER_STATE
) *vb
,
310 struct blorp_address addr
, uint32_t size
,
313 vb
[idx
].VertexBufferIndex
= idx
;
314 vb
[idx
].BufferStartingAddress
= addr
;
315 vb
[idx
].BufferPitch
= stride
;
318 vb
[idx
].MOCS
= addr
.mocs
;
322 vb
[idx
].AddressModifyEnable
= true;
326 vb
[idx
].BufferSize
= size
;
328 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
329 vb
[idx
].EndAddress
= vb
[idx
].BufferStartingAddress
;
330 vb
[idx
].EndAddress
.offset
+= size
- 1;
332 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
333 vb
[idx
].MaxIndex
= stride
> 0 ? size
/ stride
: 0;
338 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
339 const struct blorp_params
*params
)
341 struct GENX(VERTEX_BUFFER_STATE
) vb
[3];
342 uint32_t num_vbs
= 2;
343 memset(vb
, 0, sizeof(vb
));
345 struct blorp_address addrs
[2] = {};
347 blorp_emit_vertex_data(batch
, params
, &addrs
[0], &size
);
348 blorp_fill_vertex_buffer_state(batch
, vb
, 0, addrs
[0], size
,
351 blorp_emit_input_varying_data(batch
, params
, &addrs
[1], &size
);
352 blorp_fill_vertex_buffer_state(batch
, vb
, 1, addrs
[1], size
, 0);
354 blorp_vf_invalidate_for_vb_48b_transitions(batch
, addrs
, num_vbs
);
356 const unsigned num_dwords
= 1 + num_vbs
* GENX(VERTEX_BUFFER_STATE_length
);
357 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
361 for (unsigned i
= 0; i
< num_vbs
; i
++) {
362 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
363 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
368 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
369 const struct blorp_params
*params
)
371 const unsigned num_varyings
=
372 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
373 bool need_ndc
= batch
->blorp
->compiler
->devinfo
->gen
<= 5;
374 const unsigned num_elements
= 2 + need_ndc
+ num_varyings
;
376 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
377 memset(ve
, 0, num_elements
* sizeof(*ve
));
379 /* Setup VBO for the rectangle primitive..
381 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
382 * vertices. The vertices reside in screen space with DirectX
383 * coordinates (that is, (0, 0) is the upper left corner).
390 * Since the VS is disabled, the clipper loads each VUE directly from
391 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
392 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
393 * dw0: Reserved, MBZ.
394 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
395 * to assign this with primitive instance identifier which will be
396 * used for layered clears. All other renders have only one instance
397 * and therefore the value will be effectively zero.
398 * dw2: Viewport Index. The HiZ op disables viewport mapping and
399 * scissoring, so set the dword to 0.
400 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
401 * so set the dword to 0.
402 * dw4: Vertex Position X.
403 * dw5: Vertex Position Y.
404 * dw6: Vertex Position Z.
405 * dw7: Vertex Position W.
407 * dw8: Flat vertex input 0
408 * dw9: Flat vertex input 1
410 * dwn: Flat vertex input n - 8
412 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
413 * "Vertex URB Entry (VUE) Formats".
415 * Only vertex position X and Y are going to be variable, Z is fixed to
416 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
417 * include the fixed values in the vertex buffer. Vertex fetcher can be
418 * instructed to fill vertex elements with constant values of one and zero
419 * instead of reading them from the buffer.
420 * Flat inputs are program constants that are not interpolated. Moreover
421 * their values will be the same between vertices.
423 * See the vertex element setup below.
427 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
428 .VertexBufferIndex
= 1,
430 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
431 .SourceElementOffset
= 0,
432 .Component0Control
= VFCOMP_STORE_SRC
,
434 /* From Gen8 onwards hardware is no more instructed to overwrite
435 * components using an element specifier. Instead one has separate
436 * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it.
439 .Component1Control
= VFCOMP_STORE_0
,
441 .Component1Control
= VFCOMP_STORE_IID
,
443 .Component1Control
= VFCOMP_STORE_0
,
445 .Component2Control
= VFCOMP_STORE_0
,
446 .Component3Control
= VFCOMP_STORE_0
,
448 .DestinationElementOffset
= slot
* 4,
454 /* On Iron Lake and earlier, a native device coordinates version of the
455 * position goes right after the normal VUE header and before position.
456 * Since w == 1 for all of our coordinates, this is just a copy of the
459 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
460 .VertexBufferIndex
= 0,
462 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
463 .SourceElementOffset
= 0,
464 .Component0Control
= VFCOMP_STORE_SRC
,
465 .Component1Control
= VFCOMP_STORE_SRC
,
466 .Component2Control
= VFCOMP_STORE_SRC
,
467 .Component3Control
= VFCOMP_STORE_1_FP
,
468 .DestinationElementOffset
= slot
* 4,
473 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
474 .VertexBufferIndex
= 0,
476 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
477 .SourceElementOffset
= 0,
478 .Component0Control
= VFCOMP_STORE_SRC
,
479 .Component1Control
= VFCOMP_STORE_SRC
,
480 .Component2Control
= VFCOMP_STORE_SRC
,
481 .Component3Control
= VFCOMP_STORE_1_FP
,
483 .DestinationElementOffset
= slot
* 4,
488 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
489 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
490 .VertexBufferIndex
= 1,
492 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
493 .SourceElementOffset
= 16 + i
* 4 * sizeof(float),
494 .Component0Control
= VFCOMP_STORE_SRC
,
495 .Component1Control
= VFCOMP_STORE_SRC
,
496 .Component2Control
= VFCOMP_STORE_SRC
,
497 .Component3Control
= VFCOMP_STORE_SRC
,
499 .DestinationElementOffset
= slot
* 4,
505 const unsigned num_dwords
=
506 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
507 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
511 for (unsigned i
= 0; i
< num_elements
; i
++) {
512 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
513 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
516 blorp_emit(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
517 vf
.StatisticsEnable
= false;
521 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
522 * primitive instance identifier. This is used for layered clears.
524 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
525 sgvs
.InstanceIDEnable
= true;
526 sgvs
.InstanceIDComponentNumber
= COMP_1
;
527 sgvs
.InstanceIDElementOffset
= 0;
530 for (unsigned i
= 0; i
< num_elements
; i
++) {
531 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
532 vf
.VertexElementIndex
= i
;
533 vf
.InstancingEnable
= false;
537 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
538 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
543 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
545 blorp_emit_cc_viewport(struct blorp_batch
*batch
)
547 uint32_t cc_vp_offset
;
548 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
549 vp
.MinimumDepth
= 0.0;
550 vp
.MaximumDepth
= 1.0;
554 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
555 vsp
.CCViewportPointer
= cc_vp_offset
;
558 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
559 vsp
.CCViewportStateChange
= true;
560 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
568 blorp_emit_sampler_state(struct blorp_batch
*batch
)
571 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
572 sampler
.MipModeFilter
= MIPFILTER_NONE
;
573 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
574 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
577 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
578 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
579 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
580 sampler
.MaximumAnisotropy
= RATIO21
;
581 sampler
.RAddressMinFilterRoundingEnable
= true;
582 sampler
.RAddressMagFilterRoundingEnable
= true;
583 sampler
.VAddressMinFilterRoundingEnable
= true;
584 sampler
.VAddressMagFilterRoundingEnable
= true;
585 sampler
.UAddressMinFilterRoundingEnable
= true;
586 sampler
.UAddressMagFilterRoundingEnable
= true;
588 sampler
.NonnormalizedCoordinateEnable
= true;
593 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
594 ssp
.PointertoPSSamplerState
= offset
;
597 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
598 ssp
.VSSamplerStateChange
= true;
599 ssp
.GSSamplerStateChange
= true;
600 ssp
.PSSamplerStateChange
= true;
601 ssp
.PointertoPSSamplerState
= offset
;
608 /* What follows is the code for setting up a "pipeline" on Sandy Bridge and
609 * later hardware. This file will be included by i965 for gen4-5 as well, so
610 * this code is guarded by GEN_GEN >= 6.
615 blorp_emit_vs_config(struct blorp_batch
*batch
,
616 const struct blorp_params
*params
)
618 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
619 assert(!vs_prog_data
|| GEN_GEN
< 11 ||
620 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
622 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
626 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
628 vs
.DispatchGRFStartRegisterForURBData
=
629 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
630 vs
.VertexURBEntryReadLength
=
631 vs_prog_data
->base
.urb_read_length
;
632 vs
.VertexURBEntryReadOffset
= 0;
634 vs
.MaximumNumberofThreads
=
635 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
638 vs
.SIMD8DispatchEnable
=
639 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
646 blorp_emit_sf_config(struct blorp_batch
*batch
,
647 const struct blorp_params
*params
)
649 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
653 * Disable ViewportTransformEnable (dw2.1)
655 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
656 * Primitives Overview":
657 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
658 * use of screen- space coordinates).
660 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
661 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
663 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
664 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
665 * SOLID: Any triangle or rectangle object found to be front-facing
666 * is rendered as a solid object. This setting is required when
667 * (rendering rectangle (RECTLIST) objects.
672 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
674 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
675 raster
.CullMode
= CULLMODE_NONE
;
678 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
679 sbe
.VertexURBEntryReadOffset
= 1;
681 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
682 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
683 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
685 sbe
.NumberofSFOutputAttributes
= 0;
686 sbe
.VertexURBEntryReadLength
= 1;
688 sbe
.ForceVertexURBEntryReadLength
= true;
689 sbe
.ForceVertexURBEntryReadOffset
= true;
692 for (unsigned i
= 0; i
< 32; i
++)
693 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
699 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
700 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
701 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
703 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
704 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
707 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
711 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
712 sbe
.VertexURBEntryReadOffset
= 1;
714 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
715 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
716 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
718 sbe
.NumberofSFOutputAttributes
= 0;
719 sbe
.VertexURBEntryReadLength
= 1;
723 #else /* GEN_GEN <= 6 */
725 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
726 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
727 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
729 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
730 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
732 sf
.VertexURBEntryReadOffset
= 1;
734 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
735 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
736 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
738 sf
.NumberofSFOutputAttributes
= 0;
739 sf
.VertexURBEntryReadLength
= 1;
747 blorp_emit_ps_config(struct blorp_batch
*batch
,
748 const struct blorp_params
*params
)
750 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
752 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
753 * nonzero to prevent the GPU from hanging. While the documentation doesn't
754 * mention this explicitly, it notes that the valid range for the field is
755 * [1,39] = [2,40] threads, which excludes zero.
757 * To be safe (and to minimize extraneous code) we go ahead and fully
758 * configure the WM state whether or not there is a WM program.
763 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
765 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
766 if (params
->src
.enabled
) {
767 ps
.SamplerCount
= 1; /* Up to 4 samplers */
768 ps
.BindingTableEntryCount
= 2;
770 ps
.BindingTableEntryCount
= 1;
773 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
774 * disable prefetching of binding tables on A0 and B0 steppings.
775 * TODO: Revisit this WA on C0 stepping.
778 ps
.BindingTableEntryCount
= 0;
781 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
782 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
783 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
785 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
787 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
788 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
790 * Since 16x MSAA is first introduced on SKL, we don't need to apply
791 * the workaround on any older hardware.
793 if (GEN_GEN
>= 9 && !prog_data
->persample_dispatch
&&
794 params
->num_samples
== 16) {
795 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
796 ps
._32PixelDispatchEnable
= false;
799 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
800 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
801 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
802 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
803 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
804 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
806 ps
.KernelStartPointer0
= params
->wm_prog_kernel
+
807 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
808 ps
.KernelStartPointer1
= params
->wm_prog_kernel
+
809 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
810 ps
.KernelStartPointer2
= params
->wm_prog_kernel
+
811 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
814 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
815 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
816 * k, it implies 2(k+1) threads. It implicitly scales for different GT
817 * levels (which have some # of PSDs).
819 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
822 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
824 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
826 switch (params
->fast_clear_op
) {
827 case ISL_AUX_OP_NONE
:
830 case ISL_AUX_OP_PARTIAL_RESOLVE
:
831 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
833 case ISL_AUX_OP_FULL_RESOLVE
:
834 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
837 case ISL_AUX_OP_FULL_RESOLVE
:
838 ps
.RenderTargetResolveEnable
= true;
841 case ISL_AUX_OP_FAST_CLEAR
:
842 ps
.RenderTargetFastClearEnable
= true;
845 unreachable("Invalid fast clear op");
849 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
851 psx
.PixelShaderValid
= true;
852 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
853 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
856 if (params
->src
.enabled
)
857 psx
.PixelShaderKillsPixel
= true;
862 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
863 switch (params
->hiz_op
) {
864 case ISL_AUX_OP_FAST_CLEAR
:
865 wm
.DepthBufferClear
= true;
867 case ISL_AUX_OP_FULL_RESOLVE
:
868 wm
.DepthBufferResolveEnable
= true;
870 case ISL_AUX_OP_AMBIGUATE
:
871 wm
.HierarchicalDepthBufferResolveEnable
= true;
873 case ISL_AUX_OP_NONE
:
876 unreachable("not reached");
880 wm
.ThreadDispatchEnable
= true;
882 if (params
->src
.enabled
)
883 wm
.PixelShaderKillsPixel
= true;
885 if (params
->num_samples
> 1) {
886 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
887 wm
.MultisampleDispatchMode
=
888 (prog_data
&& prog_data
->persample_dispatch
) ?
889 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
891 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
892 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
896 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
897 ps
.MaximumNumberofThreads
=
898 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
905 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
906 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
907 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
909 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
910 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
911 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
912 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
913 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
914 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
916 ps
.KernelStartPointer0
= params
->wm_prog_kernel
+
917 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
918 ps
.KernelStartPointer1
= params
->wm_prog_kernel
+
919 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
920 ps
.KernelStartPointer2
= params
->wm_prog_kernel
+
921 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
923 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
925 /* Gen7 hardware gets angry if we don't enable at least one dispatch
926 * mode, so just enable 16-pixel dispatch if we don't have a program.
928 ps
._16PixelDispatchEnable
= true;
931 if (params
->src
.enabled
)
932 ps
.SamplerCount
= 1; /* Up to 4 samplers */
934 switch (params
->fast_clear_op
) {
935 case ISL_AUX_OP_NONE
:
937 case ISL_AUX_OP_FULL_RESOLVE
:
938 ps
.RenderTargetResolveEnable
= true;
940 case ISL_AUX_OP_FAST_CLEAR
:
941 ps
.RenderTargetFastClearEnable
= true;
944 unreachable("Invalid fast clear op");
948 #else /* GEN_GEN <= 6 */
950 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
951 wm
.MaximumNumberofThreads
=
952 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
954 switch (params
->hiz_op
) {
955 case ISL_AUX_OP_FAST_CLEAR
:
956 wm
.DepthBufferClear
= true;
958 case ISL_AUX_OP_FULL_RESOLVE
:
959 wm
.DepthBufferResolveEnable
= true;
961 case ISL_AUX_OP_AMBIGUATE
:
962 wm
.HierarchicalDepthBufferResolveEnable
= true;
964 case ISL_AUX_OP_NONE
:
967 unreachable("not reached");
971 wm
.ThreadDispatchEnable
= true;
973 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
974 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
975 wm
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
977 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
978 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 0);
979 wm
.DispatchGRFStartRegisterForConstantSetupData1
=
980 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 1);
981 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
982 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 2);
984 wm
.KernelStartPointer0
= params
->wm_prog_kernel
+
985 brw_wm_prog_data_prog_offset(prog_data
, wm
, 0);
986 wm
.KernelStartPointer1
= params
->wm_prog_kernel
+
987 brw_wm_prog_data_prog_offset(prog_data
, wm
, 1);
988 wm
.KernelStartPointer2
= params
->wm_prog_kernel
+
989 brw_wm_prog_data_prog_offset(prog_data
, wm
, 2);
991 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
994 if (params
->src
.enabled
) {
995 wm
.SamplerCount
= 1; /* Up to 4 samplers */
996 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
999 if (params
->num_samples
> 1) {
1000 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1001 wm
.MultisampleDispatchMode
=
1002 (prog_data
&& prog_data
->persample_dispatch
) ?
1003 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
1005 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1006 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1010 #endif /* GEN_GEN */
1014 blorp_emit_blend_state(struct blorp_batch
*batch
,
1015 const struct blorp_params
*params
)
1017 struct GENX(BLEND_STATE
) blend
;
1018 memset(&blend
, 0, sizeof(blend
));
1021 int size
= GENX(BLEND_STATE_length
) * 4;
1022 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
1023 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
1024 uint32_t *pos
= state
;
1026 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
1027 pos
+= GENX(BLEND_STATE_length
);
1029 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
1030 struct GENX(BLEND_STATE_ENTRY
) entry
= {
1031 .PreBlendColorClampEnable
= true,
1032 .PostBlendColorClampEnable
= true,
1033 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
1035 .WriteDisableRed
= params
->color_write_disable
[0],
1036 .WriteDisableGreen
= params
->color_write_disable
[1],
1037 .WriteDisableBlue
= params
->color_write_disable
[2],
1038 .WriteDisableAlpha
= params
->color_write_disable
[3],
1040 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
1041 pos
+= GENX(BLEND_STATE_ENTRY_length
);
1044 blorp_flush_range(batch
, state
, size
);
1047 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
1048 sp
.BlendStatePointer
= offset
;
1050 sp
.BlendStatePointerValid
= true;
1056 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
1057 ps_blend
.HasWriteableRT
= true;
1065 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
1066 MAYBE_UNUSED
const struct blorp_params
*params
)
1069 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
1071 cc
.StencilReferenceValue
= params
->stencil_ref
;
1076 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
1077 sp
.ColorCalcStatePointer
= offset
;
1079 sp
.ColorCalcStatePointerValid
= true;
1088 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
1089 const struct blorp_params
*params
)
1092 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
1093 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
1096 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
1099 if (params
->depth
.enabled
) {
1100 ds
.DepthBufferWriteEnable
= true;
1102 switch (params
->hiz_op
) {
1103 case ISL_AUX_OP_NONE
:
1104 ds
.DepthTestEnable
= true;
1105 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
1108 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
1109 * - 7.5.3.1 Depth Buffer Clear
1110 * - 7.5.3.2 Depth Buffer Resolve
1111 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1113 case ISL_AUX_OP_FULL_RESOLVE
:
1114 ds
.DepthTestEnable
= true;
1115 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
1118 case ISL_AUX_OP_FAST_CLEAR
:
1119 case ISL_AUX_OP_AMBIGUATE
:
1120 ds
.DepthTestEnable
= false;
1122 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1123 unreachable("Invalid HIZ op");
1127 if (params
->stencil
.enabled
) {
1128 ds
.StencilBufferWriteEnable
= true;
1129 ds
.StencilTestEnable
= true;
1130 ds
.DoubleSidedStencilEnable
= false;
1132 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1133 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1135 ds
.StencilWriteMask
= params
->stencil_mask
;
1137 ds
.StencilReferenceValue
= params
->stencil_ref
;
1142 uint32_t offset
= 0;
1143 uint32_t *dw
= blorp_emit_dwords(batch
,
1144 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1148 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1151 void *state
= blorp_alloc_dynamic_state(batch
,
1152 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1154 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1155 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1159 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1160 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1168 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1169 const struct blorp_params
*params
)
1171 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1172 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1175 /* The PRM says that this bit is valid only for DX9:
1177 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1178 * should not have any effect by setting or not setting this bit.
1180 ms
.PixelPositionOffsetEnable
= false;
1183 switch (params
->num_samples
) {
1185 GEN_SAMPLE_POS_1X(ms
.Sample
);
1188 GEN_SAMPLE_POS_2X(ms
.Sample
);
1191 GEN_SAMPLE_POS_4X(ms
.Sample
);
1194 GEN_SAMPLE_POS_8X(ms
.Sample
);
1200 GEN_SAMPLE_POS_4X(ms
.Sample
);
1202 ms
.PixelLocation
= CENTER
;
1207 blorp_emit_pipeline(struct blorp_batch
*batch
,
1208 const struct blorp_params
*params
)
1210 uint32_t blend_state_offset
= 0;
1211 uint32_t color_calc_state_offset
;
1212 uint32_t depth_stencil_state_offset
;
1214 emit_urb_config(batch
, params
);
1216 if (params
->wm_prog_data
) {
1217 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1219 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1220 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1223 /* 3DSTATE_CC_STATE_POINTERS
1225 * The pointer offsets are relative to
1226 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1228 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1230 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1231 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1232 * one CC_STATE_POINTERS packet so we have to emit that here.
1234 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1235 cc
.BLEND_STATEChange
= true;
1236 cc
.ColorCalcStatePointerValid
= true;
1237 cc
.DEPTH_STENCIL_STATEChange
= true;
1238 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1239 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1240 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1243 (void)blend_state_offset
;
1244 (void)color_calc_state_offset
;
1245 (void)depth_stencil_state_offset
;
1248 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1250 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1251 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1253 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1254 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1256 if (params
->src
.enabled
)
1257 blorp_emit_sampler_state(batch
);
1259 blorp_emit_3dstate_multisample(batch
, params
);
1261 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1262 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1265 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1266 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1268 * [DevSNB] A pipeline flush must be programmed prior to a
1269 * 3DSTATE_VS command that causes the VS Function Enable to
1270 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1271 * command with CS stall bit set and a post sync operation.
1273 * We've already done one at the start of the BLORP operation.
1275 blorp_emit_vs_config(batch
, params
);
1277 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1278 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1279 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1280 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1282 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1284 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1285 clip
.PerspectiveDivideDisable
= true;
1288 blorp_emit_sf_config(batch
, params
);
1289 blorp_emit_ps_config(batch
, params
);
1291 blorp_emit_cc_viewport(batch
);
1294 /******** This is the end of the pipeline setup code ********/
1296 #endif /* GEN_GEN >= 6 */
1300 blorp_emit_memcpy(struct blorp_batch
*batch
,
1301 struct blorp_address dst
,
1302 struct blorp_address src
,
1305 assert(size
% 4 == 0);
1307 for (unsigned dw
= 0; dw
< size
; dw
+= 4) {
1309 blorp_emit(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
1310 cp
.DestinationMemoryAddress
= dst
;
1311 cp
.SourceMemoryAddress
= src
;
1314 /* IVB does not have a general purpose register for command streamer
1315 * commands. Therefore, we use an alternate temporary register.
1317 #define BLORP_TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
1318 blorp_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), load
) {
1319 load
.RegisterAddress
= BLORP_TEMP_REG
;
1320 load
.MemoryAddress
= src
;
1322 blorp_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), store
) {
1323 store
.RegisterAddress
= BLORP_TEMP_REG
;
1324 store
.MemoryAddress
= dst
;
1326 #undef BLORP_TEMP_REG
1335 blorp_emit_surface_state(struct blorp_batch
*batch
,
1336 const struct brw_blorp_surface_info
*surface
,
1337 enum isl_aux_op aux_op
,
1338 void *state
, uint32_t state_offset
,
1339 const bool color_write_disables
[4],
1340 bool is_render_target
)
1342 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1343 struct isl_surf surf
= surface
->surf
;
1345 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1346 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1347 assert(surf
.logical_level0_px
.height
== 1);
1348 surf
.dim
= ISL_SURF_DIM_2D
;
1351 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1352 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1353 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1354 aux_usage
= ISL_AUX_USAGE_NONE
;
1356 isl_channel_mask_t write_disable_mask
= 0;
1357 if (is_render_target
&& GEN_GEN
<= 5) {
1358 if (color_write_disables
[0])
1359 write_disable_mask
|= ISL_CHANNEL_RED_BIT
;
1360 if (color_write_disables
[1])
1361 write_disable_mask
|= ISL_CHANNEL_GREEN_BIT
;
1362 if (color_write_disables
[2])
1363 write_disable_mask
|= ISL_CHANNEL_BLUE_BIT
;
1364 if (color_write_disables
[3])
1365 write_disable_mask
|= ISL_CHANNEL_ALPHA_BIT
;
1368 const bool use_clear_address
=
1369 GEN_GEN
>= 10 && (surface
->clear_color_addr
.buffer
!= NULL
);
1371 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1372 .surf
= &surf
, .view
= &surface
->view
,
1373 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1375 blorp_get_surface_address(batch
, surface
->addr
),
1376 .aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
? 0 :
1377 blorp_get_surface_address(batch
, surface
->aux_addr
),
1378 .clear_address
= !use_clear_address
? 0 :
1379 blorp_get_surface_address(batch
,
1380 surface
->clear_color_addr
),
1381 .mocs
= surface
->addr
.mocs
,
1382 .clear_color
= surface
->clear_color
,
1383 .use_clear_address
= use_clear_address
,
1384 .write_disables
= write_disable_mask
);
1386 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1389 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1390 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1391 * used to store other information. This should be ok, however, because
1392 * surface buffer addresses are always 4K page alinged.
1394 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1395 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1396 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1397 surface
->aux_addr
, *aux_addr
);
1400 if (aux_usage
!= ISL_AUX_USAGE_NONE
&& surface
->clear_color_addr
.buffer
) {
1402 assert((surface
->clear_color_addr
.offset
& 0x3f) == 0);
1403 uint32_t *clear_addr
= state
+ isl_dev
->ss
.clear_color_state_offset
;
1404 blorp_surface_reloc(batch
, state_offset
+
1405 isl_dev
->ss
.clear_color_state_offset
,
1406 surface
->clear_color_addr
, *clear_addr
);
1408 /* Fast clears just whack the AUX surface and don't actually use the
1409 * clear color for anything. We can avoid the MI memcpy on that case.
1411 if (aux_op
!= ISL_AUX_OP_FAST_CLEAR
) {
1412 struct blorp_address dst_addr
= blorp_get_surface_base_address(batch
);
1413 dst_addr
.offset
+= state_offset
+ isl_dev
->ss
.clear_value_offset
;
1414 blorp_emit_memcpy(batch
, dst_addr
, surface
->clear_color_addr
,
1415 isl_dev
->ss
.clear_value_size
);
1418 unreachable("Fast clears are only supported on gen7+");
1422 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1426 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1427 const struct brw_blorp_surface_info
*surface
,
1430 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1431 .SurfaceType
= SURFTYPE_NULL
,
1432 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1433 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1434 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1435 .MIPCountLOD
= surface
->view
.base_level
,
1436 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1437 .Depth
= surface
->view
.array_len
- 1,
1438 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1440 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1444 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1450 .TiledSurface
= true,
1454 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1456 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1460 blorp_emit_surface_states(struct blorp_batch
*batch
,
1461 const struct blorp_params
*params
)
1463 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1464 uint32_t bind_offset
= 0, surface_offsets
[2];
1465 void *surface_maps
[2];
1467 MAYBE_UNUSED
bool has_indirect_clear_color
= false;
1468 if (params
->use_pre_baked_binding_table
) {
1469 bind_offset
= params
->pre_baked_binding_table_offset
;
1471 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1472 blorp_alloc_binding_table(batch
, num_surfaces
,
1473 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1474 &bind_offset
, surface_offsets
, surface_maps
);
1476 if (params
->dst
.enabled
) {
1477 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1478 params
->fast_clear_op
,
1479 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1480 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1481 params
->color_write_disable
, true);
1482 if (params
->dst
.clear_color_addr
.buffer
!= NULL
)
1483 has_indirect_clear_color
= true;
1485 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1486 const struct brw_blorp_surface_info
*surface
=
1487 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1488 blorp_emit_null_surface_state(batch
, surface
,
1489 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1492 if (params
->src
.enabled
) {
1493 blorp_emit_surface_state(batch
, ¶ms
->src
,
1494 params
->fast_clear_op
,
1495 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1496 surface_offsets
[BLORP_TEXTURE_BT_INDEX
],
1498 if (params
->src
.clear_color_addr
.buffer
!= NULL
)
1499 has_indirect_clear_color
= true;
1504 if (has_indirect_clear_color
) {
1505 /* Updating a surface state object may require that the state cache be
1506 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1509 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1510 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1511 * modified [...], the L1 state cache must be invalidated to ensure
1512 * the new surface or sampler state is fetched from system memory.
1514 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1515 pipe
.StateCacheInvalidationEnable
= true;
1521 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1522 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1523 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1524 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1526 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1527 bt
.PointertoPSBindingTable
= bind_offset
;
1530 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1531 bt
.PSBindingTableChange
= true;
1532 bt
.PointertoPSBindingTable
= bind_offset
;
1535 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1536 bt
.PointertoPSBindingTable
= bind_offset
;
1542 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
1543 const struct blorp_params
*params
)
1545 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1547 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
1551 struct isl_depth_stencil_hiz_emit_info info
= { };
1553 if (params
->depth
.enabled
) {
1554 info
.view
= ¶ms
->depth
.view
;
1555 info
.mocs
= params
->depth
.addr
.mocs
;
1556 } else if (params
->stencil
.enabled
) {
1557 info
.view
= ¶ms
->stencil
.view
;
1558 info
.mocs
= params
->stencil
.addr
.mocs
;
1561 if (params
->depth
.enabled
) {
1562 info
.depth_surf
= ¶ms
->depth
.surf
;
1564 info
.depth_address
=
1565 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
1566 params
->depth
.addr
, 0);
1568 info
.hiz_usage
= params
->depth
.aux_usage
;
1569 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
1570 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
1572 struct blorp_address hiz_address
= params
->depth
.aux_addr
;
1574 /* Sandy bridge hardware does not technically support mipmapped HiZ.
1575 * However, we have a special layout that allows us to make it work
1576 * anyway by manually offsetting to the specified miplevel.
1578 assert(info
.hiz_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1580 isl_surf_get_image_offset_B_tile_sa(info
.hiz_surf
,
1581 info
.view
->base_level
, 0, 0,
1582 &offset_B
, NULL
, NULL
);
1583 hiz_address
.offset
+= offset_B
;
1587 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
1590 info
.depth_clear_value
= params
->depth
.clear_color
.f32
[0];
1594 if (params
->stencil
.enabled
) {
1595 info
.stencil_surf
= ¶ms
->stencil
.surf
;
1597 struct blorp_address stencil_address
= params
->stencil
.addr
;
1599 /* Sandy bridge hardware does not technically support mipmapped stencil.
1600 * However, we have a special layout that allows us to make it work
1601 * anyway by manually offsetting to the specified miplevel.
1603 assert(info
.stencil_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1605 isl_surf_get_image_offset_B_tile_sa(info
.stencil_surf
,
1606 info
.view
->base_level
, 0, 0,
1607 &offset_B
, NULL
, NULL
);
1608 stencil_address
.offset
+= offset_B
;
1611 info
.stencil_address
=
1612 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
1613 stencil_address
, 0);
1616 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
1620 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1621 * depth/stencil buffer extents are ignored to handle APIs which perform
1622 * clearing operations without such information.
1625 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1626 const struct blorp_params
*params
)
1628 /* We should be performing an operation on a depth or stencil buffer.
1630 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1632 /* The stencil buffer should only be enabled if a fast clear operation is
1635 if (params
->stencil
.enabled
)
1636 assert(params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
);
1638 /* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
1640 * 3DSTATE_MULTISAMPLE packet must be used prior to this packet to change
1641 * the Number of Multisamples. This packet must not be used to change
1642 * Number of Multisamples in a rendering sequence.
1644 * Since HIZ may be the first thing in a batch buffer, play safe and always
1645 * emit 3DSTATE_MULTISAMPLE.
1647 blorp_emit_3dstate_multisample(batch
, params
);
1649 /* From the BDW PRM Volume 7, Depth Buffer Clear:
1651 * The clear value must be between the min and max depth values
1652 * (inclusive) defined in the CC_VIEWPORT. If the depth buffer format is
1653 * D32_FLOAT, then +/-DENORM values are also allowed.
1655 * Set the bounds to match our hardware limits, [0.0, 1.0].
1657 if (params
->depth
.enabled
&& params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
) {
1658 assert(params
->depth
.clear_color
.f32
[0] >= 0.0f
);
1659 assert(params
->depth
.clear_color
.f32
[0] <= 1.0f
);
1660 blorp_emit_cc_viewport(batch
);
1663 /* According to the SKL PRM formula for WM_INT::ThreadDispatchEnable, the
1664 * 3DSTATE_WM::ForceThreadDispatchEnable field can force WM thread dispatch
1665 * even when WM_HZ_OP is active. However, WM thread dispatch is normally
1666 * disabled for HiZ ops and it appears that force-enabling it can lead to
1667 * GPU hangs on at least Skylake. Since we don't know the current state of
1668 * the 3DSTATE_WM packet, just emit a dummy one prior to 3DSTATE_WM_HZ_OP.
1670 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
1672 /* If we can't alter the depth stencil config and multiple layers are
1673 * involved, the HiZ op will fail. This is because the op requires that a
1674 * new config is emitted for each additional layer.
1676 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1677 assert(params
->num_layers
<= 1);
1679 blorp_emit_depth_stencil_config(batch
, params
);
1682 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1683 switch (params
->hiz_op
) {
1684 case ISL_AUX_OP_FAST_CLEAR
:
1685 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1686 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1687 hzp
.StencilClearValue
= params
->stencil_ref
;
1688 hzp
.FullSurfaceDepthandStencilClear
= params
->full_surface_hiz_op
;
1690 case ISL_AUX_OP_FULL_RESOLVE
:
1691 assert(params
->full_surface_hiz_op
);
1692 hzp
.DepthBufferResolveEnable
= true;
1694 case ISL_AUX_OP_AMBIGUATE
:
1695 assert(params
->full_surface_hiz_op
);
1696 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1698 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1699 case ISL_AUX_OP_NONE
:
1700 unreachable("Invalid HIZ op");
1703 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1704 hzp
.SampleMask
= 0xFFFF;
1706 /* Due to a hardware issue, this bit MBZ */
1707 assert(hzp
.ScissorRectangleEnable
== false);
1709 /* Contrary to the HW docs both fields are inclusive */
1710 hzp
.ClearRectangleXMin
= params
->x0
;
1711 hzp
.ClearRectangleYMin
= params
->y0
;
1713 /* Contrary to the HW docs both fields are exclusive */
1714 hzp
.ClearRectangleXMax
= params
->x1
;
1715 hzp
.ClearRectangleYMax
= params
->y1
;
1718 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1719 * to “Write Immediate Data” enabled.
1721 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1722 pc
.PostSyncOperation
= WriteImmediateData
;
1723 pc
.Address
= blorp_get_workaround_page(batch
);
1726 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1731 blorp_update_clear_color(struct blorp_batch
*batch
,
1732 const struct brw_blorp_surface_info
*info
,
1735 if (info
->clear_color_addr
.buffer
&& op
== ISL_AUX_OP_FAST_CLEAR
) {
1737 for (int i
= 0; i
< 4; i
++) {
1738 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1739 sdi
.Address
= info
->clear_color_addr
;
1740 sdi
.Address
.offset
+= i
* 4;
1741 sdi
.ImmediateData
= info
->clear_color
.u32
[i
];
1745 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1746 sdi
.Address
= info
->clear_color_addr
;
1747 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
1748 ISL_CHANNEL_SELECT_GREEN
<< 22 |
1749 ISL_CHANNEL_SELECT_BLUE
<< 19 |
1750 ISL_CHANNEL_SELECT_ALPHA
<< 16;
1751 if (isl_format_has_int_channel(info
->view
.format
)) {
1752 for (unsigned i
= 0; i
< 4; i
++) {
1753 assert(info
->clear_color
.u32
[i
] == 0 ||
1754 info
->clear_color
.u32
[i
] == 1);
1756 sdi
.ImmediateData
|= (info
->clear_color
.u32
[0] != 0) << 31;
1757 sdi
.ImmediateData
|= (info
->clear_color
.u32
[1] != 0) << 30;
1758 sdi
.ImmediateData
|= (info
->clear_color
.u32
[2] != 0) << 29;
1759 sdi
.ImmediateData
|= (info
->clear_color
.u32
[3] != 0) << 28;
1761 for (unsigned i
= 0; i
< 4; i
++) {
1762 assert(info
->clear_color
.f32
[i
] == 0.0f
||
1763 info
->clear_color
.f32
[i
] == 1.0f
);
1765 sdi
.ImmediateData
|= (info
->clear_color
.f32
[0] != 0.0f
) << 31;
1766 sdi
.ImmediateData
|= (info
->clear_color
.f32
[1] != 0.0f
) << 30;
1767 sdi
.ImmediateData
|= (info
->clear_color
.f32
[2] != 0.0f
) << 29;
1768 sdi
.ImmediateData
|= (info
->clear_color
.f32
[3] != 0.0f
) << 28;
1776 * \brief Execute a blit or render pass operation.
1778 * To execute the operation, this function manually constructs and emits a
1779 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1780 * constructing and after emitting the batch.
1782 * This function alters no GL state.
1785 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1787 if (!(batch
->flags
& BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
)) {
1788 blorp_update_clear_color(batch
, ¶ms
->dst
, params
->fast_clear_op
);
1789 blorp_update_clear_color(batch
, ¶ms
->depth
, params
->hiz_op
);
1793 if (params
->hiz_op
!= ISL_AUX_OP_NONE
) {
1794 blorp_emit_gen8_hiz_op(batch
, params
);
1799 blorp_emit_vertex_buffers(batch
, params
);
1800 blorp_emit_vertex_elements(batch
, params
);
1802 blorp_emit_pipeline(batch
, params
);
1804 blorp_emit_surface_states(batch
, params
);
1806 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1807 blorp_emit_depth_stencil_config(batch
, params
);
1809 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1810 prim
.VertexAccessType
= SEQUENTIAL
;
1811 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1813 prim
.PredicateEnable
= batch
->flags
& BLORP_BATCH_PREDICATE_ENABLE
;
1815 prim
.VertexCountPerInstance
= 3;
1816 prim
.InstanceCount
= params
->num_layers
;
1820 #endif /* BLORP_GENX_EXEC_H */